2 * Configuation settings for the Freescale MCF53017EVB.
4 * Copyright (C) 2004-2008 Freescale Semiconductor, Inc.
5 * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
7 * SPDX-License-Identifier: GPL-2.0+
11 * board/config.h - configuration options, board specific
18 * High Level Configuration Options
22 #define CONFIG_MCFUART
23 #define CONFIG_SYS_UART_PORT (0)
24 #define CONFIG_BAUDRATE 115200
26 #undef CONFIG_WATCHDOG
27 #define CONFIG_WATCHDOG_TIMEOUT 5000
29 /* Command line configuration */
30 #define CONFIG_CMD_DATE
31 #define CONFIG_CMD_REGINFO
33 #define CONFIG_SYS_UNIFY_CACHE
38 # define CONFIG_MII_INIT 1
39 # define CONFIG_SYS_DISCOVER_PHY
40 # define CONFIG_SYS_RX_ETH_BUFFER 8
41 # define CONFIG_SYS_TX_ETH_BUFFER 8
42 # define CONFIG_SYS_FEC_BUF_USE_SRAM
43 # define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
44 # define CONFIG_HAS_ETH1
46 # define CONFIG_SYS_FEC0_PINMUX 0
47 # define CONFIG_SYS_FEC0_MIIBASE CONFIG_SYS_FEC0_IOBASE
48 # define CONFIG_SYS_FEC1_PINMUX 0
49 # define CONFIG_SYS_FEC1_MIIBASE CONFIG_SYS_FEC1_IOBASE
50 # define MCFFEC_TOUT_LOOP 50000
52 # define CONFIG_BOOTARGS "root=/dev/mtdblock3 rw rootfstype=jffs2"
54 /* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */
55 # ifndef CONFIG_SYS_DISCOVER_PHY
56 # define FECDUPLEX FULL
57 # define FECSPEED _100BASET
59 # ifndef CONFIG_SYS_FAULT_ECHO_LINK_DOWN
60 # define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
62 # endif /* CONFIG_SYS_DISCOVER_PHY */
67 #define CONFIG_SYS_RTC_CNT (0x8000)
68 #define CONFIG_SYS_RTC_SETUP (RTC_OCEN_OSCBYP | RTC_OCEN_CLKEN)
75 #define CONFIG_SYS_I2C
76 #define CONFIG_SYS_I2C_FSL
77 #define CONFIG_SYS_FSL_I2C_SPEED 80000
78 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
79 #define CONFIG_SYS_FSL_I2C_OFFSET 0x58000
80 #define CONFIG_SYS_IMMR CONFIG_SYS_MBAR
82 #define CONFIG_BOOTDELAY 1 /* autoboot after 5 seconds */
83 #define CONFIG_UDP_CHECKSUM
86 # define CONFIG_IPADDR 192.162.1.2
87 # define CONFIG_NETMASK 255.255.255.0
88 # define CONFIG_SERVERIP 192.162.1.1
89 # define CONFIG_GATEWAYIP 192.162.1.1
92 #define CONFIG_HOSTNAME M53017
93 #define CONFIG_EXTRA_ENV_SETTINGS \
95 "loadaddr=40010000\0" \
96 "u-boot=u-boot.bin\0" \
97 "load=tftp ${loadaddr) ${u-boot}\0" \
98 "upd=run load; run prog\0" \
99 "prog=prot off 0 3ffff;" \
101 "cp.b ${loadaddr} 0 ${filesize};" \
105 #define CONFIG_PRAM 512 /* 512 KB */
106 #define CONFIG_SYS_LONGHELP /* undef to save memory */
108 #ifdef CONFIG_CMD_KGDB
109 # define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
111 # define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
114 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
115 #define CONFIG_SYS_MAXARGS 16 /* max number of cmd args */
116 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Arg Buf Sz */
117 #define CONFIG_SYS_LOAD_ADDR 0x40010000
119 #define CONFIG_SYS_CLK 80000000
120 #define CONFIG_SYS_CPU_CLK CONFIG_SYS_CLK * 3
122 #define CONFIG_SYS_MBAR 0xFC000000
125 * Low Level Configuration Settings
126 * (address mappings, register initial values, etc.)
127 * You should know what you are doing if you make changes here.
130 * Definitions for initial stack pointer and data area (in DPRAM)
132 #define CONFIG_SYS_INIT_RAM_ADDR 0x80000000
133 #define CONFIG_SYS_INIT_RAM_SIZE 0x20000 /* Size of used area in internal SRAM */
134 #define CONFIG_SYS_INIT_RAM_CTRL 0x221
135 #define CONFIG_SYS_GBL_DATA_OFFSET ((CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) - 0x10)
136 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
139 * Start addresses for the final memory configuration
140 * (Set up by the startup code)
141 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
143 #define CONFIG_SYS_SDRAM_BASE 0x40000000
144 #define CONFIG_SYS_SDRAM_SIZE 64 /* SDRAM size in MB */
145 #define CONFIG_SYS_SDRAM_CFG1 0x43711630
146 #define CONFIG_SYS_SDRAM_CFG2 0x56670000
147 #define CONFIG_SYS_SDRAM_CTRL 0xE1092000
148 #define CONFIG_SYS_SDRAM_EMOD 0x80010000
149 #define CONFIG_SYS_SDRAM_MODE 0x00CD0000
151 #define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE + 0x400
152 #define CONFIG_SYS_MEMTEST_END ((CONFIG_SYS_SDRAM_SIZE - 3) << 20)
154 #define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400)
155 #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
157 #define CONFIG_SYS_BOOTPARAMS_LEN 64*1024
158 #define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
161 * For booting Linux, the board info and command line data
162 * have to be in the first 8 MB of memory, since this is
163 * the maximum mapped by the Linux kernel during initialization ??
165 #define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20))
166 #define CONFIG_SYS_BOOTM_LEN (CONFIG_SYS_SDRAM_SIZE << 20)
168 /*-----------------------------------------------------------------------
171 #define CONFIG_SYS_FLASH_CFI
172 #ifdef CONFIG_SYS_FLASH_CFI
173 # define CONFIG_FLASH_CFI_DRIVER 1
174 # define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1
175 # define CONFIG_FLASH_SPANSION_S29WS_N 1
176 # define CONFIG_SYS_FLASH_SIZE 0x1000000 /* Max size that the board might have */
177 # define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
178 # define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
179 # define CONFIG_SYS_MAX_FLASH_SECT 137 /* max number of sectors on one chip */
180 # define CONFIG_SYS_FLASH_PROTECTION /* "Real" (hardware) sectors protection */
183 #define CONFIG_SYS_FLASH_BASE CONFIG_SYS_CS0_BASE
185 /* Configuration for environment
186 * Environment is embedded in u-boot in the second sector of the flash
188 #define CONFIG_ENV_OFFSET (CONFIG_SYS_FLASH_BASE + 0x40000)
189 #define CONFIG_ENV_SIZE 0x1000
190 #define CONFIG_ENV_SECT_SIZE 0x8000
191 #define CONFIG_ENV_IS_IN_FLASH 1
193 #define LDS_BOARD_TEXT \
194 . = DEFINED(env_offset) ? env_offset : .; \
195 common/env_embedded.o (.text*)
197 /*-----------------------------------------------------------------------
198 * Cache Configuration
200 #define CONFIG_SYS_CACHELINE_SIZE 16
202 #define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
203 CONFIG_SYS_INIT_RAM_SIZE - 8)
204 #define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
205 CONFIG_SYS_INIT_RAM_SIZE - 4)
206 #define CONFIG_SYS_ICACHE_INV (CF_CACR_CINVA)
207 #define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_SDRAM_BASE | \
208 CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
209 CF_ACR_EN | CF_ACR_SM_ALL)
210 #define CONFIG_SYS_CACHE_ICACR (CF_CACR_EC | CF_CACR_CINVA | \
213 /*-----------------------------------------------------------------------
214 * Chipselect bank definitions
224 #define CONFIG_SYS_CS0_BASE 0
225 #define CONFIG_SYS_CS0_MASK 0x00FF0001
226 #define CONFIG_SYS_CS0_CTRL 0x00001FA0
228 #define CONFIG_SYS_CS1_BASE 0xC0000000
229 #define CONFIG_SYS_CS1_MASK 0x00070001
230 #define CONFIG_SYS_CS1_CTRL 0x00001FA0
232 #endif /* _M53017EVB_H */