2 * Configuation settings for the Freescale MCF54418 TWR board.
4 * Copyright 2010-2012 Freescale Semiconductor, Inc.
5 * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
7 * SPDX-License-Identifier: GPL-2.0+
11 * board/config.h - configuration options, board specific
18 * High Level Configuration Options
22 #define CONFIG_MCFUART
23 #define CONFIG_SYS_UART_PORT (0)
24 #define CONFIG_SYS_BAUDRATE_TABLE { 9600 , 19200 , 38400 , 57600, 115200 }
26 #define LDS_BOARD_TEXT board/freescale/m54418twr/sbf_dram_init.o (.text*)
28 #undef CONFIG_WATCHDOG
30 #define CONFIG_TIMESTAMP /* Print image info with timestamp */
35 #define CONFIG_BOOTP_BOOTFILESIZE
36 #define CONFIG_BOOTP_BOOTPATH
37 #define CONFIG_BOOTP_GATEWAY
38 #define CONFIG_BOOTP_HOSTNAME
43 #ifdef CONFIG_CMD_NAND
44 #define CONFIG_JFFS2_NAND
45 #define CONFIG_NAND_FSL_NFC
46 #define CONFIG_SYS_NAND_BASE 0xFC0FC000
47 #define CONFIG_SYS_MAX_NAND_DEVICE 1
48 #define NAND_MAX_CHIPS CONFIG_SYS_MAX_NAND_DEVICE
49 #define CONFIG_SYS_NAND_SELECT_DEVICE
52 /* Network configuration */
56 #define CONFIG_MII_INIT 1
57 #define CONFIG_SYS_DISCOVER_PHY
58 #define CONFIG_SYS_RX_ETH_BUFFER 2
59 #define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
60 #define CONFIG_SYS_TX_ETH_BUFFER 2
61 #define CONFIG_HAS_ETH1
63 #define CONFIG_SYS_FEC0_PINMUX 0
64 #define CONFIG_SYS_FEC0_MIIBASE CONFIG_SYS_FEC0_IOBASE
65 #define CONFIG_SYS_FEC1_PINMUX 0
66 #define CONFIG_SYS_FEC1_MIIBASE CONFIG_SYS_FEC0_MIIBASE
67 #define MCFFEC_TOUT_LOOP 50000
68 #define CONFIG_SYS_FEC0_PHYADDR 0
69 #define CONFIG_SYS_FEC1_PHYADDR 1
71 #define CONFIG_ETHPRIME "FEC0"
72 #define CONFIG_IPADDR 192.168.1.2
73 #define CONFIG_NETMASK 255.255.255.0
74 #define CONFIG_SERVERIP 192.168.1.1
75 #define CONFIG_GATEWAYIP 192.168.1.1
77 #define CONFIG_SYS_FEC_BUF_USE_SRAM
78 /* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */
79 #ifndef CONFIG_SYS_DISCOVER_PHY
80 #define FECDUPLEX FULL
81 #define FECSPEED _100BASET
85 #ifndef CONFIG_SYS_FAULT_ECHO_LINK_DOWN
86 #define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
88 #endif /* CONFIG_SYS_DISCOVER_PHY */
91 #define CONFIG_HOSTNAME M54418TWR
93 #if defined(CONFIG_CF_SBF)
94 /* ST Micro serial flash */
95 #define CONFIG_SYS_LOAD_ADDR2 0x40010007
96 #define CONFIG_EXTRA_ENV_SETTINGS \
98 "inpclk=" __stringify(CONFIG_SYS_INPUT_CLKSRC) "\0" \
99 "loadaddr=0x40010000\0" \
100 "sbfhdr=sbfhdr.bin\0" \
101 "uboot=u-boot.bin\0" \
102 "load=tftp ${loadaddr} ${sbfhdr};" \
103 "tftp " __stringify(CONFIG_SYS_LOAD_ADDR2) " ${uboot} \0" \
104 "upd=run load; run prog\0" \
105 "prog=sf probe 0:1 1000000 3;" \
106 "sf erase 0 40000;" \
107 "sf write ${loadaddr} 0 40000;" \
110 #elif defined(CONFIG_SYS_NAND_BOOT)
111 #define CONFIG_EXTRA_ENV_SETTINGS \
113 "inpclk=" __stringify(CONFIG_SYS_INPUT_CLKSRC) "\0" \
114 "loadaddr=0x40010000\0" \
115 "u-boot=u-boot.bin\0" \
116 "load=tftp ${loadaddr} ${u-boot};\0" \
117 "upd=run load; run prog\0" \
118 "prog=nand device 0;" \
119 "nand erase 0 40000;" \
120 "nb_update ${loadaddr} ${filesize};" \
124 #define CONFIG_SYS_UBOOT_END 0x3FFFF
125 #define CONFIG_EXTRA_ENV_SETTINGS \
127 "inpclk=" __stringify(CONFIG_SYS_INPUT_CLKSRC) "\0" \
128 "loadaddr=40010000\0" \
129 "u-boot=u-boot.bin\0" \
130 "load=tftp ${loadaddr) ${u-boot}\0" \
131 "upd=run load; run prog\0" \
132 "prog=prot off mram" " ;" \
133 "cp.b ${loadaddr} 0 ${filesize};" \
140 #define CONFIG_RTC_MCFRRTC
141 #define CONFIG_SYS_MCFRRTC_BASE 0xFC0A8000
144 #define CONFIG_MCFTMR
148 #undef CONFIG_SYS_FSL_I2C
149 #undef CONFIG_SYS_I2C_SOFT /* I2C bit-banged */
150 /* I2C speed and slave address */
151 #define CONFIG_SYS_I2C_SPEED 80000
152 #define CONFIG_SYS_I2C_SLAVE 0x7F
153 #define CONFIG_SYS_I2C_OFFSET 0x58000
154 #define CONFIG_SYS_IMMR CONFIG_SYS_MBAR
156 /* DSPI and Serial Flash */
157 #define CONFIG_CF_DSPI
158 #define CONFIG_SERIAL_FLASH
159 #define CONFIG_HARD_SPI
160 #define CONFIG_SYS_SBFHDR_SIZE 0x7
161 #ifdef CONFIG_CMD_SPI
163 # define CONFIG_SYS_DSPI_CTAR0 (DSPI_CTAR_TRSZ(7) | \
164 DSPI_CTAR_PCSSCK_1CLK | \
165 DSPI_CTAR_PASC(0) | \
167 DSPI_CTAR_CSSCK(0) | \
170 # define CONFIG_SYS_DSPI_CTAR1 (CONFIG_SYS_DSPI_CTAR0)
171 # define CONFIG_SYS_DSPI_CTAR2 (CONFIG_SYS_DSPI_CTAR0)
174 /* Input, PCI, Flexbus, and VCO */
175 #define CONFIG_EXTRA_CLOCK
177 #define CONFIG_PRAM 2048 /* 2048 KB */
179 #define CONFIG_SYS_LONGHELP /* undef to save memory */
181 #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x10000)
183 #define CONFIG_SYS_MBAR 0xFC000000
186 * Low Level Configuration Settings
187 * (address mappings, register initial values, etc.)
188 * You should know what you are doing if you make changes here.
191 /*-----------------------------------------------------------------------
192 * Definitions for initial stack pointer and data area (in DPRAM)
194 #define CONFIG_SYS_INIT_RAM_ADDR 0x80000000
195 /* End of used area in internal SRAM */
196 #define CONFIG_SYS_INIT_RAM_SIZE 0x10000
197 #define CONFIG_SYS_INIT_RAM_CTRL 0x221
198 #define CONFIG_SYS_GBL_DATA_OFFSET ((CONFIG_SYS_INIT_RAM_SIZE - \
199 GENERATED_GBL_DATA_SIZE) - 32)
200 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
201 #define CONFIG_SYS_SBFHDR_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - 32)
203 /*-----------------------------------------------------------------------
204 * Start addresses for the final memory configuration
205 * (Set up by the startup code)
206 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
208 #define CONFIG_SYS_SDRAM_BASE 0x40000000
209 #define CONFIG_SYS_SDRAM_SIZE 128 /* SDRAM size in MB */
211 #define CONFIG_SYS_MEMTEST_START (CONFIG_SYS_SDRAM_BASE + 0x400)
212 #define CONFIG_SYS_MEMTEST_END ((CONFIG_SYS_SDRAM_SIZE - 3) << 20)
213 #define CONFIG_SYS_DRAM_TEST
215 #if defined(CONFIG_CF_SBF) || defined(CONFIG_SYS_NAND_BOOT)
216 #define CONFIG_SERIAL_BOOT
219 #if defined(CONFIG_SERIAL_BOOT)
220 #define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_TEXT_BASE + 0x400)
222 #define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400)
225 #define CONFIG_SYS_BOOTPARAMS_LEN (64 * 1024)
226 /* Reserve 256 kB for Monitor */
227 #define CONFIG_SYS_MONITOR_LEN (256 << 10)
228 /* Reserve 256 kB for malloc() */
229 #define CONFIG_SYS_MALLOC_LEN (256 << 10)
232 * For booting Linux, the board info and command line data
233 * have to be in the first 8 MB of memory, since this is
234 * the maximum mapped by the Linux kernel during initialization ??
236 /* Initial Memory map for Linux */
237 #define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + \
238 (CONFIG_SYS_SDRAM_SIZE << 20))
240 /* Configuration for environment
241 * Environment is embedded in u-boot in the second sector of the flash
243 #if !defined(CONFIG_SERIAL_BOOT) /*MRAM boot*/
244 #define CONFIG_ENV_ADDR (0x40000 - 0x1000) /*MRAM size 40000*/
245 #define CONFIG_ENV_SIZE 0x1000
248 #if defined(CONFIG_CF_SBF)
249 #define CONFIG_ENV_SPI_CS 1
250 #define CONFIG_ENV_OFFSET 0x40000
251 #define CONFIG_ENV_SIZE 0x2000
252 #define CONFIG_ENV_SECT_SIZE 0x10000
254 #if defined(CONFIG_SYS_NAND_BOOT)
255 #define CONFIG_ENV_OFFSET 0x80000
256 #define CONFIG_ENV_SIZE 0x20000
257 #define CONFIG_ENV_SECT_SIZE 0x20000
259 #undef CONFIG_ENV_OVERWRITE
261 /* FLASH organization */
262 #define CONFIG_SYS_FLASH_BASE CONFIG_SYS_CS0_BASE
264 #undef CONFIG_SYS_FLASH_CFI
265 #ifdef CONFIG_SYS_FLASH_CFI
267 #define CONFIG_FLASH_CFI_DRIVER 1
268 /* Max size that the board might have */
269 #define CONFIG_SYS_FLASH_SIZE 0x1000000
270 #define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
271 /* max number of memory banks */
272 #define CONFIG_SYS_MAX_FLASH_BANKS 1
273 /* max number of sectors on one chip */
274 #define CONFIG_SYS_MAX_FLASH_SECT 270
275 /* "Real" (hardware) sectors protection */
276 #define CONFIG_SYS_FLASH_PROTECTION
277 #define CONFIG_SYS_FLASH_CHECKSUM
278 #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_CS0_BASE }
280 /* max number of sectors on one chip */
281 #define CONFIG_SYS_MAX_FLASH_SECT 270
282 /* max number of sectors on one chip */
283 #define CONFIG_SYS_MAX_FLASH_BANKS 0
287 * This is setting for JFFS2 support in u-boot.
288 * NOTE: Enable CONFIG_CMD_JFFS2 for JFFS2 support.
290 #ifdef CONFIG_CMD_JFFS2
291 #define CONFIG_JFFS2_DEV "nand0"
292 #define CONFIG_JFFS2_PART_OFFSET (0x800000)
293 #define CONFIG_MTD_DEVICE
297 #ifdef CONFIG_CMD_UBI
298 #define CONFIG_MTD_DEVICE /* needed for mtdparts command */
299 #define CONFIG_MTD_PARTITIONS /* mtdparts and UBI support */
301 /* Cache Configuration */
302 #define CONFIG_SYS_CACHELINE_SIZE 16
303 #define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
304 CONFIG_SYS_INIT_RAM_SIZE - 8)
305 #define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
306 CONFIG_SYS_INIT_RAM_SIZE - 4)
307 #define CONFIG_SYS_ICACHE_INV (CF_CACR_BCINVA + CF_CACR_ICINVA)
308 #define CONFIG_SYS_DCACHE_INV (CF_CACR_DCINVA)
309 #define CONFIG_SYS_CACHE_ACR2 (CONFIG_SYS_SDRAM_BASE | \
310 CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
311 CF_ACR_EN | CF_ACR_SM_ALL)
312 #define CONFIG_SYS_CACHE_ICACR (CF_CACR_BEC | CF_CACR_IEC | \
313 CF_CACR_ICINVA | CF_CACR_EUSP)
314 #define CONFIG_SYS_CACHE_DCACR ((CONFIG_SYS_CACHE_ICACR | \
315 CF_CACR_DEC | CF_CACR_DDCM_P | \
316 CF_CACR_DCINVA) & ~CF_CACR_ICINVA)
318 #define CACR_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
319 CONFIG_SYS_INIT_RAM_SIZE - 12)
321 /*-----------------------------------------------------------------------
322 * Memory bank definitions
325 * CS0 - NOR Flash 16MB
334 #define CONFIG_SYS_CS0_BASE 0x00000000
335 #define CONFIG_SYS_CS0_MASK 0x000F0101
336 #define CONFIG_SYS_CS0_CTRL 0x00001D60
338 #endif /* _M54418TWR_H */