2 * Configuation settings for the Freescale MCF54455 EVB board.
4 * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
5 * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
7 * SPDX-License-Identifier: GPL-2.0+
11 * board/config.h - configuration options, board specific
18 * High Level Configuration Options
21 #define CONFIG_M54455EVB /* M54455EVB board */
23 #define CONFIG_DISPLAY_BOARDINFO
25 #define CONFIG_MCFUART
26 #define CONFIG_SYS_UART_PORT (0)
27 #define CONFIG_BAUDRATE 115200
29 #undef CONFIG_WATCHDOG
31 #define CONFIG_TIMESTAMP /* Print image info with timestamp */
36 #define CONFIG_BOOTP_BOOTFILESIZE
37 #define CONFIG_BOOTP_BOOTPATH
38 #define CONFIG_BOOTP_GATEWAY
39 #define CONFIG_BOOTP_HOSTNAME
41 /* Command line configuration */
42 #include <config_cmd_default.h>
44 #define CONFIG_CMD_BOOTD
45 #define CONFIG_CMD_CACHE
46 #define CONFIG_CMD_DATE
47 #define CONFIG_CMD_DHCP
48 #define CONFIG_CMD_ELF
49 #define CONFIG_CMD_EXT2
50 #define CONFIG_CMD_FAT
51 #define CONFIG_CMD_FLASH
52 #define CONFIG_CMD_I2C
53 #define CONFIG_CMD_IDE
54 #define CONFIG_CMD_JFFS2
55 #define CONFIG_CMD_MEMORY
56 #define CONFIG_CMD_MISC
57 #define CONFIG_CMD_MII
58 #define CONFIG_CMD_NET
60 #define CONFIG_CMD_PING
61 #define CONFIG_CMD_REGINFO
62 #define CONFIG_CMD_SPI
65 #undef CONFIG_CMD_LOADB
66 #undef CONFIG_CMD_LOADS
68 /* Network configuration */
72 # define CONFIG_MII_INIT 1
73 # define CONFIG_SYS_DISCOVER_PHY
74 # define CONFIG_SYS_RX_ETH_BUFFER 8
75 # define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
77 # define CONFIG_SYS_FEC0_PINMUX 0
78 # define CONFIG_SYS_FEC1_PINMUX 0
79 # define CONFIG_SYS_FEC0_MIIBASE CONFIG_SYS_FEC0_IOBASE
80 # define CONFIG_SYS_FEC1_MIIBASE CONFIG_SYS_FEC0_IOBASE
81 # define MCFFEC_TOUT_LOOP 50000
82 # define CONFIG_HAS_ETH1
84 # define CONFIG_BOOTDELAY 1 /* autoboot after 5 seconds */
85 # define CONFIG_BOOTARGS "root=/dev/mtdblock1 rw rootfstype=jffs2 ip=none mtdparts=physmap-flash.0:5M(kernel)ro,-(jffs2)"
86 # define CONFIG_ETHPRIME "FEC0"
87 # define CONFIG_IPADDR 192.162.1.2
88 # define CONFIG_NETMASK 255.255.255.0
89 # define CONFIG_SERVERIP 192.162.1.1
90 # define CONFIG_GATEWAYIP 192.162.1.1
92 /* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */
93 # ifndef CONFIG_SYS_DISCOVER_PHY
94 # define FECDUPLEX FULL
95 # define FECSPEED _100BASET
97 # ifndef CONFIG_SYS_FAULT_ECHO_LINK_DOWN
98 # define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
100 # endif /* CONFIG_SYS_DISCOVER_PHY */
103 #define CONFIG_HOSTNAME M54455EVB
104 #ifdef CONFIG_SYS_STMICRO_BOOT
105 /* ST Micro serial flash */
106 #define CONFIG_SYS_LOAD_ADDR2 0x40010013
107 #define CONFIG_EXTRA_ENV_SETTINGS \
109 "inpclk=" __stringify(CONFIG_SYS_INPUT_CLKSRC) "\0" \
110 "loadaddr=0x40010000\0" \
111 "sbfhdr=sbfhdr.bin\0" \
112 "uboot=u-boot.bin\0" \
113 "load=tftp ${loadaddr} ${sbfhdr};" \
114 "tftp " __stringify(CONFIG_SYS_LOAD_ADDR2) " ${uboot} \0" \
115 "upd=run load; run prog\0" \
116 "prog=sf probe 0:1 1000000 3;" \
117 "sf erase 0 30000;" \
118 "sf write ${loadaddr} 0 0x30000;" \
122 /* Atmel and Intel */
123 #ifdef CONFIG_SYS_ATMEL_BOOT
124 # define CONFIG_SYS_UBOOT_END 0x0403FFFF
125 #elif defined(CONFIG_SYS_INTEL_BOOT)
126 # define CONFIG_SYS_UBOOT_END 0x3FFFF
128 #define CONFIG_EXTRA_ENV_SETTINGS \
130 "inpclk=" __stringify(CONFIG_SYS_INPUT_CLKSRC) "\0" \
131 "loadaddr=0x40010000\0" \
132 "uboot=u-boot.bin\0" \
133 "load=tftp ${loadaddr} ${uboot}\0" \
134 "upd=run load; run prog\0" \
135 "prog=prot off " __stringify(CONFIG_SYS_FLASH_BASE) \
136 " " __stringify(CONFIG_SYS_UBOOT_END) ";" \
137 "era " __stringify(CONFIG_SYS_FLASH_BASE) " " \
138 __stringify(CONFIG_SYS_UBOOT_END) ";" \
139 "cp.b ${loadaddr} " __stringify(CONFIG_SYS_FLASH_BASE) \
140 " ${filesize}; save\0" \
144 /* ATA configuration */
145 #define CONFIG_ISO_PARTITION
146 #define CONFIG_DOS_PARTITION
147 #define CONFIG_IDE_RESET 1
148 #define CONFIG_IDE_PREINIT 1
152 #define CONFIG_SYS_IDE_MAXBUS 1
153 #define CONFIG_SYS_IDE_MAXDEVICE 2
155 #define CONFIG_SYS_ATA_BASE_ADDR 0x90000000
156 #define CONFIG_SYS_ATA_IDE0_OFFSET 0
158 #define CONFIG_SYS_ATA_DATA_OFFSET 0xA0 /* Offset for data I/O */
159 #define CONFIG_SYS_ATA_REG_OFFSET 0xA0 /* Offset for normal register accesses */
160 #define CONFIG_SYS_ATA_ALT_OFFSET 0xC0 /* Offset for alternate registers */
161 #define CONFIG_SYS_ATA_STRIDE 4 /* Interval between registers */
164 #define CONFIG_MCFRTC
166 #define CONFIG_SYS_RTC_OSCILLATOR (32 * CONFIG_SYS_HZ)
169 #define CONFIG_MCFTMR
173 #define CONFIG_SYS_I2C
174 #define CONFIG_SYS_I2C_FSL
175 #define CONFIG_SYS_FSL_I2C_SPEED 80000
176 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
177 #define CONFIG_SYS_FSL_I2C_OFFSET 0x58000
178 #define CONFIG_SYS_IMMR CONFIG_SYS_MBAR
180 /* DSPI and Serial Flash */
181 #define CONFIG_CF_SPI
182 #define CONFIG_CF_DSPI
183 #define CONFIG_HARD_SPI
184 #define CONFIG_SYS_SBFHDR_SIZE 0x13
185 #ifdef CONFIG_CMD_SPI
186 # define CONFIG_SPI_FLASH
187 # define CONFIG_SPI_FLASH_STMICRO
189 # define CONFIG_SYS_DSPI_CTAR0 (DSPI_CTAR_TRSZ(7) | \
190 DSPI_CTAR_PCSSCK_1CLK | \
191 DSPI_CTAR_PASC(0) | \
193 DSPI_CTAR_CSSCK(0) | \
199 #ifdef CONFIG_CMD_PCI
201 #define CONFIG_PCI_PNP 1
202 #define CONFIG_PCIAUTO_SKIP_HOST_BRIDGE 1
204 #define CONFIG_SYS_PCI_CACHE_LINE_SIZE 4
206 #define CONFIG_SYS_PCI_MEM_BUS 0xA0000000
207 #define CONFIG_SYS_PCI_MEM_PHYS CONFIG_SYS_PCI_MEM_BUS
208 #define CONFIG_SYS_PCI_MEM_SIZE 0x10000000
210 #define CONFIG_SYS_PCI_IO_BUS 0xB1000000
211 #define CONFIG_SYS_PCI_IO_PHYS CONFIG_SYS_PCI_IO_BUS
212 #define CONFIG_SYS_PCI_IO_SIZE 0x01000000
214 #define CONFIG_SYS_PCI_CFG_BUS 0xB0000000
215 #define CONFIG_SYS_PCI_CFG_PHYS CONFIG_SYS_PCI_CFG_BUS
216 #define CONFIG_SYS_PCI_CFG_SIZE 0x01000000
219 /* FPGA - Spartan 2 */
222 #define CONFIG_FPGA_COUNT 1
223 #define CONFIG_SYS_FPGA_PROG_FEEDBACK
224 #define CONFIG_SYS_FPGA_CHECK_CTRLC
227 /* Input, PCI, Flexbus, and VCO */
228 #define CONFIG_EXTRA_CLOCK
230 #define CONFIG_PRAM 2048 /* 2048 KB */
232 #define CONFIG_SYS_PROMPT "-> "
233 #define CONFIG_SYS_LONGHELP /* undef to save memory */
235 #if defined(CONFIG_CMD_KGDB)
236 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
238 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
240 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
241 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */
242 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
244 #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x10000)
246 #define CONFIG_SYS_MBAR 0xFC000000
249 * Low Level Configuration Settings
250 * (address mappings, register initial values, etc.)
251 * You should know what you are doing if you make changes here.
254 /*-----------------------------------------------------------------------
255 * Definitions for initial stack pointer and data area (in DPRAM)
257 #define CONFIG_SYS_INIT_RAM_ADDR 0x80000000
258 #define CONFIG_SYS_INIT_RAM_SIZE 0x8000 /* Size of used area in internal SRAM */
259 #define CONFIG_SYS_INIT_RAM_CTRL 0x221
260 #define CONFIG_SYS_GBL_DATA_OFFSET ((CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) - 32)
261 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
262 #define CONFIG_SYS_SBFHDR_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - 32)
264 /*-----------------------------------------------------------------------
265 * Start addresses for the final memory configuration
266 * (Set up by the startup code)
267 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
269 #define CONFIG_SYS_SDRAM_BASE 0x40000000
270 #define CONFIG_SYS_SDRAM_BASE1 0x48000000
271 #define CONFIG_SYS_SDRAM_SIZE 256 /* SDRAM size in MB */
272 #define CONFIG_SYS_SDRAM_CFG1 0x65311610
273 #define CONFIG_SYS_SDRAM_CFG2 0x59670000
274 #define CONFIG_SYS_SDRAM_CTRL 0xEA0B2000
275 #define CONFIG_SYS_SDRAM_EMOD 0x40010000
276 #define CONFIG_SYS_SDRAM_MODE 0x00010033
277 #define CONFIG_SYS_SDRAM_DRV_STRENGTH 0xAA
279 #define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE + 0x400
280 #define CONFIG_SYS_MEMTEST_END ((CONFIG_SYS_SDRAM_SIZE - 3) << 20)
283 # define CONFIG_SERIAL_BOOT
284 # define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_TEXT_BASE + 0x400)
286 # define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400)
288 #define CONFIG_SYS_BOOTPARAMS_LEN 64*1024
289 #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
291 /* Reserve 256 kB for malloc() */
292 #define CONFIG_SYS_MALLOC_LEN (256 << 10)
295 * For booting Linux, the board info and command line data
296 * have to be in the first 8 MB of memory, since this is
297 * the maximum mapped by the Linux kernel during initialization ??
299 /* Initial Memory map for Linux */
300 #define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20))
303 * Configuration for environment
304 * Environment is not embedded in u-boot. First time runing may have env
305 * crc error warning if there is no correct environment on the flash.
308 # define CONFIG_ENV_IS_IN_SPI_FLASH
309 # define CONFIG_ENV_SPI_CS 1
311 # define CONFIG_ENV_IS_IN_FLASH 1
313 #undef CONFIG_ENV_OVERWRITE
315 /*-----------------------------------------------------------------------
318 #ifdef CONFIG_SYS_STMICRO_BOOT
319 # define CONFIG_SYS_FLASH_BASE CONFIG_SYS_CS0_BASE
320 # define CONFIG_SYS_FLASH0_BASE CONFIG_SYS_CS1_BASE
321 # define CONFIG_ENV_OFFSET 0x30000
322 # define CONFIG_ENV_SIZE 0x2000
323 # define CONFIG_ENV_SECT_SIZE 0x10000
325 #ifdef CONFIG_SYS_ATMEL_BOOT
326 # define CONFIG_SYS_FLASH_BASE CONFIG_SYS_CS0_BASE
327 # define CONFIG_SYS_FLASH0_BASE CONFIG_SYS_CS0_BASE
328 # define CONFIG_SYS_FLASH1_BASE CONFIG_SYS_CS1_BASE
329 # define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x40000)
330 # define CONFIG_ENV_SIZE 0x2000
331 # define CONFIG_ENV_SECT_SIZE 0x10000
333 #ifdef CONFIG_SYS_INTEL_BOOT
334 # define CONFIG_SYS_FLASH_BASE CONFIG_SYS_CS0_BASE
335 # define CONFIG_SYS_FLASH0_BASE CONFIG_SYS_CS0_BASE
336 # define CONFIG_SYS_FLASH1_BASE CONFIG_SYS_CS1_BASE
337 # define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x40000)
338 # define CONFIG_ENV_SIZE 0x2000
339 # define CONFIG_ENV_SECT_SIZE 0x20000
342 #define CONFIG_SYS_FLASH_CFI
343 #ifdef CONFIG_SYS_FLASH_CFI
345 # define CONFIG_FLASH_CFI_DRIVER 1
346 # define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1
347 # define CONFIG_SYS_FLASH_SIZE 0x1000000 /* Max size that the board might have */
348 # define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_8BIT
349 # define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */
350 # define CONFIG_SYS_MAX_FLASH_SECT 137 /* max number of sectors on one chip */
351 # define CONFIG_SYS_FLASH_PROTECTION /* "Real" (hardware) sectors protection */
352 # define CONFIG_SYS_FLASH_CHECKSUM
353 # define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_CS0_BASE, CONFIG_SYS_CS1_BASE }
354 # define CONFIG_FLASH_CFI_LEGACY
356 #ifdef CONFIG_FLASH_CFI_LEGACY
357 # define CONFIG_SYS_ATMEL_REGION 4
358 # define CONFIG_SYS_ATMEL_TOTALSECT 11
359 # define CONFIG_SYS_ATMEL_SECT {1, 2, 1, 7}
360 # define CONFIG_SYS_ATMEL_SECTSZ {0x4000, 0x2000, 0x8000, 0x10000}
365 * This is setting for JFFS2 support in u-boot.
366 * NOTE: Enable CONFIG_CMD_JFFS2 for JFFS2 support.
368 #ifdef CONFIG_CMD_JFFS2
369 #ifdef CF_STMICRO_BOOT
370 # define CONFIG_JFFS2_DEV "nor1"
371 # define CONFIG_JFFS2_PART_SIZE 0x01000000
372 # define CONFIG_JFFS2_PART_OFFSET (CONFIG_SYS_FLASH2_BASE + 0x500000)
374 #ifdef CONFIG_SYS_ATMEL_BOOT
375 # define CONFIG_JFFS2_DEV "nor1"
376 # define CONFIG_JFFS2_PART_SIZE 0x01000000
377 # define CONFIG_JFFS2_PART_OFFSET (CONFIG_SYS_FLASH1_BASE + 0x500000)
379 #ifdef CONFIG_SYS_INTEL_BOOT
380 # define CONFIG_JFFS2_DEV "nor0"
381 # define CONFIG_JFFS2_PART_SIZE (0x01000000 - 0x500000)
382 # define CONFIG_JFFS2_PART_OFFSET (CONFIG_SYS_FLASH0_BASE + 0x500000)
386 /*-----------------------------------------------------------------------
387 * Cache Configuration
389 #define CONFIG_SYS_CACHELINE_SIZE 16
391 #define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
392 CONFIG_SYS_INIT_RAM_SIZE - 8)
393 #define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
394 CONFIG_SYS_INIT_RAM_SIZE - 4)
395 #define CONFIG_SYS_ICACHE_INV (CF_CACR_BCINVA + CF_CACR_ICINVA)
396 #define CONFIG_SYS_DCACHE_INV (CF_CACR_DCINVA)
397 #define CONFIG_SYS_CACHE_ACR2 (CONFIG_SYS_SDRAM_BASE | \
398 CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
399 CF_ACR_EN | CF_ACR_SM_ALL)
400 #define CONFIG_SYS_CACHE_ICACR (CF_CACR_BEC | CF_CACR_IEC | \
401 CF_CACR_ICINVA | CF_CACR_EUSP)
402 #define CONFIG_SYS_CACHE_DCACR ((CONFIG_SYS_CACHE_ICACR | \
403 CF_CACR_DEC | CF_CACR_DDCM_P | \
404 CF_CACR_DCINVA) & ~CF_CACR_ICINVA)
406 /*-----------------------------------------------------------------------
407 * Memory bank definitions
410 * CS0 - NOR Flash 1, 2, 4, or 8MB
411 * CS1 - CompactFlash and registers
418 #if defined(CONFIG_SYS_ATMEL_BOOT) || defined(CONFIG_SYS_STMICRO_BOOT)
420 #define CONFIG_SYS_CS0_BASE 0x04000000
421 #define CONFIG_SYS_CS0_MASK 0x00070001
422 #define CONFIG_SYS_CS0_CTRL 0x00001140
424 #define CONFIG_SYS_CS1_BASE 0x00000000
425 #define CONFIG_SYS_CS1_MASK 0x01FF0001
426 #define CONFIG_SYS_CS1_CTRL 0x00000D60
428 #define CONFIG_SYS_ATMEL_BASE CONFIG_SYS_CS0_BASE
431 #define CONFIG_SYS_CS0_BASE 0x00000000
432 #define CONFIG_SYS_CS0_MASK 0x01FF0001
433 #define CONFIG_SYS_CS0_CTRL 0x00000D60
435 #define CONFIG_SYS_CS1_BASE 0x04000000
436 #define CONFIG_SYS_CS1_MASK 0x00070001
437 #define CONFIG_SYS_CS1_CTRL 0x00001140
439 #define CONFIG_SYS_ATMEL_BASE CONFIG_SYS_CS1_BASE
443 #define CONFIG_SYS_CS2_BASE 0x08000000
444 #define CONFIG_SYS_CS2_MASK 0x00070001
445 #define CONFIG_SYS_CS2_CTRL 0x003f1140
448 #define CONFIG_SYS_CS3_BASE 0x09000000
449 #define CONFIG_SYS_CS3_MASK 0x00070001
450 #define CONFIG_SYS_CS3_CTRL 0x00000020
452 #endif /* _M54455EVB_H */