2 * Configuation settings for the Freescale MCF54455 EVB board.
4 * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
5 * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
7 * SPDX-License-Identifier: GPL-2.0+
11 * board/config.h - configuration options, board specific
18 * High Level Configuration Options
21 #define CONFIG_M54455EVB /* M54455EVB board */
23 #define CONFIG_MCFUART
24 #define CONFIG_SYS_UART_PORT (0)
26 #define LDS_BOARD_TEXT board/freescale/m54455evb/sbf_dram_init.o (.text*)
28 #undef CONFIG_WATCHDOG
30 #define CONFIG_TIMESTAMP /* Print image info with timestamp */
35 #define CONFIG_BOOTP_BOOTFILESIZE
36 #define CONFIG_BOOTP_BOOTPATH
37 #define CONFIG_BOOTP_GATEWAY
38 #define CONFIG_BOOTP_HOSTNAME
40 /* Network configuration */
44 # define CONFIG_MII_INIT 1
45 # define CONFIG_SYS_DISCOVER_PHY
46 # define CONFIG_SYS_RX_ETH_BUFFER 8
47 # define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
49 # define CONFIG_SYS_FEC0_PINMUX 0
50 # define CONFIG_SYS_FEC1_PINMUX 0
51 # define CONFIG_SYS_FEC0_MIIBASE CONFIG_SYS_FEC0_IOBASE
52 # define CONFIG_SYS_FEC1_MIIBASE CONFIG_SYS_FEC0_IOBASE
53 # define MCFFEC_TOUT_LOOP 50000
54 # define CONFIG_HAS_ETH1
56 # define CONFIG_ETHPRIME "FEC0"
57 # define CONFIG_IPADDR 192.162.1.2
58 # define CONFIG_NETMASK 255.255.255.0
59 # define CONFIG_SERVERIP 192.162.1.1
60 # define CONFIG_GATEWAYIP 192.162.1.1
62 /* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */
63 # ifndef CONFIG_SYS_DISCOVER_PHY
64 # define FECDUPLEX FULL
65 # define FECSPEED _100BASET
67 # ifndef CONFIG_SYS_FAULT_ECHO_LINK_DOWN
68 # define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
70 # endif /* CONFIG_SYS_DISCOVER_PHY */
73 #define CONFIG_HOSTNAME M54455EVB
74 #ifdef CONFIG_SYS_STMICRO_BOOT
75 /* ST Micro serial flash */
76 #define CONFIG_SYS_LOAD_ADDR2 0x40010013
77 #define CONFIG_EXTRA_ENV_SETTINGS \
79 "inpclk=" __stringify(CONFIG_SYS_INPUT_CLKSRC) "\0" \
80 "loadaddr=0x40010000\0" \
81 "sbfhdr=sbfhdr.bin\0" \
82 "uboot=u-boot.bin\0" \
83 "load=tftp ${loadaddr} ${sbfhdr};" \
84 "tftp " __stringify(CONFIG_SYS_LOAD_ADDR2) " ${uboot} \0" \
85 "upd=run load; run prog\0" \
86 "prog=sf probe 0:1 1000000 3;" \
88 "sf write ${loadaddr} 0 0x30000;" \
93 #ifdef CONFIG_SYS_ATMEL_BOOT
94 # define CONFIG_SYS_UBOOT_END 0x0403FFFF
95 #elif defined(CONFIG_SYS_INTEL_BOOT)
96 # define CONFIG_SYS_UBOOT_END 0x3FFFF
98 #define CONFIG_EXTRA_ENV_SETTINGS \
100 "inpclk=" __stringify(CONFIG_SYS_INPUT_CLKSRC) "\0" \
101 "loadaddr=0x40010000\0" \
102 "uboot=u-boot.bin\0" \
103 "load=tftp ${loadaddr} ${uboot}\0" \
104 "upd=run load; run prog\0" \
105 "prog=prot off " __stringify(CONFIG_SYS_FLASH_BASE) \
106 " " __stringify(CONFIG_SYS_UBOOT_END) ";" \
107 "era " __stringify(CONFIG_SYS_FLASH_BASE) " " \
108 __stringify(CONFIG_SYS_UBOOT_END) ";" \
109 "cp.b ${loadaddr} " __stringify(CONFIG_SYS_FLASH_BASE) \
110 " ${filesize}; save\0" \
114 /* ATA configuration */
115 #define CONFIG_IDE_RESET 1
116 #define CONFIG_IDE_PREINIT 1
120 #define CONFIG_SYS_IDE_MAXBUS 1
121 #define CONFIG_SYS_IDE_MAXDEVICE 2
123 #define CONFIG_SYS_ATA_BASE_ADDR 0x90000000
124 #define CONFIG_SYS_ATA_IDE0_OFFSET 0
126 #define CONFIG_SYS_ATA_DATA_OFFSET 0xA0 /* Offset for data I/O */
127 #define CONFIG_SYS_ATA_REG_OFFSET 0xA0 /* Offset for normal register accesses */
128 #define CONFIG_SYS_ATA_ALT_OFFSET 0xC0 /* Offset for alternate registers */
129 #define CONFIG_SYS_ATA_STRIDE 4 /* Interval between registers */
132 #define CONFIG_MCFRTC
134 #define CONFIG_SYS_RTC_OSCILLATOR (32 * CONFIG_SYS_HZ)
137 #define CONFIG_MCFTMR
141 #define CONFIG_SYS_I2C
142 #define CONFIG_SYS_I2C_FSL
143 #define CONFIG_SYS_FSL_I2C_SPEED 80000
144 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
145 #define CONFIG_SYS_FSL_I2C_OFFSET 0x58000
146 #define CONFIG_SYS_IMMR CONFIG_SYS_MBAR
148 /* DSPI and Serial Flash */
149 #define CONFIG_CF_SPI
150 #define CONFIG_CF_DSPI
151 #define CONFIG_HARD_SPI
152 #define CONFIG_SYS_SBFHDR_SIZE 0x13
153 #ifdef CONFIG_CMD_SPI
155 # define CONFIG_SYS_DSPI_CTAR0 (DSPI_CTAR_TRSZ(7) | \
156 DSPI_CTAR_PCSSCK_1CLK | \
157 DSPI_CTAR_PASC(0) | \
159 DSPI_CTAR_CSSCK(0) | \
165 #ifdef CONFIG_CMD_PCI
166 #define CONFIG_PCIAUTO_SKIP_HOST_BRIDGE 1
168 #define CONFIG_SYS_PCI_CACHE_LINE_SIZE 4
170 #define CONFIG_SYS_PCI_MEM_BUS 0xA0000000
171 #define CONFIG_SYS_PCI_MEM_PHYS CONFIG_SYS_PCI_MEM_BUS
172 #define CONFIG_SYS_PCI_MEM_SIZE 0x10000000
174 #define CONFIG_SYS_PCI_IO_BUS 0xB1000000
175 #define CONFIG_SYS_PCI_IO_PHYS CONFIG_SYS_PCI_IO_BUS
176 #define CONFIG_SYS_PCI_IO_SIZE 0x01000000
178 #define CONFIG_SYS_PCI_CFG_BUS 0xB0000000
179 #define CONFIG_SYS_PCI_CFG_PHYS CONFIG_SYS_PCI_CFG_BUS
180 #define CONFIG_SYS_PCI_CFG_SIZE 0x01000000
183 /* FPGA - Spartan 2 */
186 #define CONFIG_FPGA_COUNT 1
187 #define CONFIG_SYS_FPGA_PROG_FEEDBACK
188 #define CONFIG_SYS_FPGA_CHECK_CTRLC
191 /* Input, PCI, Flexbus, and VCO */
192 #define CONFIG_EXTRA_CLOCK
194 #define CONFIG_PRAM 2048 /* 2048 KB */
196 #define CONFIG_SYS_LONGHELP /* undef to save memory */
198 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */
199 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
201 #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x10000)
203 #define CONFIG_SYS_MBAR 0xFC000000
206 * Low Level Configuration Settings
207 * (address mappings, register initial values, etc.)
208 * You should know what you are doing if you make changes here.
211 /*-----------------------------------------------------------------------
212 * Definitions for initial stack pointer and data area (in DPRAM)
214 #define CONFIG_SYS_INIT_RAM_ADDR 0x80000000
215 #define CONFIG_SYS_INIT_RAM_SIZE 0x8000 /* Size of used area in internal SRAM */
216 #define CONFIG_SYS_INIT_RAM_CTRL 0x221
217 #define CONFIG_SYS_GBL_DATA_OFFSET ((CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) - 32)
218 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
219 #define CONFIG_SYS_SBFHDR_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - 32)
221 /*-----------------------------------------------------------------------
222 * Start addresses for the final memory configuration
223 * (Set up by the startup code)
224 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
226 #define CONFIG_SYS_SDRAM_BASE 0x40000000
227 #define CONFIG_SYS_SDRAM_BASE1 0x48000000
228 #define CONFIG_SYS_SDRAM_SIZE 256 /* SDRAM size in MB */
229 #define CONFIG_SYS_SDRAM_CFG1 0x65311610
230 #define CONFIG_SYS_SDRAM_CFG2 0x59670000
231 #define CONFIG_SYS_SDRAM_CTRL 0xEA0B2000
232 #define CONFIG_SYS_SDRAM_EMOD 0x40010000
233 #define CONFIG_SYS_SDRAM_MODE 0x00010033
234 #define CONFIG_SYS_SDRAM_DRV_STRENGTH 0xAA
236 #define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE + 0x400
237 #define CONFIG_SYS_MEMTEST_END ((CONFIG_SYS_SDRAM_SIZE - 3) << 20)
240 # define CONFIG_SERIAL_BOOT
241 # define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_TEXT_BASE + 0x400)
243 # define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400)
245 #define CONFIG_SYS_BOOTPARAMS_LEN 64*1024
246 #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
248 /* Reserve 256 kB for malloc() */
249 #define CONFIG_SYS_MALLOC_LEN (256 << 10)
252 * For booting Linux, the board info and command line data
253 * have to be in the first 8 MB of memory, since this is
254 * the maximum mapped by the Linux kernel during initialization ??
256 /* Initial Memory map for Linux */
257 #define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20))
260 * Configuration for environment
261 * Environment is not embedded in u-boot. First time runing may have env
262 * crc error warning if there is no correct environment on the flash.
265 # define CONFIG_ENV_SPI_CS 1
267 #undef CONFIG_ENV_OVERWRITE
269 /*-----------------------------------------------------------------------
272 #ifdef CONFIG_SYS_STMICRO_BOOT
273 # define CONFIG_SYS_FLASH_BASE CONFIG_SYS_CS0_BASE
274 # define CONFIG_SYS_FLASH0_BASE CONFIG_SYS_CS1_BASE
275 # define CONFIG_ENV_OFFSET 0x30000
276 # define CONFIG_ENV_SIZE 0x2000
277 # define CONFIG_ENV_SECT_SIZE 0x10000
279 #ifdef CONFIG_SYS_ATMEL_BOOT
280 # define CONFIG_SYS_FLASH_BASE CONFIG_SYS_CS0_BASE
281 # define CONFIG_SYS_FLASH0_BASE CONFIG_SYS_CS0_BASE
282 # define CONFIG_SYS_FLASH1_BASE CONFIG_SYS_CS1_BASE
283 # define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x40000)
284 # define CONFIG_ENV_SIZE 0x2000
285 # define CONFIG_ENV_SECT_SIZE 0x10000
287 #ifdef CONFIG_SYS_INTEL_BOOT
288 # define CONFIG_SYS_FLASH_BASE CONFIG_SYS_CS0_BASE
289 # define CONFIG_SYS_FLASH0_BASE CONFIG_SYS_CS0_BASE
290 # define CONFIG_SYS_FLASH1_BASE CONFIG_SYS_CS1_BASE
291 # define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x40000)
292 # define CONFIG_ENV_SIZE 0x2000
293 # define CONFIG_ENV_SECT_SIZE 0x20000
296 #define CONFIG_SYS_FLASH_CFI
297 #ifdef CONFIG_SYS_FLASH_CFI
299 # define CONFIG_FLASH_CFI_DRIVER 1
300 # define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1
301 # define CONFIG_SYS_FLASH_SIZE 0x1000000 /* Max size that the board might have */
302 # define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_8BIT
303 # define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */
304 # define CONFIG_SYS_MAX_FLASH_SECT 137 /* max number of sectors on one chip */
305 # define CONFIG_SYS_FLASH_PROTECTION /* "Real" (hardware) sectors protection */
306 # define CONFIG_SYS_FLASH_CHECKSUM
307 # define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_CS0_BASE, CONFIG_SYS_CS1_BASE }
308 # define CONFIG_FLASH_CFI_LEGACY
310 #ifdef CONFIG_FLASH_CFI_LEGACY
311 # define CONFIG_SYS_ATMEL_REGION 4
312 # define CONFIG_SYS_ATMEL_TOTALSECT 11
313 # define CONFIG_SYS_ATMEL_SECT {1, 2, 1, 7}
314 # define CONFIG_SYS_ATMEL_SECTSZ {0x4000, 0x2000, 0x8000, 0x10000}
319 * This is setting for JFFS2 support in u-boot.
320 * NOTE: Enable CONFIG_CMD_JFFS2 for JFFS2 support.
322 #ifdef CONFIG_CMD_JFFS2
323 #ifdef CF_STMICRO_BOOT
324 # define CONFIG_JFFS2_DEV "nor1"
325 # define CONFIG_JFFS2_PART_SIZE 0x01000000
326 # define CONFIG_JFFS2_PART_OFFSET (CONFIG_SYS_FLASH2_BASE + 0x500000)
328 #ifdef CONFIG_SYS_ATMEL_BOOT
329 # define CONFIG_JFFS2_DEV "nor1"
330 # define CONFIG_JFFS2_PART_SIZE 0x01000000
331 # define CONFIG_JFFS2_PART_OFFSET (CONFIG_SYS_FLASH1_BASE + 0x500000)
333 #ifdef CONFIG_SYS_INTEL_BOOT
334 # define CONFIG_JFFS2_DEV "nor0"
335 # define CONFIG_JFFS2_PART_SIZE (0x01000000 - 0x500000)
336 # define CONFIG_JFFS2_PART_OFFSET (CONFIG_SYS_FLASH0_BASE + 0x500000)
340 /*-----------------------------------------------------------------------
341 * Cache Configuration
343 #define CONFIG_SYS_CACHELINE_SIZE 16
345 #define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
346 CONFIG_SYS_INIT_RAM_SIZE - 8)
347 #define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
348 CONFIG_SYS_INIT_RAM_SIZE - 4)
349 #define CONFIG_SYS_ICACHE_INV (CF_CACR_BCINVA + CF_CACR_ICINVA)
350 #define CONFIG_SYS_DCACHE_INV (CF_CACR_DCINVA)
351 #define CONFIG_SYS_CACHE_ACR2 (CONFIG_SYS_SDRAM_BASE | \
352 CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
353 CF_ACR_EN | CF_ACR_SM_ALL)
354 #define CONFIG_SYS_CACHE_ICACR (CF_CACR_BEC | CF_CACR_IEC | \
355 CF_CACR_ICINVA | CF_CACR_EUSP)
356 #define CONFIG_SYS_CACHE_DCACR ((CONFIG_SYS_CACHE_ICACR | \
357 CF_CACR_DEC | CF_CACR_DDCM_P | \
358 CF_CACR_DCINVA) & ~CF_CACR_ICINVA)
360 /*-----------------------------------------------------------------------
361 * Memory bank definitions
364 * CS0 - NOR Flash 1, 2, 4, or 8MB
365 * CS1 - CompactFlash and registers
372 #if defined(CONFIG_SYS_ATMEL_BOOT) || defined(CONFIG_SYS_STMICRO_BOOT)
374 #define CONFIG_SYS_CS0_BASE 0x04000000
375 #define CONFIG_SYS_CS0_MASK 0x00070001
376 #define CONFIG_SYS_CS0_CTRL 0x00001140
378 #define CONFIG_SYS_CS1_BASE 0x00000000
379 #define CONFIG_SYS_CS1_MASK 0x01FF0001
380 #define CONFIG_SYS_CS1_CTRL 0x00000D60
382 #define CONFIG_SYS_ATMEL_BASE CONFIG_SYS_CS0_BASE
385 #define CONFIG_SYS_CS0_BASE 0x00000000
386 #define CONFIG_SYS_CS0_MASK 0x01FF0001
387 #define CONFIG_SYS_CS0_CTRL 0x00000D60
389 #define CONFIG_SYS_CS1_BASE 0x04000000
390 #define CONFIG_SYS_CS1_MASK 0x00070001
391 #define CONFIG_SYS_CS1_CTRL 0x00001140
393 #define CONFIG_SYS_ATMEL_BASE CONFIG_SYS_CS1_BASE
397 #define CONFIG_SYS_CS2_BASE 0x08000000
398 #define CONFIG_SYS_CS2_MASK 0x00070001
399 #define CONFIG_SYS_CS2_CTRL 0x003f1140
402 #define CONFIG_SYS_CS3_BASE 0x09000000
403 #define CONFIG_SYS_CS3_MASK 0x00070001
404 #define CONFIG_SYS_CS3_CTRL 0x00000020
406 #endif /* _M54455EVB_H */