2 * Configuation settings for the Freescale MCF5475 board.
4 * Copyright (C) 2004-2008 Freescale Semiconductor, Inc.
5 * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
7 * SPDX-License-Identifier: GPL-2.0+
11 * board/config.h - configuration options, board specific
18 * High Level Configuration Options
22 #define CONFIG_MCFUART
23 #define CONFIG_SYS_UART_PORT (0)
25 #undef CONFIG_HW_WATCHDOG
26 #define CONFIG_WATCHDOG_TIMEOUT 5000 /* timeout in milliseconds, max timeout is 6.71sec */
28 /* Command line configuration */
29 #define CONFIG_CMD_PCI
33 #define CONFIG_FSLDMAFEC
34 #ifdef CONFIG_FSLDMAFEC
36 # define CONFIG_MII_INIT 1
37 # define CONFIG_HAS_ETH1
39 # define CONFIG_SYS_DMA_USE_INTSRAM 1
40 # define CONFIG_SYS_DISCOVER_PHY
41 # define CONFIG_SYS_RX_ETH_BUFFER 32
42 # define CONFIG_SYS_TX_ETH_BUFFER 48
43 # define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
45 # define CONFIG_SYS_FEC0_PINMUX 0
46 # define CONFIG_SYS_FEC0_MIIBASE CONFIG_SYS_FEC0_IOBASE
47 # define CONFIG_SYS_FEC1_PINMUX 0
48 # define CONFIG_SYS_FEC1_MIIBASE CONFIG_SYS_FEC0_IOBASE
50 # define MCFFEC_TOUT_LOOP 50000
51 /* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */
52 # ifndef CONFIG_SYS_DISCOVER_PHY
53 # define FECDUPLEX FULL
54 # define FECSPEED _100BASET
56 # ifndef CONFIG_SYS_FAULT_ECHO_LINK_DOWN
57 # define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
59 # endif /* CONFIG_SYS_DISCOVER_PHY */
61 # define CONFIG_IPADDR 192.162.1.2
62 # define CONFIG_NETMASK 255.255.255.0
63 # define CONFIG_SERVERIP 192.162.1.1
64 # define CONFIG_GATEWAYIP 192.162.1.1
69 # define CONFIG_USB_OHCI_NEW
71 # ifndef CONFIG_CMD_PCI
72 # define CONFIG_CMD_PCI
74 # define CONFIG_PCI_OHCI
76 # undef CONFIG_SYS_USB_OHCI_BOARD_INIT
77 # undef CONFIG_SYS_USB_OHCI_CPU_INIT
78 # define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 15
79 # define CONFIG_SYS_USB_OHCI_SLOT_NAME "isp1561"
80 # define CONFIG_SYS_OHCI_SWAP_REG_ACCESS
84 #define CONFIG_SYS_I2C
85 #define CONFIG_SYS_I2C_FSL
86 #define CONFIG_SYS_FSL_I2C_SPEED 80000
87 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
88 #define CONFIG_SYS_FSL_I2C_OFFSET 0x00008F00
89 #define CONFIG_SYS_IMMR CONFIG_SYS_MBAR
93 #define CONFIG_PCIAUTO_SKIP_HOST_BRIDGE 1
95 #define CONFIG_SYS_PCI_CACHE_LINE_SIZE 8
97 #define CONFIG_SYS_PCI_MEM_BUS 0x80000000
98 #define CONFIG_SYS_PCI_MEM_PHYS CONFIG_SYS_PCI_MEM_BUS
99 #define CONFIG_SYS_PCI_MEM_SIZE 0x10000000
101 #define CONFIG_SYS_PCI_IO_BUS 0x71000000
102 #define CONFIG_SYS_PCI_IO_PHYS CONFIG_SYS_PCI_IO_BUS
103 #define CONFIG_SYS_PCI_IO_SIZE 0x01000000
105 #define CONFIG_SYS_PCI_CFG_BUS 0x70000000
106 #define CONFIG_SYS_PCI_CFG_PHYS CONFIG_SYS_PCI_CFG_BUS
107 #define CONFIG_SYS_PCI_CFG_SIZE 0x01000000
110 #define CONFIG_UDP_CHECKSUM
113 # define CONFIG_IPADDR 192.162.1.2
114 # define CONFIG_NETMASK 255.255.255.0
115 # define CONFIG_SERVERIP 192.162.1.1
116 # define CONFIG_GATEWAYIP 192.162.1.1
117 #endif /* FEC_ENET */
119 #define CONFIG_HOSTNAME M547xEVB
120 #define CONFIG_EXTRA_ENV_SETTINGS \
123 "u-boot=u-boot.bin\0" \
124 "load=tftp ${loadaddr) ${u-boot}\0" \
125 "upd=run load; run prog\0" \
126 "prog=prot off bank 1;" \
127 "era ff800000 ff83ffff;" \
128 "cp.b ${loadaddr} ff800000 ${filesize};"\
132 #define CONFIG_PRAM 512 /* 512 KB */
133 #define CONFIG_SYS_LONGHELP /* undef to save memory */
135 #ifdef CONFIG_CMD_KGDB
136 # define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
138 # define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
141 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
142 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */
143 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
144 #define CONFIG_SYS_LOAD_ADDR 0x00010000
146 #define CONFIG_SYS_CLK CONFIG_SYS_BUSCLK
147 #define CONFIG_SYS_CPU_CLK CONFIG_SYS_CLK * 2
149 #define CONFIG_SYS_MBAR 0xF0000000
150 #define CONFIG_SYS_INTSRAM (CONFIG_SYS_MBAR + 0x10000)
151 #define CONFIG_SYS_INTSRAMSZ 0x8000
153 /*#define CONFIG_SYS_LATCH_ADDR (CONFIG_SYS_CS1_BASE + 0x80000)*/
156 * Low Level Configuration Settings
157 * (address mappings, register initial values, etc.)
158 * You should know what you are doing if you make changes here.
160 /*-----------------------------------------------------------------------
161 * Definitions for initial stack pointer and data area (in DPRAM)
163 #define CONFIG_SYS_INIT_RAM_ADDR 0xF2000000
164 #define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in internal SRAM */
165 #define CONFIG_SYS_INIT_RAM_CTRL 0x21
166 #define CONFIG_SYS_INIT_RAM1_ADDR (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_SIZE)
167 #define CONFIG_SYS_INIT_RAM1_END 0x1000 /* End of used area in internal SRAM */
168 #define CONFIG_SYS_INIT_RAM1_CTRL 0x21
169 #define CONFIG_SYS_GBL_DATA_OFFSET ((CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) - 0x10)
170 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
172 /*-----------------------------------------------------------------------
173 * Start addresses for the final memory configuration
174 * (Set up by the startup code)
175 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
177 #define CONFIG_SYS_SDRAM_BASE 0x00000000
178 #define CONFIG_SYS_SDRAM_CFG1 0x73711630
179 #define CONFIG_SYS_SDRAM_CFG2 0x46770000
180 #define CONFIG_SYS_SDRAM_CTRL 0xE10B0000
181 #define CONFIG_SYS_SDRAM_EMOD 0x40010000
182 #define CONFIG_SYS_SDRAM_MODE 0x018D0000
183 #define CONFIG_SYS_SDRAM_DRVSTRENGTH 0x000002AA
184 #ifdef CONFIG_SYS_DRAMSZ1
185 # define CONFIG_SYS_SDRAM_SIZE (CONFIG_SYS_DRAMSZ + CONFIG_SYS_DRAMSZ1)
187 # define CONFIG_SYS_SDRAM_SIZE CONFIG_SYS_DRAMSZ
190 #define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE + 0x400
191 #define CONFIG_SYS_MEMTEST_END ((CONFIG_SYS_SDRAM_SIZE - 3) << 20)
193 #define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400)
194 #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
196 #define CONFIG_SYS_BOOTPARAMS_LEN 64*1024
198 /* Reserve 256 kB for malloc() */
199 #define CONFIG_SYS_MALLOC_LEN (256 << 10)
201 * For booting Linux, the board info and command line data
202 * have to be in the first 8 MB of memory, since this is
203 * the maximum mapped by the Linux kernel during initialization ??
205 #define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20))
207 /*-----------------------------------------------------------------------
210 #define CONFIG_SYS_FLASH_CFI
211 #ifdef CONFIG_SYS_FLASH_CFI
212 # define CONFIG_SYS_FLASH_BASE (CONFIG_SYS_CS0_BASE)
213 # define CONFIG_FLASH_CFI_DRIVER 1
214 # define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
215 # define CONFIG_SYS_MAX_FLASH_SECT 137 /* max number of sectors on one chip */
216 # define CONFIG_SYS_FLASH_PROTECTION /* "Real" (hardware) sectors protection */
217 # define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
218 #ifdef CONFIG_SYS_NOR1SZ
219 # define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */
220 # define CONFIG_SYS_FLASH_SIZE ((CONFIG_SYS_NOR1SZ + CONFIG_SYS_BOOTSZ) << 20)
221 # define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_CS0_BASE, CONFIG_SYS_CS1_BASE }
223 # define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
224 # define CONFIG_SYS_FLASH_SIZE (CONFIG_SYS_BOOTSZ << 20)
228 /* Configuration for environment
229 * Environment is not embedded in u-boot but at offset 0x40000 on the flash.
230 * First time runing may have env crc error warning if there is
231 * no correct environment on the flash.
233 #define CONFIG_ENV_OFFSET 0x40000
234 #define CONFIG_ENV_SECT_SIZE 0x10000
236 /*-----------------------------------------------------------------------
237 * Cache Configuration
239 #define CONFIG_SYS_CACHELINE_SIZE 16
241 #define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
242 CONFIG_SYS_INIT_RAM_SIZE - 8)
243 #define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
244 CONFIG_SYS_INIT_RAM_SIZE - 4)
245 #define CONFIG_SYS_ICACHE_INV (CF_CACR_BCINVA + CF_CACR_ICINVA + \
247 #define CONFIG_SYS_DCACHE_INV (CF_CACR_DCINVA)
248 #define CONFIG_SYS_CACHE_ACR2 (CONFIG_SYS_SDRAM_BASE | \
249 CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
250 CF_ACR_EN | CF_ACR_SM_ALL)
251 #define CONFIG_SYS_CACHE_ICACR (CF_CACR_BEC | CF_CACR_BCINVA | \
252 CF_CACR_IEC | CF_CACR_ICINVA)
253 #define CONFIG_SYS_CACHE_DCACR ((CONFIG_SYS_CACHE_ICACR | \
254 CF_CACR_DEC | CF_CACR_DDCM_P | \
255 CF_CACR_DCINVA) & ~CF_CACR_ICINVA)
257 /*-----------------------------------------------------------------------
258 * Chipselect bank definitions
261 * CS0 - NOR Flash 1, 2, 4, or 8MB
268 #define CONFIG_SYS_CS0_BASE 0xFF800000
269 #define CONFIG_SYS_CS0_MASK (((CONFIG_SYS_BOOTSZ << 20) - 1) & 0xFFFF0001)
270 #define CONFIG_SYS_CS0_CTRL 0x00101980
272 #ifdef CONFIG_SYS_NOR1SZ
273 #define CONFIG_SYS_CS1_BASE 0xE0000000
274 #define CONFIG_SYS_CS1_MASK (((CONFIG_SYS_NOR1SZ << 20) - 1) & 0xFFFF0001)
275 #define CONFIG_SYS_CS1_CTRL 0x00101D80
278 #endif /* _M5475EVB_H */