2 * Configuation settings for the Freescale MCF5475 board.
4 * Copyright (C) 2004-2008 Freescale Semiconductor, Inc.
5 * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
7 * SPDX-License-Identifier: GPL-2.0+
11 * board/config.h - configuration options, board specific
18 * High Level Configuration Options
22 #define CONFIG_MCFUART
23 #define CONFIG_SYS_UART_PORT (0)
24 #define CONFIG_BAUDRATE 115200
26 #undef CONFIG_HW_WATCHDOG
27 #define CONFIG_WATCHDOG_TIMEOUT 5000 /* timeout in milliseconds, max timeout is 6.71sec */
29 /* Command line configuration */
30 #undef CONFIG_CMD_DATE
31 #define CONFIG_CMD_PCI
32 #define CONFIG_CMD_REGINFO
36 #define CONFIG_FSLDMAFEC
37 #ifdef CONFIG_FSLDMAFEC
39 # define CONFIG_MII_INIT 1
40 # define CONFIG_HAS_ETH1
42 # define CONFIG_SYS_DMA_USE_INTSRAM 1
43 # define CONFIG_SYS_DISCOVER_PHY
44 # define CONFIG_SYS_RX_ETH_BUFFER 32
45 # define CONFIG_SYS_TX_ETH_BUFFER 48
46 # define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
48 # define CONFIG_SYS_FEC0_PINMUX 0
49 # define CONFIG_SYS_FEC0_MIIBASE CONFIG_SYS_FEC0_IOBASE
50 # define CONFIG_SYS_FEC1_PINMUX 0
51 # define CONFIG_SYS_FEC1_MIIBASE CONFIG_SYS_FEC0_IOBASE
53 # define MCFFEC_TOUT_LOOP 50000
54 /* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */
55 # ifndef CONFIG_SYS_DISCOVER_PHY
56 # define FECDUPLEX FULL
57 # define FECSPEED _100BASET
59 # ifndef CONFIG_SYS_FAULT_ECHO_LINK_DOWN
60 # define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
62 # endif /* CONFIG_SYS_DISCOVER_PHY */
64 # define CONFIG_IPADDR 192.162.1.2
65 # define CONFIG_NETMASK 255.255.255.0
66 # define CONFIG_SERVERIP 192.162.1.1
67 # define CONFIG_GATEWAYIP 192.162.1.1
72 # define CONFIG_USB_OHCI_NEW
74 # ifndef CONFIG_CMD_PCI
75 # define CONFIG_CMD_PCI
77 # define CONFIG_PCI_OHCI
78 # define CONFIG_DOS_PARTITION
80 # undef CONFIG_SYS_USB_OHCI_BOARD_INIT
81 # undef CONFIG_SYS_USB_OHCI_CPU_INIT
82 # define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 15
83 # define CONFIG_SYS_USB_OHCI_SLOT_NAME "isp1561"
84 # define CONFIG_SYS_OHCI_SWAP_REG_ACCESS
88 #define CONFIG_SYS_I2C
89 #define CONFIG_SYS_I2C_FSL
90 #define CONFIG_SYS_FSL_I2C_SPEED 80000
91 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
92 #define CONFIG_SYS_FSL_I2C_OFFSET 0x00008F00
93 #define CONFIG_SYS_IMMR CONFIG_SYS_MBAR
98 #define CONFIG_PCI_PNP 1
99 #define CONFIG_PCIAUTO_SKIP_HOST_BRIDGE 1
101 #define CONFIG_SYS_PCI_CACHE_LINE_SIZE 8
103 #define CONFIG_SYS_PCI_MEM_BUS 0x80000000
104 #define CONFIG_SYS_PCI_MEM_PHYS CONFIG_SYS_PCI_MEM_BUS
105 #define CONFIG_SYS_PCI_MEM_SIZE 0x10000000
107 #define CONFIG_SYS_PCI_IO_BUS 0x71000000
108 #define CONFIG_SYS_PCI_IO_PHYS CONFIG_SYS_PCI_IO_BUS
109 #define CONFIG_SYS_PCI_IO_SIZE 0x01000000
111 #define CONFIG_SYS_PCI_CFG_BUS 0x70000000
112 #define CONFIG_SYS_PCI_CFG_PHYS CONFIG_SYS_PCI_CFG_BUS
113 #define CONFIG_SYS_PCI_CFG_SIZE 0x01000000
116 #define CONFIG_UDP_CHECKSUM
119 # define CONFIG_IPADDR 192.162.1.2
120 # define CONFIG_NETMASK 255.255.255.0
121 # define CONFIG_SERVERIP 192.162.1.1
122 # define CONFIG_GATEWAYIP 192.162.1.1
123 #endif /* FEC_ENET */
125 #define CONFIG_HOSTNAME M547xEVB
126 #define CONFIG_EXTRA_ENV_SETTINGS \
129 "u-boot=u-boot.bin\0" \
130 "load=tftp ${loadaddr) ${u-boot}\0" \
131 "upd=run load; run prog\0" \
132 "prog=prot off bank 1;" \
133 "era ff800000 ff83ffff;" \
134 "cp.b ${loadaddr} ff800000 ${filesize};"\
138 #define CONFIG_PRAM 512 /* 512 KB */
139 #define CONFIG_SYS_LONGHELP /* undef to save memory */
141 #ifdef CONFIG_CMD_KGDB
142 # define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
144 # define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
147 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
148 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */
149 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
150 #define CONFIG_SYS_LOAD_ADDR 0x00010000
152 #define CONFIG_SYS_CLK CONFIG_SYS_BUSCLK
153 #define CONFIG_SYS_CPU_CLK CONFIG_SYS_CLK * 2
155 #define CONFIG_SYS_MBAR 0xF0000000
156 #define CONFIG_SYS_INTSRAM (CONFIG_SYS_MBAR + 0x10000)
157 #define CONFIG_SYS_INTSRAMSZ 0x8000
159 /*#define CONFIG_SYS_LATCH_ADDR (CONFIG_SYS_CS1_BASE + 0x80000)*/
162 * Low Level Configuration Settings
163 * (address mappings, register initial values, etc.)
164 * You should know what you are doing if you make changes here.
166 /*-----------------------------------------------------------------------
167 * Definitions for initial stack pointer and data area (in DPRAM)
169 #define CONFIG_SYS_INIT_RAM_ADDR 0xF2000000
170 #define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in internal SRAM */
171 #define CONFIG_SYS_INIT_RAM_CTRL 0x21
172 #define CONFIG_SYS_INIT_RAM1_ADDR (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_SIZE)
173 #define CONFIG_SYS_INIT_RAM1_END 0x1000 /* End of used area in internal SRAM */
174 #define CONFIG_SYS_INIT_RAM1_CTRL 0x21
175 #define CONFIG_SYS_GBL_DATA_OFFSET ((CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) - 0x10)
176 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
178 /*-----------------------------------------------------------------------
179 * Start addresses for the final memory configuration
180 * (Set up by the startup code)
181 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
183 #define CONFIG_SYS_SDRAM_BASE 0x00000000
184 #define CONFIG_SYS_SDRAM_CFG1 0x73711630
185 #define CONFIG_SYS_SDRAM_CFG2 0x46770000
186 #define CONFIG_SYS_SDRAM_CTRL 0xE10B0000
187 #define CONFIG_SYS_SDRAM_EMOD 0x40010000
188 #define CONFIG_SYS_SDRAM_MODE 0x018D0000
189 #define CONFIG_SYS_SDRAM_DRVSTRENGTH 0x000002AA
190 #ifdef CONFIG_SYS_DRAMSZ1
191 # define CONFIG_SYS_SDRAM_SIZE (CONFIG_SYS_DRAMSZ + CONFIG_SYS_DRAMSZ1)
193 # define CONFIG_SYS_SDRAM_SIZE CONFIG_SYS_DRAMSZ
196 #define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE + 0x400
197 #define CONFIG_SYS_MEMTEST_END ((CONFIG_SYS_SDRAM_SIZE - 3) << 20)
199 #define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400)
200 #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
202 #define CONFIG_SYS_BOOTPARAMS_LEN 64*1024
204 /* Reserve 256 kB for malloc() */
205 #define CONFIG_SYS_MALLOC_LEN (256 << 10)
207 * For booting Linux, the board info and command line data
208 * have to be in the first 8 MB of memory, since this is
209 * the maximum mapped by the Linux kernel during initialization ??
211 #define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20))
213 /*-----------------------------------------------------------------------
216 #define CONFIG_SYS_FLASH_CFI
217 #ifdef CONFIG_SYS_FLASH_CFI
218 # define CONFIG_SYS_FLASH_BASE (CONFIG_SYS_CS0_BASE)
219 # define CONFIG_FLASH_CFI_DRIVER 1
220 # define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
221 # define CONFIG_SYS_MAX_FLASH_SECT 137 /* max number of sectors on one chip */
222 # define CONFIG_SYS_FLASH_PROTECTION /* "Real" (hardware) sectors protection */
223 # define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
224 #ifdef CONFIG_SYS_NOR1SZ
225 # define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */
226 # define CONFIG_SYS_FLASH_SIZE ((CONFIG_SYS_NOR1SZ + CONFIG_SYS_BOOTSZ) << 20)
227 # define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_CS0_BASE, CONFIG_SYS_CS1_BASE }
229 # define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
230 # define CONFIG_SYS_FLASH_SIZE (CONFIG_SYS_BOOTSZ << 20)
234 /* Configuration for environment
235 * Environment is not embedded in u-boot but at offset 0x40000 on the flash.
236 * First time runing may have env crc error warning if there is
237 * no correct environment on the flash.
239 #define CONFIG_ENV_OFFSET 0x40000
240 #define CONFIG_ENV_SECT_SIZE 0x10000
241 #define CONFIG_ENV_IS_IN_FLASH 1
243 /*-----------------------------------------------------------------------
244 * Cache Configuration
246 #define CONFIG_SYS_CACHELINE_SIZE 16
248 #define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
249 CONFIG_SYS_INIT_RAM_SIZE - 8)
250 #define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
251 CONFIG_SYS_INIT_RAM_SIZE - 4)
252 #define CONFIG_SYS_ICACHE_INV (CF_CACR_BCINVA + CF_CACR_ICINVA + \
254 #define CONFIG_SYS_DCACHE_INV (CF_CACR_DCINVA)
255 #define CONFIG_SYS_CACHE_ACR2 (CONFIG_SYS_SDRAM_BASE | \
256 CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
257 CF_ACR_EN | CF_ACR_SM_ALL)
258 #define CONFIG_SYS_CACHE_ICACR (CF_CACR_BEC | CF_CACR_BCINVA | \
259 CF_CACR_IEC | CF_CACR_ICINVA)
260 #define CONFIG_SYS_CACHE_DCACR ((CONFIG_SYS_CACHE_ICACR | \
261 CF_CACR_DEC | CF_CACR_DDCM_P | \
262 CF_CACR_DCINVA) & ~CF_CACR_ICINVA)
264 /*-----------------------------------------------------------------------
265 * Chipselect bank definitions
268 * CS0 - NOR Flash 1, 2, 4, or 8MB
275 #define CONFIG_SYS_CS0_BASE 0xFF800000
276 #define CONFIG_SYS_CS0_MASK (((CONFIG_SYS_BOOTSZ << 20) - 1) & 0xFFFF0001)
277 #define CONFIG_SYS_CS0_CTRL 0x00101980
279 #ifdef CONFIG_SYS_NOR1SZ
280 #define CONFIG_SYS_CS1_BASE 0xE0000000
281 #define CONFIG_SYS_CS1_MASK (((CONFIG_SYS_NOR1SZ << 20) - 1) & 0xFFFF0001)
282 #define CONFIG_SYS_CS1_CTRL 0x00101D80
285 #endif /* _M5475EVB_H */