3 * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
4 * Marius Groeger <mgroeger@sysgo.de>
6 * Configuation settings for the MBX8xx board.
8 * -----------------------------------------------------------------
9 * See file CREDITS for list of people who contributed to this
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License as
14 * published by the Free Software Foundation; either version 2 of
15 * the License, or (at your option) any later version.
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
29 * Added PCMCIA defines mostly taken from other U-Boot boards that
30 * have PCMCIA already working. If you find any bugs, incorrect assumptions
31 * feel free to fix them yourself and submit a patch.
32 * Rod Boyce <rod_boyce@stratexnet.com.
35 * board/config.h - configuration options, board specific
42 * High Level Configuration Options
46 #define CONFIG_MPC860 1 /* This is a MPC860 CPU */
47 #define CONFIG_MBX 1 /* ...on an MBX module */
49 #define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */
50 #undef CONFIG_8xx_CONS_SMC2
51 #undef CONFIG_8xx_CONS_NONE
52 #define CONFIG_BAUDRATE 9600
53 /* Define this to use the PCI bus */
56 #define CONFIG_CLOCKS_IN_MHZ 1 /* clocks passsed to Linux in MHz */
57 #define CONFIG_8xx_GCLK_FREQ (50000000UL)
59 #define CONFIG_BOOTDELAY -1 /* autoboot disabled */
61 #define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
63 #define CONFIG_BOOTCOMMAND "bootm 20000" /* autoboot command */
65 #define CONFIG_BOOTARGS "root=/dev/nfs rw " \
66 "nfsroot=10.0.0.2:/opt/eldk/ppc_8xx " \
67 "nfsaddrs=10.0.0.99:10.0.0.2"
69 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
70 #undef CFG_LOADS_BAUD_CHANGE /* don't allow baudrate change */
72 #undef CONFIG_WATCHDOG /* watchdog disabled */
76 * Command line configuration.
78 #define CONFIG_CMD_NET
79 #define CONFIG_CMD_DFL
80 #define CONFIG_CMD_SDRAM
81 #define CONFIG_CMD_PCMCIA
82 #define CONFIG_CMD_IDE
85 #define CONFIG_DOS_PARTITION
88 * Miscellaneous configurable options
90 #define CFG_LONGHELP /* undef to save memory */
91 #define CFG_PROMPT "=> " /* Monitor Command Prompt */
92 #undef CFG_HUSH_PARSER /* Hush parse for U-Boot */
93 #ifdef CFG_HUSH_PARSER
94 #define CFG_PROMPT_HUSH_PS2 "> "
96 #if defined(CONFIG_CMD_KGDB)
97 #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
99 #define CFG_CBSIZE 256 /* Console I/O Buffer Size */
101 #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
102 #define CFG_MAXARGS 16 /* max number of command args */
103 #define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
105 #define CFG_MEMTEST_START 0x0400000 /* memtest works on */
106 #define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
108 #define CFG_LOAD_ADDR 0x100000 /* default load address */
110 #define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
112 #define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
115 * Low Level Configuration Settings
116 * (address mappings, register initial values, etc.)
117 * You should know what you are doing if you make changes here.
120 /*-----------------------------------------------------------------------
121 * Physical memory map as defined by the MBX PGM
123 #define CFG_IMMR 0xFA200000 /* Internal Memory Mapped Register*/
124 #define CFG_NVRAM_BASE 0xFA000000 /* NVRAM */
125 #define CFG_NVRAM_OR 0xffe00000 /* w/o speed dependent flags!! */
126 #define CFG_CSR_BASE 0xFA100000 /* Control/Status Registers */
127 #define CFG_PCIMEM_BASE 0x80000000 /* PCI I/O and Memory Spaces */
128 #define CFG_PCIMEM_OR 0xA0000108
129 #define CFG_PCIBRIDGE_BASE 0xFA210000 /* PCI-Bus Bridge Registers */
130 #define CFG_PCIBRIDGE_OR 0xFFFF0108
132 /*-----------------------------------------------------------------------
133 * Definitions for initial stack pointer and data area (in DPRAM)
135 #define CFG_INIT_RAM_ADDR CFG_IMMR
136 #define CFG_INIT_RAM_END 0x2f00 /* End of used area in DPRAM */
137 #define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */
138 #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
139 #define CFG_INIT_VPD_SIZE 256 /* size in bytes reserved for vpd buffer */
140 #define CFG_INIT_VPD_OFFSET (CFG_GBL_DATA_OFFSET - CFG_INIT_VPD_SIZE)
141 #define CFG_INIT_SP_OFFSET (CFG_INIT_VPD_OFFSET-8)
143 /*-----------------------------------------------------------------------
144 * Offset in DPMEM where we keep the VPD data
146 #define CFG_DPRAMVPD (CFG_INIT_VPD_OFFSET - 0x2000)
148 /*-----------------------------------------------------------------------
149 * Start addresses for the final memory configuration
150 * (Set up by the startup code)
151 * Please note that CFG_SDRAM_BASE _must_ start at 0
153 #define CFG_SDRAM_BASE 0x00000000
154 #define CFG_FLASH_BASE 0xfe000000
156 #define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
158 #define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
160 #undef CFG_MONITOR_BASE /* 0x200000 to run U-Boot from RAM */
161 #define CFG_MONITOR_BASE CFG_FLASH_BASE
162 #define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
165 * For booting Linux, the board info and command line data
166 * have to be in the first 8 MB of memory, since this is
167 * the maximum mapped by the Linux kernel during initialization.
169 #define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
171 /*-----------------------------------------------------------------------
174 #define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
175 #define CFG_MAX_FLASH_SECT 16 /* max number of sectors on one chip */
177 #define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
178 #define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
180 /*-----------------------------------------------------------------------
181 * NVRAM Configuration
183 * Note: the MBX is special because there is already a firmware on this
184 * board: EPPC-Bug from Motorola. To avoid collisions in NVRAM Usage, we
185 * access the NVRAM at the offset 0x1000.
187 #define CFG_ENV_IS_IN_NVRAM 1 /* turn on NVRAM env feature */
188 #define CFG_ENV_ADDR (CFG_NVRAM_BASE + 0x1000)
189 #define CFG_ENV_SIZE 0x1000
191 /*-----------------------------------------------------------------------
192 * Cache Configuration
194 #define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
195 #if defined(CONFIG_CMD_KGDB)
196 #define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */
199 /*-----------------------------------------------------------------------
200 * SYPCR - System Protection Control 11-9
201 * SYPCR can only be written once after reset!
202 *-----------------------------------------------------------------------
203 * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
205 #if defined(CONFIG_WATCHDOG)
206 #define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
207 SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP)
209 #define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF)
212 /*-----------------------------------------------------------------------
213 * SIUMCR - SIU Module Configuration 11-6
214 *-----------------------------------------------------------------------
215 * PCMCIA config., multi-function pin tri-state
217 /* #define CFG_SIUMCR (SIUMCR_DBGC11 | SIUMCR_DPC | SIUMCR_MLRC10 | SIUMCR_SEME) */
218 #define CFG_SIUMCR (SIUMCR_DBGC11 | SIUMCR_DPC | SIUMCR_MLRC11 | SIUMCR_SEME | SIUMCR_BSC )
220 /*-----------------------------------------------------------------------
221 * TBSCR - Time Base Status and Control 11-26
222 *-----------------------------------------------------------------------
223 * Clear Reference Interrupt Status, Timebase freezing enabled
225 #define CFG_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
227 /*-----------------------------------------------------------------------
228 * PISCR - Periodic Interrupt Status and Control 11-31
229 *-----------------------------------------------------------------------
230 * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
232 #define CFG_PISCR (PISCR_PS | PISCR_PITF | PISCR_PTE)
234 /*-----------------------------------------------------------------------
235 * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30
236 *-----------------------------------------------------------------------
237 * Reset PLL lock status sticky bit, timer expired status bit and timer
238 * interrupt status bit - leave PLL multiplication factor unchanged !
240 #define CFG_PLPRCR (PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST)
242 /*-----------------------------------------------------------------------
243 * SCCR - System Clock and reset Control Register 15-27
244 *-----------------------------------------------------------------------
245 * Set clock output, timebase and RTC source and divider,
246 * power management and some other internal clocks
248 #define SCCR_MASK (SCCR_RTDIV | SCCR_RTSEL)
249 #define CFG_SCCR SCCR_TBS
251 /*-----------------------------------------------------------------------
253 *-----------------------------------------------------------------------
256 #define CFG_PCMCIA_MEM_ADDR (0xE0000000)
257 #define CFG_PCMCIA_MEM_SIZE ( 64 << 20 )
258 #define CFG_PCMCIA_DMA_ADDR (0xE4000000)
259 #define CFG_PCMCIA_DMA_SIZE ( 64 << 20 )
260 #define CFG_PCMCIA_ATTRB_ADDR (0xE8000000)
261 #define CFG_PCMCIA_ATTRB_SIZE ( 64 << 20 )
262 #define CFG_PCMCIA_IO_ADDR (0xEC000000)
263 #define CFG_PCMCIA_IO_SIZE ( 64 << 20 )
265 #define CFG_PCMCIA_INTERRUPT SIU_LEVEL6
267 #define CONFIG_PCMCIA_SLOT_A 1
270 /*-----------------------------------------------------------------------
271 * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter)
272 *-----------------------------------------------------------------------
275 #define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */
277 #undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
278 #undef CONFIG_IDE_LED /* LED for ide not supported */
279 #undef CONFIG_IDE_RESET /* reset for ide not supported */
281 #define CFG_IDE_MAXBUS 1 /* max. 1 IDE bus */
282 #define CFG_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */
284 #define CFG_ATA_IDE0_OFFSET 0x0000
286 #define CFG_ATA_BASE_ADDR CFG_PCMCIA_MEM_ADDR
288 /* Offset for data I/O */
289 #define CFG_ATA_DATA_OFFSET (CFG_PCMCIA_MEM_SIZE + 0x320)
291 /* Offset for normal register accesses */
292 #define CFG_ATA_REG_OFFSET (2 * CFG_PCMCIA_MEM_SIZE + 0x320)
294 /* Offset for alternate registers */
295 #define CFG_ATA_ALT_OFFSET 0x0100
297 /*-----------------------------------------------------------------------
299 *-----------------------------------------------------------------------
305 * Internal Definitions
309 #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
310 #define BOOTFLAG_WARM 0x02 /* Software reboot */
312 #endif /* __CONFIG_H */