2 * Copyright (C) 2007 Freescale Semiconductor, Inc.
4 * Copyright (C) 2011 Matrix Vision GmbH
5 * Andre Schwarz <andre.schwarz@matrix-vision.de>
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of
10 * the License, or (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
29 * High Level Configuration Options
32 #define CONFIG_MPC83xx 1
33 #define CONFIG_MPC837x 1
34 #define CONFIG_MPC8377 1
36 #define CONFIG_SYS_TEXT_BASE 0xFC000000
40 #define CONFIG_MASK_AER_AO
41 #define CONFIG_DISPLAY_AER_FULL
43 #define CONFIG_MISC_INIT_R
48 #define CONFIG_TSEC_ENET
53 #define CONFIG_83XX_CLKIN 66666667 /* in Hz */
55 #define CONFIG_83XX_GENERIC_PCIE_REGISTER_HOSES
56 #define CONFIG_SYS_CLK_FREQ CONFIG_83XX_CLKIN
59 * Hardware Reset Configuration Word stored in EEPROM.
61 #define CONFIG_SYS_HRCW_LOW 0
62 #define CONFIG_SYS_HRCW_HIGH 0
64 /* Arbiter Configuration Register */
65 #define CONFIG_SYS_ACR_PIPE_DEP 3
66 #define CONFIG_SYS_ACR_RPTCNT 3
68 /* System Priority Control Regsiter */
69 #define CONFIG_SYS_SPCR_TSECEP 3
71 /* System Clock Configuration Register */
72 #define CONFIG_SYS_SCCR_TSEC1CM 3
73 #define CONFIG_SYS_SCCR_TSEC2CM 0
74 #define CONFIG_SYS_SCCR_SDHCCM 3
75 #define CONFIG_SYS_SCCR_ENCCM 3 /* also clock for I2C-1 */
76 #define CONFIG_SYS_SCCR_USBDRCM CONFIG_SYS_SCCR_ENCCM /* must match */
77 #define CONFIG_SYS_SCCR_PCIEXP1CM 3
78 #define CONFIG_SYS_SCCR_PCIEXP2CM 3
79 #define CONFIG_SYS_SCCR_PCICM 1
80 #define CONFIG_SYS_SCCR_SATACM 0xFF
85 #define CONFIG_SYS_SICRH 0x087c0000
86 #define CONFIG_SYS_SICRL 0x40000000
89 * Output Buffer Impedance
91 #define CONFIG_SYS_OBIR 0x30000000
96 #define CONFIG_SYS_IMMR 0xE0000000
101 #define CONFIG_SYS_DDR_BASE 0x00000000
102 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE
103 #define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE
104 #define CONFIG_SYS_83XX_DDR_USES_CS0
106 #define CONFIG_SYS_DDRCDR_VALUE (DDRCDR_EN | DDRCDR_PZ_HIZ |\
107 DDRCDR_NZ_HIZ | DDRCDR_ODT |\
110 #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05
112 #define CONFIG_SYS_DDR_MODE_WEAK
113 #define CONFIG_SYS_DDR_WRITE_DATA_DELAY 2
114 #define CONFIG_SYS_DDR_CPO 0x1f
116 /* SPD table located at offset 0x20 in extended adressing ROM
117 * used for HRCW fetch after power-on reset
119 #define CONFIG_SPD_EEPROM
120 #define SPD_EEPROM_ADDRESS 0x50
121 #define SPD_EEPROM_OFFSET 0x20
122 #define SPD_EEPROM_ADDR_LEN 2
125 * The reserved memory
127 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
128 #define CONFIG_SYS_MONITOR_LEN (512*1024)
129 #define CONFIG_SYS_MALLOC_LEN (512*1024)
132 * Initial RAM Base Address Setup
134 #define CONFIG_SYS_INIT_RAM_LOCK 1
135 #define CONFIG_SYS_INIT_RAM_ADDR 0xE6000000 /* Initial RAM address */
136 #define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* End of used area in RAM */
137 #define CONFIG_SYS_GBL_DATA_SIZE 0x100 /* num bytes initial data */
138 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE -\
139 CONFIG_SYS_GBL_DATA_SIZE)
142 * Local Bus Configuration & Clock Setup
144 #define CONFIG_SYS_LCRR_DBYP LCRR_DBYP
145 #define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_8
146 #define CONFIG_SYS_LBC_LBCR 0x00000000
147 #define CONFIG_FSL_ELBC 1
150 * FLASH on the Local Bus
152 #define CONFIG_SYS_FLASH_CFI
153 #define CONFIG_FLASH_CFI_DRIVER
154 #define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
156 #define CONFIG_SYS_FLASH_BASE CONFIG_SYS_TEXT_BASE
157 #define CONFIG_SYS_FLASH_SIZE 64
159 #define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE
160 #define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_64MB)
162 #define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE | BR_PS_16 | BR_V)
163 #define CONFIG_SYS_OR0_PRELIM (CONFIG_SYS_FLASH_BASE | OR_UPM_XAM |\
164 OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 |\
165 OR_GPCM_XACS | OR_GPCM_SCY_15 | OR_GPCM_TRLX |\
166 OR_GPCM_EHTR | OR_GPCM_EAD)
168 #define CONFIG_SYS_MAX_FLASH_BANKS 1
169 #define CONFIG_SYS_MAX_FLASH_SECT 512
171 #undef CONFIG_SYS_FLASH_CHECKSUM
172 #define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Flash Erase Timeout (ms) */
173 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
176 * NAND Flash on the Local Bus
178 #define CONFIG_MTD_NAND_VERIFY_WRITE 1
179 #define CONFIG_SYS_MAX_NAND_DEVICE 1
180 #define CONFIG_NAND_FSL_ELBC 1
182 #define CONFIG_SYS_NAND_BASE 0xE0600000
183 #define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_NAND_BASE | (2<<BR_DECC_SHIFT) |\
184 BR_PS_8 | BR_MS_FCM | BR_V)
185 #define CONFIG_SYS_OR1_PRELIM (0xFFFF8000 | OR_FCM_BCTLD | OR_FCM_CST |\
186 OR_FCM_CHT | OR_FCM_SCY_1 | OR_FCM_RST |\
187 OR_FCM_TRLX | OR_FCM_EHTR)
189 #define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_NAND_BASE
190 #define CONFIG_SYS_LBLAWAR1_PRELIM 0x8000000E
195 #define CONFIG_CONS_INDEX 1
196 #define CONFIG_SYS_NS16550
197 #define CONFIG_SYS_NS16550_SERIAL
198 #define CONFIG_SYS_NS16550_REG_SIZE 1
199 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
201 #define CONFIG_SYS_BAUDRATE_TABLE \
202 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
204 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500)
205 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600)
207 #define CONFIG_CONSOLE ttyS0
208 #define CONFIG_BAUDRATE 115200
211 #define CONFIG_FSL_SERDES
212 #define CONFIG_FSL_SERDES1 0xe3000
213 #define CONFIG_FSL_SERDES2 0xe3100
215 /* Use the HUSH parser */
216 #define CONFIG_SYS_HUSH_PARSER
217 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
219 /* Pass open firmware flat tree */
220 #define CONFIG_OF_LIBFDT 1
221 #define CONFIG_OF_BOARD_SETUP 1
222 #define CONFIG_OF_STDOUT_VIA_ALIAS 1
225 #define CONFIG_HARD_I2C
226 #define CONFIG_FSL_I2C
227 #define CONFIG_I2C_MULTI_BUS
228 #define CONFIG_SYS_I2C_SPEED 120000
229 #define CONFIG_SYS_I2C_SLAVE 0x7F
230 #define CONFIG_SYS_I2C_OFFSET 0x3000
231 #define CONFIG_SYS_I2C2_OFFSET 0x3100
235 * Addresses are mapped 1-1.
237 #define CONFIG_SYS_PCI_MEM_BASE 0x80000000
238 #define CONFIG_SYS_PCI_MEM_PHYS CONFIG_SYS_PCI_MEM_BASE
239 #define CONFIG_SYS_PCI_MEM_SIZE (256 << 20)
240 #define CONFIG_SYS_PCI_MMIO_BASE 0x90000000
241 #define CONFIG_SYS_PCI_MMIO_PHYS CONFIG_SYS_PCI_MMIO_BASE
242 #define CONFIG_SYS_PCI_MMIO_SIZE (256 << 20)
243 #define CONFIG_SYS_PCI_IO_BASE 0x00000000
244 #define CONFIG_SYS_PCI_IO_PHYS 0xE0300000
245 #define CONFIG_SYS_PCI_IO_SIZE (1 << 20)
248 #define CONFIG_SYS_PCIE1_BASE 0xA0000000
249 #define CONFIG_SYS_PCIE1_CFG_BASE 0xA0000000
250 #define CONFIG_SYS_PCIE1_CFG_SIZE (128 << 20)
251 #define CONFIG_SYS_PCIE1_MEM_BASE 0xA8000000
252 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xA8000000
253 #define CONFIG_SYS_PCIE1_MEM_SIZE (256 << 20)
254 #define CONFIG_SYS_PCIE1_IO_BASE 0x00000000
255 #define CONFIG_SYS_PCIE1_IO_PHYS 0xB8000000
256 #define CONFIG_SYS_PCIE1_IO_SIZE (8 << 20)
258 #define CONFIG_SYS_PCIE2_BASE 0xC0000000
259 #define CONFIG_SYS_PCIE2_CFG_BASE 0xC0000000
260 #define CONFIG_SYS_PCIE2_CFG_SIZE (128 << 20)
261 #define CONFIG_SYS_PCIE2_MEM_BASE 0xC8000000
262 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xC8000000
263 #define CONFIG_SYS_PCIE2_MEM_SIZE (256 << 20)
264 #define CONFIG_SYS_PCIE2_IO_BASE 0x00000000
265 #define CONFIG_SYS_PCIE2_IO_PHYS 0xD8000000
266 #define CONFIG_SYS_PCIE2_IO_SIZE (8 << 20)
269 #define CONFIG_PCI_PNP
270 #define CONFIG_PCI_SCAN_SHOW
271 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */
276 #define CONFIG_GMII /* MII PHY management */
277 #define CONFIG_SYS_VSC8601_SKEWFIX
278 #define CONFIG_SYS_VSC8601_SKEW_TX 3
279 #define CONFIG_SYS_VSC8601_SKEW_RX 3
282 #define CONFIG_HAS_ETH0
283 #define CONFIG_TSEC1_NAME "TSEC0"
284 #define CONFIG_SYS_TSEC1_OFFSET 0x24000
285 #define TSEC1_PHY_ADDR 0x10
286 #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
287 #define TSEC1_PHYIDX 0
289 #define CONFIG_ETHPRIME "TSEC0"
290 #define CONFIG_HAS_ETH0
295 #define CONFIG_LIBATA
296 #define CONFIG_FSL_SATA
298 #define CONFIG_SYS_SATA_MAX_DEVICE 2
300 #define CONFIG_SYS_SATA1_OFFSET 0x18000
301 #define CONFIG_SYS_SATA1 (CONFIG_SYS_IMMR + CONFIG_SYS_SATA1_OFFSET)
302 #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA
304 #define CONFIG_SYS_SATA2_OFFSET 0x19000
305 #define CONFIG_SYS_SATA2 (CONFIG_SYS_IMMR + CONFIG_SYS_SATA2_OFFSET)
306 #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA
309 #define CONFIG_CMD_SATA
310 #define CONFIG_DOS_PARTITION
311 #define CONFIG_CMD_EXT2
316 #define CONFIG_BOOTP_BOOTFILESIZE
317 #define CONFIG_BOOTP_BOOTPATH
318 #define CONFIG_BOOTP_GATEWAY
319 #define CONFIG_BOOTP_HOSTNAME
320 #define CONFIG_BOOTP_VENDOREX
321 #define CONFIG_BOOTP_SUBNETMASK
322 #define CONFIG_BOOTP_DNS
323 #define CONFIG_BOOTP_DNS2
324 #define CONFIG_BOOTP_NTPSERVER
325 #define CONFIG_BOOTP_RANDOM_DELAY
326 #define CONFIG_BOOTP_SEND_HOSTNAME
329 * Command line configuration.
331 #include <config_cmd_default.h>
333 #define CONFIG_CMD_ASKENV
334 #define CONFIG_CMD_NAND
335 #define CONFIG_CMD_PING
336 #define CONFIG_CMD_EEPROM
337 #define CONFIG_CMD_I2C
338 #define CONFIG_CMD_MII
339 #define CONFIG_CMD_PCI
340 #define CONFIG_CMD_USB
341 #define CONFIG_CMD_SPI
342 #define CONFIG_CMD_DHCP
343 #define CONFIG_CMD_UBI
344 #define CONFIG_CMD_UBIFS
345 #define CONFIG_CMD_MTDPARTS
346 #define CONFIG_CMD_SATA
348 #define CONFIG_CMD_EXT2
349 #define CONFIG_CMD_FAT
350 #define CONFIG_CMD_JFFS2
352 #define CONFIG_RBTREE
355 #define CONFIG_MTD_DEVICE
356 #define CONFIG_MTD_PARTITIONS
358 #define CONFIG_FLASH_CFI_MTD
359 #define MTDIDS_DEFAULT "nor0=NOR,nand0=NAND"
360 #define MTDPARTS_DEFAULT "mtdparts=NOR:1M(u-boot),2M(FPGA);NAND:-(root)"
363 #define CONFIG_FIT_VERBOSE 1
365 #define CONFIG_CMDLINE_EDITING 1
366 #define CONFIG_AUTO_COMPLETE
369 * Miscellaneous configurable options
371 #define CONFIG_SYS_LONGHELP
372 #define CONFIG_SYS_LOAD_ADDR 0x2000000
373 #define CONFIG_LOADADDR 0x4000000
374 #define CONFIG_SYS_PROMPT "=> "
375 #define CONFIG_SYS_CBSIZE 256
377 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
378 #define CONFIG_SYS_MAXARGS 16
379 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
380 #define CONFIG_SYS_HZ 1000
382 #define CONFIG_LOADS_ECHO 1
383 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1
385 #define CONFIG_SYS_MEMTEST_START (60<<20)
386 #define CONFIG_SYS_MEMTEST_END (70<<20)
389 * For booting Linux, the board info and command line data
390 * have to be in the first 256 MB of memory, since this is
391 * the maximum mapped by the Linux kernel during initialization.
393 #define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* Initial Memory map for Linux */
398 #define CONFIG_SYS_HID0_INIT 0x000000000
399 #define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | \
400 HID0_ENABLE_INSTRUCTION_CACHE)
401 #define CONFIG_SYS_HID2 HID2_HBE
406 #define CONFIG_HIGH_BATS 1
408 /* DDR: cache cacheable */
409 #define CONFIG_SYS_SDRAM CONFIG_SYS_SDRAM_BASE
411 #define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM | BATL_PP_10 |\
413 #define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM | BATU_BL_256M | BATU_VS |\
415 #define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L
416 #define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U
419 #define CONFIG_SYS_IBAT1L (0)
420 #define CONFIG_SYS_IBAT1U (0)
421 #define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L
422 #define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U
424 /* IMMRBAR, PCI IO and NAND: cache-inhibit and guarded */
425 #define CONFIG_SYS_IBAT2L (CONFIG_SYS_IMMR | BATL_PP_10 |\
426 BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
427 #define CONFIG_SYS_IBAT2U (CONFIG_SYS_IMMR | BATU_BL_8M | BATU_VS |\
429 #define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L
430 #define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U
433 #define CONFIG_SYS_IBAT3L (0)
434 #define CONFIG_SYS_IBAT3U (0)
435 #define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L
436 #define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U
438 /* FLASH: icache cacheable, but dcache-inhibit and guarded */
439 #define CONFIG_SYS_IBAT4L (CONFIG_SYS_FLASH_BASE | BATL_PP_10 |\
441 #define CONFIG_SYS_IBAT4U (CONFIG_SYS_FLASH_BASE | BATU_BL_64M |\
443 #define CONFIG_SYS_DBAT4L (CONFIG_SYS_FLASH_BASE | BATL_PP_10 | \
444 BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
445 #define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U
447 /* Stack in dcache: cacheable, no memory coherence */
448 #define CONFIG_SYS_IBAT5L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_10)
449 #define CONFIG_SYS_IBAT5U (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K |\
451 #define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L
452 #define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U
454 /* PCI MEM space: cacheable */
455 #define CONFIG_SYS_IBAT6L (CONFIG_SYS_PCI_MEM_PHYS | BATL_PP_10 |\
457 #define CONFIG_SYS_IBAT6U (CONFIG_SYS_PCI_MEM_PHYS | BATU_BL_256M |\
459 #define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L
460 #define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U
462 /* PCI MMIO space: cache-inhibit and guarded */
463 #define CONFIG_SYS_IBAT7L (CONFIG_SYS_PCI_MMIO_PHYS | BATL_PP_10 | \
464 BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
465 #define CONFIG_SYS_IBAT7U (CONFIG_SYS_PCI_MMIO_PHYS | BATU_BL_256M |\
467 #define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L
468 #define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U
471 * I2C EEPROM settings
473 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50
474 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 6
475 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10
476 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
477 #define CONFIG_SYS_EEPROM_SIZE 0x4000
480 * Environment Configuration
482 #define CONFIG_SYS_FLASH_PROTECTION
483 #define CONFIG_ENV_OVERWRITE
484 #define CONFIG_ENV_IS_IN_FLASH 1
485 #define CONFIG_ENV_ADDR 0xFFD00000
486 #define CONFIG_ENV_SECT_SIZE 0x20000
487 #define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE
493 #define CONFIG_VIDEO_SM501_PCI
494 #define VIDEO_FB_LITTLE_ENDIAN
495 #define CONFIG_CMD_BMP
496 #define CONFIG_VIDEO_SM501
497 #define CONFIG_VIDEO_SM501_32BPP
498 #define CONFIG_VIDEO_SM501_FBMEM_OFFSET 0x10000
499 #define CONFIG_CFB_CONSOLE
500 #define CONFIG_VIDEO_LOGO
501 #define CONFIG_VIDEO_BMP_LOGO
502 #define CONFIG_VGA_AS_SINGLE_DEVICE
503 #define CONFIG_SPLASH_SCREEN
504 #define CONFIG_SYS_CONSOLE_IS_IN_ENV
505 #define CONFIG_VIDEO_BMP_GZIP
506 #define CONFIG_SYS_VIDEO_LOGO_MAX_SIZE (2 << 20)
511 #define CONFIG_MPC8XXX_SPI
516 #define CONFIG_SYS_USB_HOST
517 #define CONFIG_USB_EHCI
518 #define CONFIG_USB_EHCI_FSL
519 #define CONFIG_HAS_FSL_DR_USB
520 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
522 #define CONFIG_USB_STORAGE
523 #define CONFIG_USB_KEYBOARD
527 #define CONFIG_BOOTDELAY 5
528 #define CONFIG_AUTOBOOT_KEYED
529 #define CONFIG_AUTOBOOT_STOP_STR "s"
530 #define CONFIG_ZERO_BOOTDELAY_CHECK
531 #define CONFIG_RESET_TO_RETRY 1000
533 #define MV_CI MergerBox
534 #define MV_VCI MergerBox
535 #define MV_FPGA_DATA 0xfc100000
536 #define MV_FPGA_SIZE 0x00200000
538 #define CONFIG_SHOW_BOOT_PROGRESS 1
540 #define MV_KERNEL_ADDR_RAM 0x02800000
541 #define MV_DTB_ADDR_RAM 0x00600000
542 #define MV_INITRD_ADDR_RAM 0x01000000
543 #define MV_FITADDR 0xfc300000
544 #define MV_SPLAH_ADDR 0xffe00000
546 #define CONFIG_BOOTCOMMAND "run i2c_init;if test ${boot_sqfs} -eq 1;"\
547 "then; run fitboot;else;run ubiboot;fi;"
548 #define CONFIG_BOOTARGS "console=ttyS0,115200n8"
550 #define XMK_STR(x) #x
551 #define MK_STR(x) XMK_STR(x)
553 #define CONFIG_EXTRA_ENV_SETTINGS \
559 "usb_dr_mode=host\0"\
560 "bootfile=MergerBox.fit\0"\
561 "baudrate=" MK_STR(CONFIG_BAUDRATE) "\0"\
563 "fpgadata=" MK_STR(MV_FPGA_DATA) "\0"\
564 "fpgadatasize=" MK_STR(MV_FPGA_SIZE) "\0"\
565 "mv_kernel_ram=" MK_STR(MV_KERNEL_ADDR_RAM) "\0"\
566 "mv_initrd_ram=" MK_STR(MV_INITRD_ADDR_RAM) "\0"\
567 "mv_dtb_ram=" MK_STR(MV_DTB_ADDR_RAM) "\0"\
568 "uboota=" MK_STR(CONFIG_SYS_TEXT_BASE) "\0"\
569 "fitaddr=" MK_STR(MV_FITADDR) "\0"\
570 "mv_version=" U_BOOT_VERSION "\0"\
571 "mtdids=" MTDIDS_DEFAULT "\0"\
572 "mtdparts=" MTDPARTS_DEFAULT "\0"\
573 "dhcp_client_id=" MK_STR(MV_CI) "\0"\
574 "dhcp_vendor-class-identifier=" MK_STR(MV_VCI) "\0"\
575 "upd_uboot=dhcp;tftp bdi2000/u-boot-mergerbox-xp.bin;"\
576 "protect off all;erase $uboota +0xC0000;"\
577 "cp.b $loadaddr $uboota $filesize\0"\
578 "upd_fpga=dhcp;tftp MergerBox.rbf;erase $fpgadata +$fpgadatasize;"\
579 "cp.b $loadaddr $fpgadata $filesize\0"\
580 "upd_fit=dhcp;tftp MergerBox.fit;erase $fitaddr +0x1000000;"\
581 "cp.b $loadaddr $fitaddr $filesize\0"\
582 "addsqshrfs=set bootargs $bootargs root=/dev/ram ro "\
583 "rootfstype=squashfs\0"\
584 "addubirfs=set bootargs $bootargs ubi.mtd=9 root=ubi0:rootfs rw "\
585 "rootfstype=ubifs\0"\
586 "addusbrfs=set bootargs $bootargs root=/dev/sda1 rw "\
587 "rootfstype=ext3 usb-storage.delay_use=1 rootdelay=3\0"\
588 "netusbboot=bootp;run fpganetload fitnetload addusbrfs doboot\0"\
589 "netubiboot= bootp;run fpganetload fitnetload addubirfs doboot\0"\
590 "ubiboot=run fitprep addubirfs;set mv_initrd_ram -;run doboot\0"\
591 "doboot=bootm $mv_kernel_ram $mv_initrd_ram $mv_dtb_ram\0"\
592 "fitprep=imxtract $fitaddr kernel $mv_kernel_ram;"\
593 "imxtract $fitaddr ramdisk $mv_initrd_ram;"\
594 "imxtract $fitaddr fdt $mv_dtb_ram\0"\
595 "fdtprep=fdt addr $mv_dtb_ram;fdt boardsetup\0"\
596 "fitboot=run fitprep fdtprep addsqshrfs doboot\0"\
597 "i2c_init=run i2c_speed init_sdi_tx i2c_init_pll\0"\
598 "i2c_init_pll=i2c mw 65 9 2;i2c mw 65 9 0;i2c mw 65 5 2b;"\
599 "i2c mw 65 7 f;i2c mw 65 8 f;i2c mw 65 11 40;i2c mw 65 12 40;"\
600 "i2c mw 65 13 40; i2c mw 65 14 40; i2c mw 65 a 0\0"\
601 "i2c_speed=i2c dev 0;i2c speed 300000;i2c dev 1;i2c speed 120000\0"\
602 "init_sdi_tx=i2c mw 21 6 0;i2c mw 21 2 0;i2c mw 21 3 0;sleep 1;"\
603 "i2c mw 21 2 ff;i2c mw 21 3 3c\0"\
604 "splashimage=" MK_STR(MV_SPLAH_ADDR) "\0"\
613 #define CONFIG_FPGA_COUNT 1
614 #define CONFIG_FPGA CONFIG_SYS_ALTERA_CYCLON2
615 #define CONFIG_FPGA_ALTERA
616 #define CONFIG_FPGA_CYCLON2