2 * (C) Copyright 2001, 2002
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
25 * board/config.h - configuration options, board specific
31 /***********************************************************
32 * High Level Configuration Options
34 ***********************************************************/
35 #define CONFIG_405GP 1 /* This is a PPC405 CPU */
36 #define CONFIG_4xx 1 /* ...member of PPC4xx family */
37 #define CONFIG_MIP405 1 /* ...on a MIP405 board */
38 /***********************************************************
39 * Note that it may also be a MIP405T board which is a subset of the
41 ***********************************************************/
42 /***********************************************************
44 * CONFIG_BOOT_PCI is only used for first boot-up and should
45 * NOT be enabled for production bootloader
46 ***********************************************************/
47 /*#define CONFIG_BOOT_PCI 1*/
48 /***********************************************************
50 ***********************************************************/
51 #define CONFIG_SYS_CLK_FREQ 33000000 /* external frequency to pll */
53 /***********************************************************
55 ***********************************************************/
56 #define MIP405_COMMON_CMDS \
76 #if defined(CONFIG_MIP405T)
77 #define CONFIG_COMMANDS \
80 #define CONFIG_COMMANDS \
81 (MIP405_COMMON_CMDS | \
87 /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
88 #include <cmd_confdefs.h>
90 #define CFG_NAND_LEGACY
92 #define CFG_HUSH_PARSER
93 #define CFG_PROMPT_HUSH_PS2 "> "
94 /**************************************************************
96 * the MIP405 is equiped with an Atmel 24C128/256 EEPROM at address
98 * The Atmel EEPROM uses 16Bit addressing.
99 ***************************************************************/
101 #define CONFIG_HARD_I2C /* I2c with hardware support */
102 #define CFG_I2C_SPEED 50000 /* I2C speed and slave address */
103 #define CFG_I2C_SLAVE 0x7F
105 #define CFG_I2C_EEPROM_ADDR 0x53 /* EEPROM 24C128/256 */
106 #define CFG_I2C_EEPROM_ADDR_LEN 2 /* Bytes of address */
107 /* mask of address bits that overflow into the "EEPROM chip address" */
108 #undef CFG_I2C_EEPROM_ADDR_OVERFLOW
109 #define CFG_EEPROM_PAGE_WRITE_BITS 6 /* The Atmel 24C128/256 has */
110 /* 64 byte page write mode using*/
111 /* last 6 bits of the address */
112 #define CFG_EEPROM_PAGE_WRITE_ENABLE /* enable Page write */
113 #define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */
116 #define CFG_ENV_IS_IN_EEPROM 1 /* use EEPROM for environment vars */
117 #define CFG_ENV_OFFSET 0x00000 /* environment starts at the beginning of the EEPROM */
118 #define CFG_ENV_SIZE 0x00800 /* 2k bytes may be used for env vars */
120 /***************************************************************
121 * Definitions for Serial Presence Detect EEPROM address
122 * (to get SDRAM settings)
123 ***************************************************************/
124 /*#define SDRAM_EEPROM_WRITE_ADDRESS 0xA0
125 #define SDRAM_EEPROM_READ_ADDRESS 0xA1
127 /**************************************************************
128 * Environment definitions
129 **************************************************************/
130 #define CONFIG_BAUDRATE 9600 /* STD Baudrate */
131 #define CONFIG_BOOTDELAY 5
132 /* autoboot (do NOT change this set environment variable "bootdelay" to -1 instead) */
133 /* #define CONFIG_BOOT_RETRY_TIME -10 /XXX* feature is available but not enabled */
134 #define CONFIG_ZERO_BOOTDELAY_CHECK /* check console even if bootdelay = 0 */
136 #define CONFIG_BOOTCOMMAND "diskboot 400000 0:1; bootm" /* autoboot command */
137 #define CONFIG_BOOTARGS "console=ttyS0,9600 root=/dev/hda5" /* boot arguments */
139 #define CONFIG_IPADDR 10.0.0.100
140 #define CONFIG_SERVERIP 10.0.0.1
141 #define CONFIG_PREBOOT
142 /***************************************************************
143 * defines if the console is stored in the environment
144 ***************************************************************/
145 #define CFG_CONSOLE_IS_IN_ENV /* stdin, stdout and stderr are in evironment */
146 /***************************************************************
147 * defines if an overwrite_console function exists
148 *************************************************************/
149 #define CFG_CONSOLE_OVERWRITE_ROUTINE
150 #define CFG_CONSOLE_INFO_QUIET
151 /***************************************************************
152 * defines if the overwrite_console should be stored in the
154 **************************************************************/
155 #undef CFG_CONSOLE_ENV_OVERWRITE
157 /**************************************************************
159 *************************************************************/
160 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
161 #define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
163 #define CONFIG_MISC_INIT_R
164 /***********************************************************
165 * Miscellaneous configurable options
166 **********************************************************/
167 #define CFG_LONGHELP /* undef to save memory */
168 #define CFG_PROMPT "=> " /* Monitor Command Prompt */
169 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
170 #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
172 #define CFG_CBSIZE 256 /* Console I/O Buffer Size */
174 #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
175 #define CFG_MAXARGS 16 /* max number of command args */
176 #define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
178 #define CFG_MEMTEST_START 0x0100000 /* memtest works on */
179 #define CFG_MEMTEST_END 0x0C00000 /* 1 ... 12 MB in DRAM */
181 #undef CFG_EXT_SERIAL_CLOCK /* no external serial clock used */
182 #define CFG_BASE_BAUD 916667
184 /* The following table includes the supported baudrates */
185 #define CFG_BAUDRATE_TABLE \
186 { 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, \
187 57600, 115200, 230400, 460800, 921600 }
189 #define CFG_LOAD_ADDR 0x400000 /* default load address */
190 #define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */
192 #define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
194 /*-----------------------------------------------------------------------
196 *-----------------------------------------------------------------------
198 #define PCI_HOST_ADAPTER 0 /* configure as pci adapter */
199 #define PCI_HOST_FORCE 1 /* configure as pci host */
200 #define PCI_HOST_AUTO 2 /* detected via arbiter enable */
202 #define CONFIG_PCI /* include pci support */
203 #define CONFIG_PCI_HOST PCI_HOST_FORCE /* configure as pci-host */
204 #define CONFIG_PCI_PNP /* pci plug-and-play */
205 /* resource configuration */
206 #define CFG_PCI_SUBSYS_VENDORID 0x0000 /* PCI Vendor ID: to-do!!! */
207 #define CFG_PCI_SUBSYS_DEVICEID 0x0000 /* PCI Device ID: to-do!!! */
208 #define CFG_PCI_PTM1LA 0x00000000 /* point to sdram */
209 #define CFG_PCI_PTM1MS 0x80000001 /* 2GB, enable hard-wired to 1 */
210 #define CFG_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */
211 #define CFG_PCI_PTM2LA 0x00000000 /* disabled */
212 #define CFG_PCI_PTM2MS 0x00000000 /* disabled */
213 #define CFG_PCI_PTM2PCI 0x00000000 /* Host: use this pci address */
215 /*-----------------------------------------------------------------------
216 * Start addresses for the final memory configuration
217 * (Set up by the startup code)
218 * Please note that CFG_SDRAM_BASE _must_ start at 0
220 #define CFG_SDRAM_BASE 0x00000000
221 #define CFG_FLASH_BASE 0xFFF80000
222 #define CFG_MONITOR_BASE CFG_FLASH_BASE
223 #define CFG_MONITOR_LEN (512 * 1024) /* Reserve 512 kB for Monitor */
224 #define CFG_MALLOC_LEN (1024 * 1024) /* Reserve 1024 kB for malloc() */
227 * For booting Linux, the board info and command line data
228 * have to be in the first 8 MB of memory, since this is
229 * the maximum mapped by the Linux kernel during initialization.
231 #define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
232 /*-----------------------------------------------------------------------
235 #define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
236 #define CFG_MAX_FLASH_SECT 256 /* max number of sectors on one chip */
238 #define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
239 #define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
245 /* No command line, one static partition, whole device */
246 #undef CONFIG_JFFS2_CMDLINE
247 #define CONFIG_JFFS2_DEV "nor0"
248 #define CONFIG_JFFS2_PART_SIZE 0xFFFFFFFF
249 #define CONFIG_JFFS2_PART_OFFSET 0x00000000
251 /* mtdparts command line support */
252 /* Note: fake mtd_id used, no linux mtd map file */
254 #define CONFIG_JFFS2_CMDLINE
255 #define MTDIDS_DEFAULT "nor0=mip405-0"
256 #define MTDPARTS_DEFAULT "mtdparts=mip405-0:-(jffs2)"
259 /*-----------------------------------------------------------------------
260 * Cache Configuration
262 #define CFG_DCACHE_SIZE 0x4000 /* For AMCC 405GPr CPUs */
263 #define CFG_CACHELINE_SIZE 32 /* ... */
264 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
265 #define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
268 /*-----------------------------------------------------------------------
269 * Logbuffer Configuration
271 #undef CONFIG_LOGBUFFER /* supported but not enabled */
272 /*-----------------------------------------------------------------------
273 * Bootcountlimit Configuration
275 #undef CONFIG_BOOTCOUNT_LIMIT /* supported but not enabled */
277 /*-----------------------------------------------------------------------
280 #if 0 /* enable this if POST is desired (is supported but not enabled) */
281 #define CONFIG_POST (CFG_POST_MEMORY | \
288 * Init Memory Controller:
290 #define FLASH_MAX_SIZE 0x00800000 /* 8MByte max */
291 #define FLASH_BASE_PRELIM 0xFF800000 /* open the flash CS */
292 /* Size: 0=1MB, 1=2MB, 2=4MB, 3=8MB, 4=16MB, 5=32MB, 6=64MB, 7=128MB */
293 #define FLASH_SIZE_PRELIM 3 /* maximal flash FLASH size bank #0 */
295 #define CONFIG_BOARD_EARLY_INIT_F 1
297 /* Peripheral Bus Mapping */
298 #define PER_PLD_ADDR 0xF4000000 /* smallest window is 1MByte 0x10 0000*/
299 #define PER_UART0_ADDR 0xF4100000 /* smallest window is 1MByte 0x10 0000*/
300 #define PER_UART1_ADDR 0xF4200000 /* smallest window is 1MByte 0x10 0000*/
302 #define MULTI_PURPOSE_SOCKET_ADDR 0xF8000000
303 #define CONFIG_PORT_ADDR PER_PLD_ADDR + 5
306 /*-----------------------------------------------------------------------
307 * Definitions for initial stack pointer and data area (in On Chip SRAM)
309 #define CFG_TEMP_STACK_OCM 1
310 #define CFG_OCM_DATA_ADDR 0xF0000000
311 #define CFG_OCM_DATA_SIZE 0x1000
312 #define CFG_INIT_RAM_ADDR CFG_OCM_DATA_ADDR /* inside of On Chip SRAM */
313 #define CFG_INIT_RAM_END CFG_OCM_DATA_SIZE /* End of On Chip SRAM */
314 #define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */
315 #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
316 /* reserve some memory for POST and BOOT limit info */
317 #define CFG_INIT_SP_OFFSET (CFG_GBL_DATA_OFFSET - 32)
319 #ifdef CONFIG_POST /* reserve one word for POST Info */
320 #define CFG_POST_WORD_ADDR (CFG_GBL_DATA_OFFSET - 4)
323 #ifdef CONFIG_BOOTCOUNT_LIMIT /* reserve 2 word for bootcount limit */
324 #define CFG_BOOTCOUNT_ADDR (CFG_GBL_DATA_OFFSET - 12)
328 * Internal Definitions
332 #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
333 #define BOOTFLAG_WARM 0x02 /* Software reboot */
336 /***********************************************************************
337 * External peripheral base address
338 ***********************************************************************/
339 #define CFG_ISA_IO_BASE_ADDRESS 0xE8000000
341 /***********************************************************************
343 ***********************************************************************/
344 #define CONFIG_LAST_STAGE_INIT
345 /************************************************************
347 ***********************************************************/
348 #define CONFIG_MII 1 /* MII PHY management */
349 #define CONFIG_PHY_ADDR 1 /* PHY address */
350 #define CONFIG_PHY_RESET_DELAY 300 /* Intel LXT971A needs this */
351 #define CONFIG_PHY_CMD_DELAY 40 /* Intel LXT971A needs this */
352 /************************************************************
354 ***********************************************************/
355 #define CONFIG_RTC_MC146818
356 #undef CONFIG_WATCHDOG /* watchdog disabled */
358 /************************************************************
360 ************************************************************/
361 #if defined(CONFIG_MIP405T)
362 #define CFG_IDE_MAXBUS 1 /* MIP405T has only one IDE bus */
364 #define CFG_IDE_MAXBUS 2 /* max. 2 IDE busses */
367 #define CFG_IDE_MAXDEVICE (CFG_IDE_MAXBUS*2) /* max. 2 drives per IDE bus */
369 #define CFG_ATA_BASE_ADDR CFG_ISA_IO_BASE_ADDRESS /* base address */
370 #define CFG_ATA_IDE0_OFFSET 0x01F0 /* ide0 offste */
371 #define CFG_ATA_IDE1_OFFSET 0x0170 /* ide1 offset */
372 #define CFG_ATA_DATA_OFFSET 0 /* data reg offset */
373 #define CFG_ATA_REG_OFFSET 0 /* reg offset */
374 #define CFG_ATA_ALT_OFFSET 0x200 /* alternate register offset */
376 #undef CONFIG_IDE_8xx_DIRECT /* no pcmcia interface required */
377 #undef CONFIG_IDE_LED /* no led for ide supported */
378 #define CONFIG_IDE_RESET /* reset for ide supported... */
379 #define CONFIG_IDE_RESET_ROUTINE /* with a special reset function */
380 #define CONFIG_SUPPORT_VFAT
381 /************************************************************
382 * ATAPI support (experimental)
383 ************************************************************/
384 #define CONFIG_ATAPI /* enable ATAPI Support */
386 /************************************************************
387 * DISK Partition support
388 ************************************************************/
389 #define CONFIG_DOS_PARTITION
390 #define CONFIG_MAC_PARTITION
391 #define CONFIG_ISO_PARTITION /* Experimental */
393 /************************************************************
394 * Disk-On-Chip configuration
395 ************************************************************/
396 #define CFG_MAX_DOC_DEVICE 1 /* Max number of DOC devices */
397 #define CFG_DOC_SHORT_TIMEOUT
398 #define CFG_DOC_SUPPORT_2000
399 #define CFG_DOC_SUPPORT_MILLENNIUM
400 /************************************************************
402 ************************************************************/
403 #undef CONFIG_ISA_KEYBOARD
405 /************************************************************
407 ************************************************************/
408 #define CONFIG_VIDEO /*To enable video controller support */
409 #define CONFIG_VIDEO_CT69000
410 #define CONFIG_CFB_CONSOLE
411 #define CONFIG_VIDEO_LOGO
412 #define CONFIG_CONSOLE_EXTRA_INFO
413 #define CONFIG_VGA_AS_SINGLE_DEVICE
414 #define CONFIG_VIDEO_SW_CURSOR
415 #undef CONFIG_VIDEO_ONBOARD
416 /************************************************************
417 * USB support EXPERIMENTAL
418 ************************************************************/
419 #if !defined(CONFIG_MIP405T)
420 #define CONFIG_USB_UHCI
421 #define CONFIG_USB_KEYBOARD
422 #define CONFIG_USB_STORAGE
424 /* Enable needed helper functions */
425 #define CFG_DEVICE_DEREGISTER /* needs device_deregister */
427 /************************************************************
429 ************************************************************/
430 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
431 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
432 #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
435 /************************************************************
436 * support BZIP2 compression
437 ************************************************************/
438 #define CONFIG_BZIP2 1
440 /************************************************************
442 ************************************************************/
444 #define VERSION_TAG "released"
445 #if !defined(CONFIG_MIP405T)
446 #define CONFIG_ISO_STRING "MEV-10072-001"
448 #define CONFIG_ISO_STRING "MEV-10082-001"
451 #if !defined(CONFIG_BOOT_PCI)
452 #define CONFIG_IDENT_STRING "\n(c) 2003 by MPL AG Switzerland, " CONFIG_ISO_STRING " " VERSION_TAG
454 #define CONFIG_IDENT_STRING "\n(c) 2003 by MPL AG Switzerland, PCI_BOOT Version"
458 #endif /* __CONFIG_H */