2 * (C) Copyright 2001, 2002
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
25 * board/config.h - configuration options, board specific
31 /***********************************************************
32 * High Level Configuration Options
34 ***********************************************************/
35 #define CONFIG_405GP 1 /* This is a PPC405 CPU */
36 #define CONFIG_4xx 1 /* ...member of PPC4xx family */
37 #define CONFIG_MIP405 1 /* ...on a MIP405 board */
38 /***********************************************************
39 * Note that it may also be a MIP405T board which is a subset of the
41 ***********************************************************/
42 /***********************************************************
44 * CONFIG_BOOT_PCI is only used for first boot-up and should
45 * NOT be enabled for production bootloader
46 ***********************************************************/
47 /*#define CONFIG_BOOT_PCI 1*/
48 /***********************************************************
50 ***********************************************************/
51 #define CONFIG_SYS_CLK_FREQ 33000000 /* external frequency to pll */
53 /***********************************************************
55 ***********************************************************/
56 #define MIP405_COMMON_CMDS \
74 #if defined(CONFIG_MIP405T)
75 #define CONFIG_COMMANDS \
78 #define CONFIG_COMMANDS \
79 (MIP405_COMMON_CMDS | \
85 /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
86 #include <cmd_confdefs.h>
88 #define CFG_HUSH_PARSER
89 #define CFG_PROMPT_HUSH_PS2 "> "
90 /**************************************************************
92 * the MIP405 is equiped with an Atmel 24C128/256 EEPROM at address
94 * The Atmel EEPROM uses 16Bit addressing.
95 ***************************************************************/
97 #define CONFIG_HARD_I2C /* I2c with hardware support */
98 #define CFG_I2C_SPEED 50000 /* I2C speed and slave address */
99 #define CFG_I2C_SLAVE 0x7F
101 #define CFG_I2C_EEPROM_ADDR 0x53 /* EEPROM 24C128/256 */
102 #define CFG_I2C_EEPROM_ADDR_LEN 2 /* Bytes of address */
103 /* mask of address bits that overflow into the "EEPROM chip address" */
104 #undef CFG_I2C_EEPROM_ADDR_OVERFLOW
105 #define CFG_EEPROM_PAGE_WRITE_BITS 6 /* The Atmel 24C128/256 has */
106 /* 64 byte page write mode using*/
107 /* last 6 bits of the address */
108 #define CFG_EEPROM_PAGE_WRITE_ENABLE /* enable Page write */
109 #define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */
112 #define CFG_ENV_IS_IN_EEPROM 1 /* use EEPROM for environment vars */
113 #define CFG_ENV_OFFSET 0x00000 /* environment starts at the beginning of the EEPROM */
114 #define CFG_ENV_SIZE 0x00800 /* 2k bytes may be used for env vars */
116 /***************************************************************
117 * Definitions for Serial Presence Detect EEPROM address
118 * (to get SDRAM settings)
119 ***************************************************************/
120 /*#define SDRAM_EEPROM_WRITE_ADDRESS 0xA0
121 #define SDRAM_EEPROM_READ_ADDRESS 0xA1
123 /**************************************************************
124 * Environment definitions
125 **************************************************************/
126 #define CONFIG_BAUDRATE 9600 /* STD Baudrate */
127 #define CONFIG_BOOTDELAY 5
128 /* autoboot (do NOT change this set environment variable "bootdelay" to -1 instead) */
129 #define CONFIG_BOOT_RETRY_TIME -10 /* feature is avaiable but not enabled */
130 #define CONFIG_ZERO_BOOTDELAY_CHECK /* check console even if bootdelay = 0 */
132 #define CONFIG_BOOTCOMMAND "diskboot 400000 0:1; bootm" /* autoboot command */
133 #define CONFIG_BOOTARGS "console=ttyS0,9600 root=/dev/hda5" /* boot arguments */
135 #define CONFIG_IPADDR 10.0.0.100
136 #define CONFIG_SERVERIP 10.0.0.1
137 #define CONFIG_PREBOOT
138 /***************************************************************
139 * defines if the console is stored in the environment
140 ***************************************************************/
141 #define CFG_CONSOLE_IS_IN_ENV /* stdin, stdout and stderr are in evironment */
142 /***************************************************************
143 * defines if an overwrite_console function exists
144 *************************************************************/
145 #define CFG_CONSOLE_OVERWRITE_ROUTINE
146 #define CFG_CONSOLE_INFO_QUIET
147 /***************************************************************
148 * defines if the overwrite_console should be stored in the
150 **************************************************************/
151 #undef CFG_CONSOLE_ENV_OVERWRITE
153 /**************************************************************
155 *************************************************************/
156 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
157 #define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
159 #define CONFIG_MISC_INIT_R
160 /***********************************************************
161 * Miscellaneous configurable options
162 **********************************************************/
163 #define CFG_LONGHELP /* undef to save memory */
164 #define CFG_PROMPT "=> " /* Monitor Command Prompt */
165 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
166 #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
168 #define CFG_CBSIZE 256 /* Console I/O Buffer Size */
170 #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
171 #define CFG_MAXARGS 16 /* max number of command args */
172 #define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
174 #define CFG_MEMTEST_START 0x0100000 /* memtest works on */
175 #define CFG_MEMTEST_END 0x0C00000 /* 1 ... 12 MB in DRAM */
177 #undef CFG_EXT_SERIAL_CLOCK /* no external serial clock used */
178 #define CFG_BASE_BAUD 916667
180 /* The following table includes the supported baudrates */
181 #define CFG_BAUDRATE_TABLE \
182 { 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, \
183 57600, 115200, 230400, 460800, 921600 }
185 #define CFG_LOAD_ADDR 0x400000 /* default load address */
186 #define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */
188 #define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
190 /*-----------------------------------------------------------------------
192 *-----------------------------------------------------------------------
194 #define PCI_HOST_ADAPTER 0 /* configure as pci adapter */
195 #define PCI_HOST_FORCE 1 /* configure as pci host */
196 #define PCI_HOST_AUTO 2 /* detected via arbiter enable */
198 #define CONFIG_PCI /* include pci support */
199 #define CONFIG_PCI_HOST PCI_HOST_FORCE /* configure as pci-host */
200 #define CONFIG_PCI_PNP /* pci plug-and-play */
201 /* resource configuration */
202 #define CFG_PCI_SUBSYS_VENDORID 0x0000 /* PCI Vendor ID: to-do!!! */
203 #define CFG_PCI_SUBSYS_DEVICEID 0x0000 /* PCI Device ID: to-do!!! */
204 #define CFG_PCI_PTM1LA 0x00000000 /* point to sdram */
205 #define CFG_PCI_PTM1MS 0x80000001 /* 2GB, enable hard-wired to 1 */
206 #define CFG_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */
207 #define CFG_PCI_PTM2LA 0x00000000 /* disabled */
208 #define CFG_PCI_PTM2MS 0x00000000 /* disabled */
209 #define CFG_PCI_PTM2PCI 0x00000000 /* Host: use this pci address */
211 /*-----------------------------------------------------------------------
212 * Start addresses for the final memory configuration
213 * (Set up by the startup code)
214 * Please note that CFG_SDRAM_BASE _must_ start at 0
216 #define CFG_SDRAM_BASE 0x00000000
217 #define CFG_FLASH_BASE 0xFFF80000
218 #define CFG_MONITOR_BASE CFG_FLASH_BASE
219 #define CFG_MONITOR_LEN (512 * 1024) /* Reserve 512 kB for Monitor */
220 #define CFG_MALLOC_LEN (128 * 1024) /* Reserve 128 kB for malloc() */
223 * For booting Linux, the board info and command line data
224 * have to be in the first 8 MB of memory, since this is
225 * the maximum mapped by the Linux kernel during initialization.
227 #define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
228 /*-----------------------------------------------------------------------
231 #define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
232 #define CFG_MAX_FLASH_SECT 256 /* max number of sectors on one chip */
234 #define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
235 #define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
237 /*-----------------------------------------------------------------------
238 * Cache Configuration
240 #define CFG_DCACHE_SIZE 0x4000 /* For IBM 405GPr CPUs */
241 #define CFG_CACHELINE_SIZE 32 /* ... */
242 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
243 #define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
247 * Init Memory Controller:
250 #define FLASH_BASE0_PRELIM 0xFFC00000 /* FLASH bank #0 */
251 #define FLASH_BASE1_PRELIM 0 /* FLASH bank #1 */
253 #define CONFIG_BOARD_PRE_INIT
255 /* Peripheral Bus Mapping */
256 #define PER_PLD_ADDR 0xF4000000 /* smallest window is 1MByte 0x10 0000*/
257 #define PER_UART0_ADDR 0xF4100000 /* smallest window is 1MByte 0x10 0000*/
258 #define PER_UART1_ADDR 0xF4200000 /* smallest window is 1MByte 0x10 0000*/
260 #define MULTI_PURPOSE_SOCKET_ADDR 0xF8000000
261 #define CONFIG_PORT_ADDR PER_PLD_ADDR + 5
264 /*-----------------------------------------------------------------------
265 * Definitions for initial stack pointer and data area (in On Chip SRAM)
267 #define CFG_TEMP_STACK_OCM 1
268 #define CFG_OCM_DATA_ADDR 0xF0000000
269 #define CFG_OCM_DATA_SIZE 0x1000
270 #define CFG_INIT_RAM_ADDR CFG_OCM_DATA_ADDR /* inside of On Chip SRAM */
271 #define CFG_INIT_RAM_END CFG_OCM_DATA_SIZE /* End of On Chip SRAM */
272 #define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */
273 #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
274 #define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
277 * Internal Definitions
281 #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
282 #define BOOTFLAG_WARM 0x02 /* Software reboot */
285 /***********************************************************************
286 * External peripheral base address
287 ***********************************************************************/
288 #define CFG_ISA_IO_BASE_ADDRESS 0xE8000000
290 /***********************************************************************
292 ***********************************************************************/
293 #define CONFIG_LAST_STAGE_INIT
294 /************************************************************
296 ***********************************************************/
297 #define CONFIG_MII 1 /* MII PHY management */
298 #define CONFIG_PHY_ADDR 1 /* PHY address */
300 /************************************************************
302 ***********************************************************/
303 #define CONFIG_RTC_MC146818
304 #undef CONFIG_WATCHDOG /* watchdog disabled */
306 /************************************************************
308 ************************************************************/
309 #if defined(CONFIG_MIP405T)
310 #define CFG_IDE_MAXBUS 1 /* MIP405T has only one IDE bus */
312 #define CFG_IDE_MAXBUS 2 /* max. 2 IDE busses */
315 #define CFG_IDE_MAXDEVICE (CFG_IDE_MAXBUS*2) /* max. 2 drives per IDE bus */
317 #define CFG_ATA_BASE_ADDR CFG_ISA_IO_BASE_ADDRESS /* base address */
318 #define CFG_ATA_IDE0_OFFSET 0x01F0 /* ide0 offste */
319 #define CFG_ATA_IDE1_OFFSET 0x0170 /* ide1 offset */
320 #define CFG_ATA_DATA_OFFSET 0 /* data reg offset */
321 #define CFG_ATA_REG_OFFSET 0 /* reg offset */
322 #define CFG_ATA_ALT_OFFSET 0x200 /* alternate register offset */
324 #undef CONFIG_IDE_8xx_DIRECT /* no pcmcia interface required */
325 #undef CONFIG_IDE_LED /* no led for ide supported */
326 #define CONFIG_IDE_RESET /* reset for ide supported... */
327 #define CONFIG_IDE_RESET_ROUTINE /* with a special reset function */
329 /************************************************************
330 * ATAPI support (experimental)
331 ************************************************************/
332 #define CONFIG_ATAPI /* enable ATAPI Support */
334 /************************************************************
335 * SCSI support (experimental) only SYM53C8xx supported
336 ************************************************************/
337 #undef CONFIG_SCSI_SYM53C8XX
339 #ifdef CONFIG_SCSI_SYM53C8XX
340 #define CFG_SCSI_MAX_LUN 8 /* number of supported LUNs */
341 #define CFG_SCSI_MAX_SCSI_ID 7 /* maximum SCSI ID (0..6) */
342 #define CFG_SCSI_MAX_DEVICE CFG_SCSI_MAX_SCSI_ID * CFG_SCSI_MAX_LUN /* maximum Target devices */
343 #define CFG_SCSI_SPIN_UP_TIME 2
344 #endif /* CONFIG_SCSI_SYM53C8XX */
345 /************************************************************
346 * DISK Partition support
347 ************************************************************/
348 #define CONFIG_DOS_PARTITION
349 #define CONFIG_MAC_PARTITION
350 #define CONFIG_ISO_PARTITION /* Experimental */
352 /************************************************************
353 * Disk-On-Chip configuration
354 ************************************************************/
355 #define CFG_MAX_DOC_DEVICE 1 /* Max number of DOC devices */
356 #define CFG_DOC_SHORT_TIMEOUT
357 #define CFG_DOC_SUPPORT_2000
358 #define CFG_DOC_SUPPORT_MILLENNIUM
359 /************************************************************
361 ************************************************************/
362 #undef CONFIG_ISA_KEYBOARD
364 /************************************************************
366 ************************************************************/
367 #define CONFIG_VIDEO /*To enable video controller support */
368 #define CONFIG_VIDEO_CT69000
369 #define CONFIG_CFB_CONSOLE
370 #define CONFIG_VIDEO_LOGO
371 #define CONFIG_CONSOLE_EXTRA_INFO
372 #define CONFIG_VGA_AS_SINGLE_DEVICE
373 #define CONFIG_VIDEO_SW_CURSOR
374 #undef CONFIG_VIDEO_ONBOARD
375 /************************************************************
376 * USB support EXPERIMENTAL
377 ************************************************************/
378 #if !defined(CONFIG_MIP405T)
379 #define CONFIG_USB_UHCI
380 #define CONFIG_USB_KEYBOARD
381 #define CONFIG_USB_STORAGE
383 /* Enable needed helper functions */
384 #define CFG_DEVICE_DEREGISTER /* needs device_deregister */
386 /************************************************************
388 ************************************************************/
389 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
390 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
391 #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
394 /************************************************************
396 ************************************************************/
398 #define VERSION_TAG "released"
399 #if !defined(CONFIG_MIP405T)
400 #define CONFIG_ISO_STRING "MEV-10072-001"
402 #define CONFIG_ISO_STRING "MEV-10082-001"
405 #if !defined(CONFIG_BOOT_PCI)
406 #define CONFIG_IDENT_STRING "\n(c) 2003 by MPL AG Switzerland, " CONFIG_ISO_STRING " " VERSION_TAG
408 #define CONFIG_IDENT_STRING "\n(c) 2003 by MPL AG Switzerland, PCI_BOOT Version"
412 #endif /* __CONFIG_H */