2 * (C) Copyright 2001, 2002
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
5 * SPDX-License-Identifier: GPL-2.0+
9 * board/config.h - configuration options, board specific
15 /***********************************************************
16 * High Level Configuration Options
18 ***********************************************************/
19 #define CONFIG_405GP 1 /* This is a PPC405 CPU */
20 #define CONFIG_MIP405 1 /* ...on a MIP405 board */
22 #define CONFIG_SYS_TEXT_BASE 0xFFF80000
24 /***********************************************************
25 * Note that it may also be a MIP405T board which is a subset of the
27 ***********************************************************/
28 /***********************************************************
30 * CONFIG_BOOT_PCI is only used for first boot-up and should
31 * NOT be enabled for production bootloader
32 ***********************************************************/
33 /*#define CONFIG_BOOT_PCI 1*/
34 /***********************************************************
36 ***********************************************************/
37 #define CONFIG_SYS_CLK_FREQ 33000000 /* external frequency to pll */
42 #define CONFIG_BOOTP_BOOTFILESIZE
43 #define CONFIG_BOOTP_BOOTPATH
44 #define CONFIG_BOOTP_GATEWAY
45 #define CONFIG_BOOTP_HOSTNAME
48 * Command line configuration.
50 #define CONFIG_CMD_DATE
51 #define CONFIG_CMD_EEPROM
52 #define CONFIG_CMD_IDE
53 #define CONFIG_CMD_IRQ
54 #define CONFIG_CMD_JFFS2
55 #define CONFIG_CMD_PCI
56 #define CONFIG_CMD_REGINFO
57 #define CONFIG_CMD_SAVES
58 #define CONFIG_CMD_BSP
60 #if !defined(CONFIG_MIP405T)
63 /**************************************************************
65 * the MIP405 is equiped with an Atmel 24C128/256 EEPROM at address
67 * The Atmel EEPROM uses 16Bit addressing.
68 ***************************************************************/
70 #define CONFIG_SYS_I2C
71 #define CONFIG_SYS_I2C_PPC4XX
72 #define CONFIG_SYS_I2C_PPC4XX_CH0
73 #define CONFIG_SYS_I2C_PPC4XX_SPEED_0 50000
74 #define CONFIG_SYS_I2C_PPC4XX_SLAVE_0 0x7F
76 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x53 /* EEPROM 24C128/256 */
77 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 /* Bytes of address */
78 /* mask of address bits that overflow into the "EEPROM chip address" */
79 #undef CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW
80 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 6 /* The Atmel 24C128/256 has */
81 /* 64 byte page write mode using*/
82 /* last 6 bits of the address */
83 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */
85 #define CONFIG_ENV_IS_IN_EEPROM 1 /* use EEPROM for environment vars */
86 #define CONFIG_ENV_OFFSET 0x00000 /* environment starts at the beginning of the EEPROM */
87 #define CONFIG_ENV_SIZE 0x00800 /* 2k bytes may be used for env vars */
89 /***************************************************************
90 * Definitions for Serial Presence Detect EEPROM address
91 * (to get SDRAM settings)
92 ***************************************************************/
93 /*#define SDRAM_EEPROM_WRITE_ADDRESS 0xA0
94 #define SDRAM_EEPROM_READ_ADDRESS 0xA1
96 /**************************************************************
97 * Environment definitions
98 **************************************************************/
99 #define CONFIG_BAUDRATE 9600 /* STD Baudrate */
100 /* autoboot (do NOT change this set environment variable "bootdelay" to -1 instead) */
101 /* #define CONFIG_BOOT_RETRY_TIME -10 /XXX* feature is available but not enabled */
102 #define CONFIG_ZERO_BOOTDELAY_CHECK /* check console even if bootdelay = 0 */
104 #define CONFIG_BOOTCOMMAND "diskboot 400000 0:1; bootm" /* autoboot command */
105 #define CONFIG_BOOTARGS "console=ttyS0,9600 root=/dev/hda5" /* boot arguments */
107 #define CONFIG_IPADDR 10.0.0.100
108 #define CONFIG_SERVERIP 10.0.0.1
109 #define CONFIG_PREBOOT
110 /***************************************************************
111 * defines if the console is stored in the environment
112 ***************************************************************/
113 #define CONFIG_SYS_CONSOLE_IS_IN_ENV /* stdin, stdout and stderr are in evironment */
114 /***************************************************************
115 * defines if an overwrite_console function exists
116 *************************************************************/
117 #define CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE
118 #define CONFIG_SYS_CONSOLE_INFO_QUIET
119 /***************************************************************
120 * defines if the overwrite_console should be stored in the
122 **************************************************************/
123 #undef CONFIG_SYS_CONSOLE_ENV_OVERWRITE
125 /**************************************************************
127 *************************************************************/
128 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
129 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
131 #define CONFIG_MISC_INIT_R
132 /***********************************************************
133 * Miscellaneous configurable options
134 **********************************************************/
135 #define CONFIG_SYS_LONGHELP /* undef to save memory */
136 #if defined(CONFIG_CMD_KGDB)
137 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
139 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
141 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
142 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */
143 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
145 #define CONFIG_SYS_MEMTEST_START 0x0100000 /* memtest works on */
146 #define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 1 ... 12 MB in DRAM */
148 #define CONFIG_CONS_INDEX 1 /* Use UART0 */
149 #define CONFIG_SYS_NS16550_SERIAL
150 #define CONFIG_SYS_NS16550_REG_SIZE 1
151 #define CONFIG_SYS_NS16550_CLK get_serial_clock()
153 #undef CONFIG_SYS_EXT_SERIAL_CLOCK /* no external serial clock used */
154 #define CONFIG_SYS_BASE_BAUD 916667
156 /* The following table includes the supported baudrates */
157 #define CONFIG_SYS_BAUDRATE_TABLE \
158 { 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, \
159 57600, 115200, 230400, 460800, 921600 }
161 #define CONFIG_SYS_LOAD_ADDR 0x400000 /* default load address */
162 #define CONFIG_SYS_EXTBDINFO 1 /* To use extended board_into (bd_t) */
164 /*-----------------------------------------------------------------------
166 *-----------------------------------------------------------------------
168 #define PCI_HOST_ADAPTER 0 /* configure as pci adapter */
169 #define PCI_HOST_FORCE 1 /* configure as pci host */
170 #define PCI_HOST_AUTO 2 /* detected via arbiter enable */
172 #define CONFIG_PCI /* include pci support */
173 #define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */
174 #define CONFIG_PCI_HOST PCI_HOST_FORCE /* configure as pci-host */
175 #define CONFIG_PCI_PNP /* pci plug-and-play */
176 /* resource configuration */
177 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x0000 /* PCI Vendor ID: to-do!!! */
178 #define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0x0000 /* PCI Device ID: to-do!!! */
179 #define CONFIG_SYS_PCI_PTM1LA 0x00000000 /* point to sdram */
180 #define CONFIG_SYS_PCI_PTM1MS 0x80000001 /* 2GB, enable hard-wired to 1 */
181 #define CONFIG_SYS_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */
182 #define CONFIG_SYS_PCI_PTM2LA 0x00000000 /* disabled */
183 #define CONFIG_SYS_PCI_PTM2MS 0x00000000 /* disabled */
184 #define CONFIG_SYS_PCI_PTM2PCI 0x00000000 /* Host: use this pci address */
186 /*-----------------------------------------------------------------------
187 * Start addresses for the final memory configuration
188 * (Set up by the startup code)
189 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
191 #define CONFIG_SYS_SDRAM_BASE 0x00000000
192 #define CONFIG_SYS_FLASH_BASE 0xFFF80000
193 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
194 #define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 kB for Monitor */
195 #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserve 1024 kB for malloc() */
198 * For booting Linux, the board info and command line data
199 * have to be in the first 8 MB of memory, since this is
200 * the maximum mapped by the Linux kernel during initialization.
202 #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
203 /*-----------------------------------------------------------------------
206 #define CONFIG_SYS_UPDATE_FLASH_SIZE
207 #define CONFIG_SYS_FLASH_PROTECTION
208 #define CONFIG_SYS_FLASH_EMPTY_INFO
210 #define CONFIG_SYS_FLASH_CFI
211 #define CONFIG_FLASH_CFI_DRIVER
213 #define CONFIG_FLASH_SHOW_PROGRESS 45
215 #define CONFIG_SYS_MAX_FLASH_BANKS 1
216 #define CONFIG_SYS_MAX_FLASH_SECT 256
222 /* No command line, one static partition, whole device */
223 #undef CONFIG_CMD_MTDPARTS
224 #define CONFIG_JFFS2_DEV "nor0"
225 #define CONFIG_JFFS2_PART_SIZE 0xFFFFFFFF
226 #define CONFIG_JFFS2_PART_OFFSET 0x00000000
228 /* mtdparts command line support */
229 /* Note: fake mtd_id used, no linux mtd map file */
231 #define CONFIG_CMD_MTDPARTS
232 #define MTDIDS_DEFAULT "nor0=mip405-0"
233 #define MTDPARTS_DEFAULT "mtdparts=mip405-0:-(jffs2)"
236 /*-----------------------------------------------------------------------
237 * Logbuffer Configuration
239 #undef CONFIG_LOGBUFFER /* supported but not enabled */
240 /*-----------------------------------------------------------------------
241 * Bootcountlimit Configuration
243 #undef CONFIG_BOOTCOUNT_LIMIT /* supported but not enabled */
245 /*-----------------------------------------------------------------------
248 #if 0 /* enable this if POST is desired (is supported but not enabled) */
249 #define CONFIG_POST (CONFIG_SYS_POST_MEMORY | \
250 CONFIG_SYS_POST_CPU | \
251 CONFIG_SYS_POST_RTC | \
256 * Init Memory Controller:
258 #define FLASH_MAX_SIZE 0x00800000 /* 8MByte max */
259 #define FLASH_BASE_PRELIM 0xFF800000 /* open the flash CS */
260 /* Size: 0=1MB, 1=2MB, 2=4MB, 3=8MB, 4=16MB, 5=32MB, 6=64MB, 7=128MB */
261 #define FLASH_SIZE_PRELIM 3 /* maximal flash FLASH size bank #0 */
263 #define CONFIG_BOARD_EARLY_INIT_F 1
264 #define CONFIG_BOARD_EARLY_INIT_R
266 /* Peripheral Bus Mapping */
267 #define PER_PLD_ADDR 0xF4000000 /* smallest window is 1MByte 0x10 0000*/
268 #define PER_UART0_ADDR 0xF4100000 /* smallest window is 1MByte 0x10 0000*/
269 #define PER_UART1_ADDR 0xF4200000 /* smallest window is 1MByte 0x10 0000*/
271 #define MULTI_PURPOSE_SOCKET_ADDR 0xF8000000
272 #define CONFIG_PORT_ADDR PER_PLD_ADDR + 5
274 /*-----------------------------------------------------------------------
275 * Definitions for initial stack pointer and data area (in On Chip SRAM)
277 #define CONFIG_SYS_TEMP_STACK_OCM 1
278 #define CONFIG_SYS_OCM_DATA_ADDR 0xF0000000
279 #define CONFIG_SYS_OCM_DATA_SIZE 0x1000
280 #define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_OCM_DATA_ADDR /* inside of On Chip SRAM */
281 #define CONFIG_SYS_INIT_RAM_SIZE CONFIG_SYS_OCM_DATA_SIZE /* Size of On Chip SRAM */
282 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
283 /* reserve some memory for POST and BOOT limit info */
284 #define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_GBL_DATA_OFFSET - 32)
286 #ifdef CONFIG_BOOTCOUNT_LIMIT /* reserve 2 word for bootcount limit */
287 #define CONFIG_SYS_BOOTCOUNT_ADDR (CONFIG_SYS_GBL_DATA_OFFSET - 12)
290 /***********************************************************************
291 * External peripheral base address
292 ***********************************************************************/
293 #define CONFIG_SYS_ISA_IO_BASE_ADDRESS 0xE8000000
295 /***********************************************************************
297 ***********************************************************************/
298 #define CONFIG_LAST_STAGE_INIT
299 /************************************************************
301 ***********************************************************/
302 #define CONFIG_PPC4xx_EMAC
303 #define CONFIG_MII 1 /* MII PHY management */
304 #define CONFIG_PHY_ADDR 1 /* PHY address */
305 #define CONFIG_PHY_RESET_DELAY 300 /* Intel LXT971A needs this */
306 #define CONFIG_PHY_CMD_DELAY 40 /* Intel LXT971A needs this */
307 /************************************************************
309 ***********************************************************/
310 #define CONFIG_RTC_MC146818
311 #undef CONFIG_WATCHDOG /* watchdog disabled */
313 /************************************************************
315 ************************************************************/
316 #if defined(CONFIG_MIP405T)
317 #define CONFIG_SYS_IDE_MAXBUS 1 /* MIP405T has only one IDE bus */
319 #define CONFIG_SYS_IDE_MAXBUS 2 /* max. 2 IDE busses */
322 #define CONFIG_SYS_IDE_MAXDEVICE (CONFIG_SYS_IDE_MAXBUS*2) /* max. 2 drives per IDE bus */
324 #define CONFIG_SYS_ATA_BASE_ADDR CONFIG_SYS_ISA_IO_BASE_ADDRESS /* base address */
325 #define CONFIG_SYS_ATA_IDE0_OFFSET 0x01F0 /* ide0 offste */
326 #define CONFIG_SYS_ATA_IDE1_OFFSET 0x0170 /* ide1 offset */
327 #define CONFIG_SYS_ATA_DATA_OFFSET 0 /* data reg offset */
328 #define CONFIG_SYS_ATA_REG_OFFSET 0 /* reg offset */
329 #define CONFIG_SYS_ATA_ALT_OFFSET 0x200 /* alternate register offset */
331 #undef CONFIG_IDE_8xx_DIRECT /* no pcmcia interface required */
332 #undef CONFIG_IDE_LED /* no led for ide supported */
333 #define CONFIG_IDE_RESET /* reset for ide supported... */
334 #define CONFIG_IDE_RESET_ROUTINE /* with a special reset function */
335 #define CONFIG_SUPPORT_VFAT
336 /************************************************************
337 * ATAPI support (experimental)
338 ************************************************************/
339 #define CONFIG_ATAPI /* enable ATAPI Support */
341 /************************************************************
342 * DISK Partition support
343 ************************************************************/
344 #define CONFIG_DOS_PARTITION
345 #define CONFIG_MAC_PARTITION
346 #define CONFIG_ISO_PARTITION /* Experimental */
348 /************************************************************
350 ************************************************************/
351 #define CONFIG_VIDEO /*To enable video controller support */
352 #define CONFIG_VIDEO_CT69000
353 #define CONFIG_CFB_CONSOLE
354 #define CONFIG_VIDEO_LOGO
355 #define CONFIG_CONSOLE_EXTRA_INFO
356 #define CONFIG_VGA_AS_SINGLE_DEVICE
357 #define CONFIG_VIDEO_SW_CURSOR
358 #undef CONFIG_VIDEO_ONBOARD
359 /************************************************************
360 * USB support EXPERIMENTAL
361 ************************************************************/
362 #if !defined(CONFIG_MIP405T)
363 #define CONFIG_USB_UHCI
364 #define CONFIG_USB_KEYBOARD
365 #define CONFIG_USB_STORAGE
367 /* Enable needed helper functions */
368 #define CONFIG_SYS_STDIO_DEREGISTER /* needs stdio_deregister */
370 /************************************************************
372 ************************************************************/
373 #if defined(CONFIG_CMD_KGDB)
374 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
377 /************************************************************
378 * support BZIP2 compression
379 ************************************************************/
380 #define CONFIG_BZIP2 1
382 /************************************************************
384 ************************************************************/
386 #define VERSION_TAG "released"
387 #if !defined(CONFIG_MIP405T)
388 #define CONFIG_ISO_STRING "MEV-10072-001"
390 #define CONFIG_ISO_STRING "MEV-10082-001"
393 #if !defined(CONFIG_BOOT_PCI)
394 #define CONFIG_IDENT_STRING "\n(c) 2003 by MPL AG Switzerland, " CONFIG_ISO_STRING " " VERSION_TAG
396 #define CONFIG_IDENT_STRING "\n(c) 2003 by MPL AG Switzerland, PCI_BOOT Version"
399 #endif /* __CONFIG_H */