2 * (C) Copyright 2001, 2002
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
25 * board/config.h - configuration options, board specific
31 /***********************************************************
32 * High Level Configuration Options
34 ***********************************************************/
35 #define CONFIG_405GP 1 /* This is a PPC405 CPU */
36 #define CONFIG_4xx 1 /* ...member of PPC4xx family */
37 #define CONFIG_MIP405 1 /* ...on a MIP405 board */
38 /***********************************************************
39 * Note that it may also be a MIP405T board which is a subset of the
41 ***********************************************************/
42 /***********************************************************
44 * CONFIG_BOOT_PCI is only used for first boot-up and should
45 * NOT be enabled for production bootloader
46 ***********************************************************/
47 /*#define CONFIG_BOOT_PCI 1*/
48 /***********************************************************
50 ***********************************************************/
51 #define CONFIG_SYS_CLK_FREQ 33000000 /* external frequency to pll */
53 /***********************************************************
55 ***********************************************************/
56 #define MIP405_COMMON_CMDS \
76 #if defined(CONFIG_MIP405T)
77 #define CONFIG_COMMANDS \
80 #define CONFIG_COMMANDS \
81 (MIP405_COMMON_CMDS | \
87 /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
88 #include <cmd_confdefs.h>
90 #define CFG_HUSH_PARSER
91 #define CFG_PROMPT_HUSH_PS2 "> "
92 /**************************************************************
94 * the MIP405 is equiped with an Atmel 24C128/256 EEPROM at address
96 * The Atmel EEPROM uses 16Bit addressing.
97 ***************************************************************/
99 #define CONFIG_HARD_I2C /* I2c with hardware support */
100 #define CFG_I2C_SPEED 50000 /* I2C speed and slave address */
101 #define CFG_I2C_SLAVE 0x7F
103 #define CFG_I2C_EEPROM_ADDR 0x53 /* EEPROM 24C128/256 */
104 #define CFG_I2C_EEPROM_ADDR_LEN 2 /* Bytes of address */
105 /* mask of address bits that overflow into the "EEPROM chip address" */
106 #undef CFG_I2C_EEPROM_ADDR_OVERFLOW
107 #define CFG_EEPROM_PAGE_WRITE_BITS 6 /* The Atmel 24C128/256 has */
108 /* 64 byte page write mode using*/
109 /* last 6 bits of the address */
110 #define CFG_EEPROM_PAGE_WRITE_ENABLE /* enable Page write */
111 #define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */
114 #define CFG_ENV_IS_IN_EEPROM 1 /* use EEPROM for environment vars */
115 #define CFG_ENV_OFFSET 0x00000 /* environment starts at the beginning of the EEPROM */
116 #define CFG_ENV_SIZE 0x00800 /* 2k bytes may be used for env vars */
118 /***************************************************************
119 * Definitions for Serial Presence Detect EEPROM address
120 * (to get SDRAM settings)
121 ***************************************************************/
122 /*#define SDRAM_EEPROM_WRITE_ADDRESS 0xA0
123 #define SDRAM_EEPROM_READ_ADDRESS 0xA1
125 /**************************************************************
126 * Environment definitions
127 **************************************************************/
128 #define CONFIG_BAUDRATE 9600 /* STD Baudrate */
129 #define CONFIG_BOOTDELAY 5
130 /* autoboot (do NOT change this set environment variable "bootdelay" to -1 instead) */
131 #define CONFIG_BOOT_RETRY_TIME -10 /* feature is avaiable but not enabled */
132 #define CONFIG_ZERO_BOOTDELAY_CHECK /* check console even if bootdelay = 0 */
134 #define CONFIG_BOOTCOMMAND "diskboot 400000 0:1; bootm" /* autoboot command */
135 #define CONFIG_BOOTARGS "console=ttyS0,9600 root=/dev/hda5" /* boot arguments */
137 #define CONFIG_IPADDR 10.0.0.100
138 #define CONFIG_SERVERIP 10.0.0.1
139 #define CONFIG_PREBOOT
140 /***************************************************************
141 * defines if the console is stored in the environment
142 ***************************************************************/
143 #define CFG_CONSOLE_IS_IN_ENV /* stdin, stdout and stderr are in evironment */
144 /***************************************************************
145 * defines if an overwrite_console function exists
146 *************************************************************/
147 #define CFG_CONSOLE_OVERWRITE_ROUTINE
148 #define CFG_CONSOLE_INFO_QUIET
149 /***************************************************************
150 * defines if the overwrite_console should be stored in the
152 **************************************************************/
153 #undef CFG_CONSOLE_ENV_OVERWRITE
155 /**************************************************************
157 *************************************************************/
158 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
159 #define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
161 #define CONFIG_MISC_INIT_R
162 /***********************************************************
163 * Miscellaneous configurable options
164 **********************************************************/
165 #define CFG_LONGHELP /* undef to save memory */
166 #define CFG_PROMPT "=> " /* Monitor Command Prompt */
167 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
168 #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
170 #define CFG_CBSIZE 256 /* Console I/O Buffer Size */
172 #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
173 #define CFG_MAXARGS 16 /* max number of command args */
174 #define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
176 #define CFG_MEMTEST_START 0x0100000 /* memtest works on */
177 #define CFG_MEMTEST_END 0x0C00000 /* 1 ... 12 MB in DRAM */
179 #undef CFG_EXT_SERIAL_CLOCK /* no external serial clock used */
180 #define CFG_BASE_BAUD 916667
182 /* The following table includes the supported baudrates */
183 #define CFG_BAUDRATE_TABLE \
184 { 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, \
185 57600, 115200, 230400, 460800, 921600 }
187 #define CFG_LOAD_ADDR 0x400000 /* default load address */
188 #define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */
190 #define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
192 /*-----------------------------------------------------------------------
194 *-----------------------------------------------------------------------
196 #define PCI_HOST_ADAPTER 0 /* configure as pci adapter */
197 #define PCI_HOST_FORCE 1 /* configure as pci host */
198 #define PCI_HOST_AUTO 2 /* detected via arbiter enable */
200 #define CONFIG_PCI /* include pci support */
201 #define CONFIG_PCI_HOST PCI_HOST_FORCE /* configure as pci-host */
202 #define CONFIG_PCI_PNP /* pci plug-and-play */
203 /* resource configuration */
204 #define CFG_PCI_SUBSYS_VENDORID 0x0000 /* PCI Vendor ID: to-do!!! */
205 #define CFG_PCI_SUBSYS_DEVICEID 0x0000 /* PCI Device ID: to-do!!! */
206 #define CFG_PCI_PTM1LA 0x00000000 /* point to sdram */
207 #define CFG_PCI_PTM1MS 0x80000001 /* 2GB, enable hard-wired to 1 */
208 #define CFG_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */
209 #define CFG_PCI_PTM2LA 0x00000000 /* disabled */
210 #define CFG_PCI_PTM2MS 0x00000000 /* disabled */
211 #define CFG_PCI_PTM2PCI 0x00000000 /* Host: use this pci address */
213 /*-----------------------------------------------------------------------
214 * Start addresses for the final memory configuration
215 * (Set up by the startup code)
216 * Please note that CFG_SDRAM_BASE _must_ start at 0
218 #define CFG_SDRAM_BASE 0x00000000
219 #define CFG_FLASH_BASE 0xFFF80000
220 #define CFG_MONITOR_BASE CFG_FLASH_BASE
221 #define CFG_MONITOR_LEN (512 * 1024) /* Reserve 512 kB for Monitor */
222 #define CFG_MALLOC_LEN (1024 * 1024) /* Reserve 1024 kB for malloc() */
225 * For booting Linux, the board info and command line data
226 * have to be in the first 8 MB of memory, since this is
227 * the maximum mapped by the Linux kernel during initialization.
229 #define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
230 /*-----------------------------------------------------------------------
233 #define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
234 #define CFG_MAX_FLASH_SECT 256 /* max number of sectors on one chip */
236 #define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
237 #define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
239 #define CFG_JFFS2_FIRST_BANK 0 /* use for JFFS2 */
240 #define CFG_JFFS2_NUM_BANKS 1 /* ! second bank contains U-Boot */
242 /*-----------------------------------------------------------------------
243 * Cache Configuration
245 #define CFG_DCACHE_SIZE 0x4000 /* For IBM 405GPr CPUs */
246 #define CFG_CACHELINE_SIZE 32 /* ... */
247 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
248 #define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
251 /*-----------------------------------------------------------------------
252 * Logbuffer Configuration
254 #undef CONFIG_LOGBUFFER /* supported but not enabled */
255 /*-----------------------------------------------------------------------
256 * Bootcountlimit Configuration
258 #undef CONFIG_BOOTCOUNT_LIMIT /* supported but not enabled */
260 /*-----------------------------------------------------------------------
263 #if 0 /* enable this if POST is desired (is supported but not enabled) */
264 #define CONFIG_POST (CFG_POST_MEMORY | \
271 * Init Memory Controller:
273 #define FLASH_MAX_SIZE 0x00800000 /* 8MByte max */
274 #define FLASH_BASE_PRELIM 0xFF800000 /* open the flash CS */
275 /* Size: 0=1MB, 1=2MB, 2=4MB, 3=8MB, 4=16MB, 5=32MB, 6=64MB, 7=128MB */
276 #define FLASH_SIZE_PRELIM 3 /* maximal flash FLASH size bank #0 */
278 #define CONFIG_BOARD_EARLY_INIT_F 1
280 /* Peripheral Bus Mapping */
281 #define PER_PLD_ADDR 0xF4000000 /* smallest window is 1MByte 0x10 0000*/
282 #define PER_UART0_ADDR 0xF4100000 /* smallest window is 1MByte 0x10 0000*/
283 #define PER_UART1_ADDR 0xF4200000 /* smallest window is 1MByte 0x10 0000*/
285 #define MULTI_PURPOSE_SOCKET_ADDR 0xF8000000
286 #define CONFIG_PORT_ADDR PER_PLD_ADDR + 5
289 /*-----------------------------------------------------------------------
290 * Definitions for initial stack pointer and data area (in On Chip SRAM)
292 #define CFG_TEMP_STACK_OCM 1
293 #define CFG_OCM_DATA_ADDR 0xF0000000
294 #define CFG_OCM_DATA_SIZE 0x1000
295 #define CFG_INIT_RAM_ADDR CFG_OCM_DATA_ADDR /* inside of On Chip SRAM */
296 #define CFG_INIT_RAM_END CFG_OCM_DATA_SIZE /* End of On Chip SRAM */
297 #define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */
298 #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
299 /* reserve some memory for POST and BOOT limit info */
300 #define CFG_INIT_SP_OFFSET (CFG_GBL_DATA_OFFSET - 32)
302 #ifdef CONFIG_POST /* reserve one word for POST Info */
303 #define CFG_POST_WORD_ADDR (CFG_GBL_DATA_OFFSET - 4)
306 #ifdef CONFIG_BOOTCOUNT_LIMIT /* reserve 2 word for bootcount limit */
307 #define CFG_BOOTCOUNT_ADDR (CFG_GBL_DATA_OFFSET - 12)
311 * Internal Definitions
315 #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
316 #define BOOTFLAG_WARM 0x02 /* Software reboot */
319 /***********************************************************************
320 * External peripheral base address
321 ***********************************************************************/
322 #define CFG_ISA_IO_BASE_ADDRESS 0xE8000000
324 /***********************************************************************
326 ***********************************************************************/
327 #define CONFIG_LAST_STAGE_INIT
328 /************************************************************
330 ***********************************************************/
331 #define CONFIG_MII 1 /* MII PHY management */
332 #define CONFIG_PHY_ADDR 1 /* PHY address */
333 #define CONFIG_PHY_RESET_DELAY 300 /* Intel LXT971A needs this */
334 #define CONFIG_PHY_CMD_DELAY 40 /* Intel LXT971A needs this */
335 /************************************************************
337 ***********************************************************/
338 #define CONFIG_RTC_MC146818
339 #undef CONFIG_WATCHDOG /* watchdog disabled */
341 /************************************************************
343 ************************************************************/
344 #if defined(CONFIG_MIP405T)
345 #define CFG_IDE_MAXBUS 1 /* MIP405T has only one IDE bus */
347 #define CFG_IDE_MAXBUS 2 /* max. 2 IDE busses */
350 #define CFG_IDE_MAXDEVICE (CFG_IDE_MAXBUS*2) /* max. 2 drives per IDE bus */
352 #define CFG_ATA_BASE_ADDR CFG_ISA_IO_BASE_ADDRESS /* base address */
353 #define CFG_ATA_IDE0_OFFSET 0x01F0 /* ide0 offste */
354 #define CFG_ATA_IDE1_OFFSET 0x0170 /* ide1 offset */
355 #define CFG_ATA_DATA_OFFSET 0 /* data reg offset */
356 #define CFG_ATA_REG_OFFSET 0 /* reg offset */
357 #define CFG_ATA_ALT_OFFSET 0x200 /* alternate register offset */
359 #undef CONFIG_IDE_8xx_DIRECT /* no pcmcia interface required */
360 #undef CONFIG_IDE_LED /* no led for ide supported */
361 #define CONFIG_IDE_RESET /* reset for ide supported... */
362 #define CONFIG_IDE_RESET_ROUTINE /* with a special reset function */
363 #define CONFIG_SUPPORT_VFAT
364 /************************************************************
365 * ATAPI support (experimental)
366 ************************************************************/
367 #define CONFIG_ATAPI /* enable ATAPI Support */
369 /************************************************************
370 * SCSI support (experimental) only SYM53C8xx supported
371 ************************************************************/
372 #undef CONFIG_SCSI_SYM53C8XX
374 #ifdef CONFIG_SCSI_SYM53C8XX
375 #define CFG_SCSI_MAX_LUN 8 /* number of supported LUNs */
376 #define CFG_SCSI_MAX_SCSI_ID 7 /* maximum SCSI ID (0..6) */
377 #define CFG_SCSI_MAX_DEVICE CFG_SCSI_MAX_SCSI_ID * CFG_SCSI_MAX_LUN /* maximum Target devices */
378 #define CFG_SCSI_SPIN_UP_TIME 2
379 #endif /* CONFIG_SCSI_SYM53C8XX */
380 /************************************************************
381 * DISK Partition support
382 ************************************************************/
383 #define CONFIG_DOS_PARTITION
384 #define CONFIG_MAC_PARTITION
385 #define CONFIG_ISO_PARTITION /* Experimental */
387 /************************************************************
388 * Disk-On-Chip configuration
389 ************************************************************/
390 #define CFG_MAX_DOC_DEVICE 1 /* Max number of DOC devices */
391 #define CFG_DOC_SHORT_TIMEOUT
392 #define CFG_DOC_SUPPORT_2000
393 #define CFG_DOC_SUPPORT_MILLENNIUM
394 /************************************************************
396 ************************************************************/
397 #undef CONFIG_ISA_KEYBOARD
399 /************************************************************
401 ************************************************************/
402 #define CONFIG_VIDEO /*To enable video controller support */
403 #define CONFIG_VIDEO_CT69000
404 #define CONFIG_CFB_CONSOLE
405 #define CONFIG_VIDEO_LOGO
406 #define CONFIG_CONSOLE_EXTRA_INFO
407 #define CONFIG_VGA_AS_SINGLE_DEVICE
408 #define CONFIG_VIDEO_SW_CURSOR
409 #undef CONFIG_VIDEO_ONBOARD
410 /************************************************************
411 * USB support EXPERIMENTAL
412 ************************************************************/
413 #if !defined(CONFIG_MIP405T)
414 #define CONFIG_USB_UHCI
415 #define CONFIG_USB_KEYBOARD
416 #define CONFIG_USB_STORAGE
418 /* Enable needed helper functions */
419 #define CFG_DEVICE_DEREGISTER /* needs device_deregister */
421 /************************************************************
423 ************************************************************/
424 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
425 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
426 #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
429 /************************************************************
430 * support BZIP2 compression
431 ************************************************************/
432 #define CONFIG_BZIP2 1
434 /************************************************************
436 ************************************************************/
438 #define VERSION_TAG "released"
439 #if !defined(CONFIG_MIP405T)
440 #define CONFIG_ISO_STRING "MEV-10072-001"
442 #define CONFIG_ISO_STRING "MEV-10082-001"
445 #if !defined(CONFIG_BOOT_PCI)
446 #define CONFIG_IDENT_STRING "\n(c) 2003 by MPL AG Switzerland, " CONFIG_ISO_STRING " " VERSION_TAG
448 #define CONFIG_IDENT_STRING "\n(c) 2003 by MPL AG Switzerland, PCI_BOOT Version"
452 #endif /* __CONFIG_H */