2 * ML2.h: ML2 specific config options
4 * Copyright 2002 Mind NV
8 * Author : Peter De Schrijver (p2@mind.be)
10 * Derived from : other configuration header files in this tree
12 * This software may be used and distributed according to the terms of
13 * the GNU General Public License (GPL) version 2, incorporated herein by
14 * reference. Drivers based on or derived from this code fall under the GPL
15 * and must retain the authorship, copyright and this license notice. This
16 * file is not a complete program and may only be used when the entire
17 * program is licensed under the GPL.
25 * High Level Configuration Options
29 #define CONFIG_405 1 /* This is a PPC405 CPU */
30 #define CONFIG_4xx 1 /* ...member of PPC4xx family */
31 #define CONFIG_ML2 1 /* ...on a ML2 board */
34 #define CFG_ENV_IS_IN_FLASH 1
36 #ifdef CFG_ENV_IS_IN_NVRAM
37 #undef CFG_ENV_IS_IN_FLASH
39 #ifdef CFG_ENV_IS_IN_FLASH
40 #undef CFG_ENV_IS_IN_NVRAM
44 #define CONFIG_BAUDRATE 9600
45 #define CONFIG_BOOTDELAY 3 /* autoboot after 3 seconds */
48 #define CONFIG_BOOTCOMMAND "bootm" /* autoboot command */
50 #define CONFIG_BOOTCOMMAND "bootp" /* autoboot command */
53 #define CONFIG_PREBOOT "fsload 0x00100000 /boot/image"
55 /* Size (bytes) of interrupt driven serial port buffer.
56 * Set to 0 to use polling instead of interrupts.
57 * Setting to 0 will also disable RTS/CTS handshaking.
60 #define CONFIG_SERIAL_SOFTWARE_FIFO 4000
62 #undef CONFIG_SERIAL_SOFTWARE_FIFO
66 #define CONFIG_BOOTARGS "root=/dev/nfs " \
67 "ip=192.168.2.176:192.168.2.190:192.168.2.79:255.255.255.0 " \
68 "nfsroot=192.168.2.190:/home/stefan/cpci405/target_ftest4"
70 #define CONFIG_BOOTARGS "root=/dev/mtdblock2 " \
71 "console=ttyS0 console=tty"
75 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
76 #define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
79 #define CONFIG_COMMANDS ( (CONFIG_CMD_DFL & (~CFG_CMD_NET) & \
80 (~CFG_CMD_RTC) & ~(CFG_CMD_PCI) & ~(CFG_CMD_I2C)) | \
84 CFG_CMD_ELF | CFG_CMD_JFFS2 )
86 /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
87 #include <cmd_confdefs.h>
89 #undef CONFIG_WATCHDOG /* watchdog disabled */
91 #define CONFIG_SYS_CLK_FREQ 50000000
93 #define CONFIG_SPD_EEPROM 1 /* use SPD EEPROM for setup */
96 * Miscellaneous configurable options
98 #define CFG_LONGHELP /* undef to save memory */
99 #define CFG_PROMPT "=> " /* Monitor Command Prompt */
100 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
101 #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
103 #define CFG_CBSIZE 256 /* Console I/O Buffer Size */
105 #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
106 #define CFG_MAXARGS 16 /* max number of command args */
107 #define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
109 #define CFG_MEMTEST_START 0x0400000 /* memtest works on */
110 #define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
113 * If CFG_EXT_SERIAL_CLOCK, then the UART divisor is 1.
114 * If CFG_405_UART_ERRATA_59, then UART divisor is 31.
115 * Otherwise, UART divisor is determined by CPU Clock and CFG_BASE_BAUD value.
116 * The Linux BASE_BAUD define should match this configuration.
117 * baseBaud = cpuClock/(uartDivisor*16)
118 * If CFG_405_UART_ERRATA_59 and 200MHz CPU clock,
119 * set Linux BASE_BAUD to 403200.
121 #undef CFG_EXT_SERIAL_CLOCK /* external serial clock */
122 #undef CFG_405_UART_ERRATA_59 /* 405GP/CR Rev. D silicon */
124 #define CFG_BASE_BAUD (3125000*16)
125 #define CFG_NS16550_CLK CFG_BASE_BAUD
126 #define CFG_DUART_CHAN 0
127 #define CFG_NS16550_COM1 0xa0001003
128 #define CFG_NS16550_COM2 0xa0011003
129 #define CFG_NS16550_REG_SIZE -4
130 #define CFG_NS16550 1
131 #define CFG_INIT_CHAN1 1
132 #define CFG_INIT_CHAN2 1
134 /* The following table includes the supported baudrates */
135 #define CFG_BAUDRATE_TABLE \
136 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200, 230400}
138 #define CFG_LOAD_ADDR 0x100000 /* default load address */
139 #define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */
141 #define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
144 /*-----------------------------------------------------------------------
145 * Start addresses for the final memory configuration
146 * (Set up by the startup code)
147 * Please note that CFG_SDRAM_BASE _must_ start at 0
149 #define CFG_SDRAM_BASE 0x00000000
150 #define CFG_FLASH_BASE 0x18000000
151 #define CFG_MONITOR_BASE CFG_FLASH_BASE
152 #define CFG_MONITOR_LEN (192 * 1024) /* Reserve 196 kB for Monitor */
153 #define CFG_MALLOC_LEN (128 * 1024) /* Reserve 128 kB for malloc() */
156 * For booting Linux, the board info and command line data
157 * have to be in the first 8 MB of memory, since this is
158 * the maximum mapped by the Linux kernel during initialization.
160 #define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
161 /*-----------------------------------------------------------------------
164 #define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
165 #define CFG_MAX_FLASH_SECT 256 /* max number of sectors on one chip */
167 #define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
168 #define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
170 /* BEG ENVIRONNEMENT FLASH */
171 #ifdef CFG_ENV_IS_IN_FLASH
172 #define CFG_ENV_OFFSET 0x00050000 /* Offset of Environment Sector */
173 #define CFG_ENV_SIZE 0x10000 /* Total Size of Environment Sector */
174 #define CFG_ENV_SECT_SIZE 0x10000 /* see README - env sector total size */
176 /* END ENVIRONNEMENT FLASH */
177 /*-----------------------------------------------------------------------
180 #define CFG_NVRAM_BASE_ADDR 0xf0000000 /* NVRAM base address */
181 #define CFG_NVRAM_SIZE 0x1ff8 /* NVRAM size */
183 #ifdef CFG_ENV_IS_IN_NVRAM
184 #define CFG_ENV_SIZE 0x1000 /* Size of Environment vars */
185 #define CFG_ENV_ADDR \
186 (CFG_NVRAM_BASE_ADDR+CFG_NVRAM_SIZE-CFG_ENV_SIZE) /* Env */
188 /*-----------------------------------------------------------------------
189 * Cache Configuration
191 #define CFG_DCACHE_SIZE 8192 /* For IBM 405 CPUs */
192 #define CFG_CACHELINE_SIZE 32 /* ... */
193 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
194 #define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
198 * Init Memory Controller:
200 * BR0/1 and OR0/1 (FLASH)
203 #define FLASH_BASE0_PRELIM CFG_FLASH_BASE /* FLASH bank #0 */
204 #define FLASH_BASE1_PRELIM 0 /* FLASH bank #1 */
207 /* Configuration Port location */
208 #define CONFIG_PORT_ADDR 0xF0000500
210 /*-----------------------------------------------------------------------
211 * Definitions for initial stack pointer and data area (in DPRAM)
214 #define CFG_INIT_RAM_ADDR 0x800000 /* inside of SDRAM */
215 #define CFG_INIT_RAM_END 0x2000 /* End of used area in RAM */
216 #define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
217 #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
218 #define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
220 /*-----------------------------------------------------------------------
221 * Definitions for Serial Presence Detect EEPROM address
222 * (to get SDRAM settings)
224 #define SPD_EEPROM_ADDRESS 0x50
227 * Internal Definitions
231 #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
232 #define BOOTFLAG_WARM 0x02 /* Software reboot */
234 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
235 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
236 #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
241 #define CFG_JFFS2_FIRST_BANK 0
242 #define CFG_JFFS2_NUM_BANKS 1
243 #define CFG_JFFS2_FIRST_SECTOR 1
244 #endif /* __CONFIG_H */