3 * Stuart Hughes <stuarth@lineo.com>
4 * This file is based on similar values for other boards found in other
5 * U-Boot config files, and some that I found in the mpc8260ads manual.
7 * Note: my board is a PILOT rev.
8 * Note: the mpc8260ads doesn't come with a proper Ethernet MAC address.
10 * (C) Copyright 2003-2004 Arabella Software Ltd.
11 * Yuli Barcohen <yuli@arabellasw.com>
12 * Added support for SDRAM DIMMs SPD EEPROM, MII, JFFS2.
13 * Ported to PQ2FADS-ZU and PQ2FADS-VR boards.
14 * Ported to MPC8272ADS board.
16 * Copyright (c) 2005 MontaVista Software, Inc.
17 * Vitaly Bordug <vbordug@ru.mvista.com>
18 * Added support for PCI bridge on MPC8272ADS
20 * Copyright (C) Freescale Semiconductor, Inc. 2006-2009.
22 * SPDX-License-Identifier: GPL-2.0+
29 * High Level Configuration Options
33 #define CONFIG_MPC8260ADS 1 /* Motorola PQ2 ADS family board */
35 #ifndef CONFIG_SYS_TEXT_BASE
36 #define CONFIG_SYS_TEXT_BASE 0xFFF00000 /* Standard: boot high */
39 #define CONFIG_CPM2 1 /* Has a CPM2 */
42 * Figure out if we are booting low via flash HRCW or high via the BCSR.
44 #if (CONFIG_SYS_TEXT_BASE != 0xFFF00000) /* Boot low (flash HRCW) */
45 # define CONFIG_SYS_LOWBOOT 1
49 #define CONFIG_SYS_8260ADS 1 /* MPC8260ADS */
50 #define CONFIG_SYS_8266ADS 2 /* MPC8266ADS */
51 #define CONFIG_SYS_PQ2FADS 3 /* PQ2FADS-ZU or PQ2FADS-VR */
52 #define CONFIG_SYS_8272ADS 4 /* MPC8272ADS */
54 #ifndef CONFIG_ADSTYPE
55 #define CONFIG_ADSTYPE CONFIG_SYS_8260ADS
56 #endif /* CONFIG_ADSTYPE */
58 #if CONFIG_ADSTYPE == CONFIG_SYS_8272ADS
59 #define CONFIG_MPC8272 1
60 #elif CONFIG_ADSTYPE == CONFIG_SYS_PQ2FADS
62 * Actually MPC8275, but the code is littered with ifdefs that
63 * apply to both, or which use this ifdef to assume board-specific
66 #define CONFIG_MPC8272 1
67 #endif /* CONFIG_ADSTYPE == CONFIG_SYS_8272ADS */
69 #define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */
70 #define CONFIG_RESET_PHY_R 1 /* Call reset_phy() */
72 /* allow serial and ethaddr to be overwritten */
73 #define CONFIG_ENV_OVERWRITE
76 * select serial console configuration
78 * if either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then
79 * CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4
82 * if CONFIG_CONS_NONE is defined, then the serial console routines must
83 * defined elsewhere (for example, on the cogent platform, there are serial
84 * ports on the motherboard which are used for the serial console - see
85 * cogent/cma101/serial.[ch]).
87 #undef CONFIG_CONS_ON_SMC /* define if console on SMC */
88 #define CONFIG_CONS_ON_SCC /* define if console on SCC */
89 #undef CONFIG_CONS_NONE /* define if console on something else */
90 #define CONFIG_CONS_INDEX 1 /* which serial channel for console */
93 * select ethernet configuration
95 * if either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected, then
96 * CONFIG_ETHER_INDEX must be set to the channel number (1-4 for SCC, 1-3
99 * if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be
100 * defined elsewhere (as for the console), or CONFIG_CMD_NET must be unset.
102 #undef CONFIG_ETHER_ON_SCC /* define if ether on SCC */
103 #define CONFIG_ETHER_ON_FCC /* define if ether on FCC */
104 #undef CONFIG_ETHER_NONE /* define if ether on something else */
106 #ifdef CONFIG_ETHER_ON_FCC
108 #define CONFIG_ETHER_INDEX 2 /* which SCC/FCC channel for ethernet */
110 #if CONFIG_ETHER_INDEX == 1
112 # define CONFIG_SYS_PHY_ADDR 0
113 # define CONFIG_SYS_CMXFCR_VALUE1 (CMXFCR_RF1CS_CLK11 | CMXFCR_TF1CS_CLK10)
114 # define CONFIG_SYS_CMXFCR_MASK1 (CMXFCR_FC1 | CMXFCR_RF1CS_MSK | CMXFCR_TF1CS_MSK)
116 #elif CONFIG_ETHER_INDEX == 2
118 #if CONFIG_ADSTYPE == CONFIG_SYS_8272ADS /* RxCLK is CLK15, TxCLK is CLK16 */
119 # define CONFIG_SYS_PHY_ADDR 3
120 # define CONFIG_SYS_CMXFCR_VALUE2 (CMXFCR_RF2CS_CLK15 | CMXFCR_TF2CS_CLK16)
121 #else /* RxCLK is CLK13, TxCLK is CLK14 */
122 # define CONFIG_SYS_PHY_ADDR 0
123 # define CONFIG_SYS_CMXFCR_VALUE2 (CMXFCR_RF2CS_CLK13 | CMXFCR_TF2CS_CLK14)
124 #endif /* CONFIG_ADSTYPE == CONFIG_SYS_8272ADS */
126 # define CONFIG_SYS_CMXFCR_MASK2 (CMXFCR_FC2 | CMXFCR_RF2CS_MSK | CMXFCR_TF2CS_MSK)
128 #endif /* CONFIG_ETHER_INDEX */
130 #define CONFIG_SYS_CPMFCR_RAMTYPE 0 /* BDs and buffers on 60x bus */
131 #define CONFIG_SYS_FCC_PSMR (FCC_PSMR_FDE | FCC_PSMR_LPB) /* Full duplex */
133 #define CONFIG_MII /* MII PHY management */
134 #define CONFIG_BITBANGMII /* bit-bang MII PHY management */
136 * GPIO pins used for bit-banged MII communications
138 #define MDIO_PORT 2 /* Port C */
139 #define MDIO_DECLARE volatile ioport_t *iop = ioport_addr ( \
140 (immap_t *) CONFIG_SYS_IMMR, MDIO_PORT )
141 #define MDC_DECLARE MDIO_DECLARE
143 #if CONFIG_ADSTYPE == CONFIG_SYS_8272ADS
144 #define CONFIG_SYS_MDIO_PIN 0x00002000 /* PC18 */
145 #define CONFIG_SYS_MDC_PIN 0x00001000 /* PC19 */
147 #define CONFIG_SYS_MDIO_PIN 0x00400000 /* PC9 */
148 #define CONFIG_SYS_MDC_PIN 0x00200000 /* PC10 */
149 #endif /* CONFIG_ADSTYPE == CONFIG_SYS_8272ADS */
151 #define MDIO_ACTIVE (iop->pdir |= CONFIG_SYS_MDIO_PIN)
152 #define MDIO_TRISTATE (iop->pdir &= ~CONFIG_SYS_MDIO_PIN)
153 #define MDIO_READ ((iop->pdat & CONFIG_SYS_MDIO_PIN) != 0)
155 #define MDIO(bit) if(bit) iop->pdat |= CONFIG_SYS_MDIO_PIN; \
156 else iop->pdat &= ~CONFIG_SYS_MDIO_PIN
158 #define MDC(bit) if(bit) iop->pdat |= CONFIG_SYS_MDC_PIN; \
159 else iop->pdat &= ~CONFIG_SYS_MDC_PIN
161 #define MIIDELAY udelay(1)
163 #endif /* CONFIG_ETHER_ON_FCC */
165 #if CONFIG_ADSTYPE >= CONFIG_SYS_PQ2FADS
166 #undef CONFIG_SPD_EEPROM /* On new boards, SDRAM is soldered */
168 #define CONFIG_HARD_I2C 1 /* To enable I2C support */
169 #define CONFIG_SYS_I2C_SPEED 100000 /* I2C speed and slave address */
170 #define CONFIG_SYS_I2C_SLAVE 0x7F
172 #if defined(CONFIG_SPD_EEPROM) && !defined(CONFIG_SPD_ADDR)
173 #define CONFIG_SPD_ADDR 0x50
175 #endif /* CONFIG_ADSTYPE >= CONFIG_SYS_PQ2FADS */
178 #if CONFIG_ADSTYPE >= CONFIG_SYS_PQ2FADS
180 #define CONFIG_PCI_INDIRECT_BRIDGE
181 #define CONFIG_PCI_PNP
182 #define CONFIG_PCI_BOOTDELAY 0
183 #define CONFIG_PCI_SCAN_SHOW
186 #ifndef CONFIG_SDRAM_PBI
187 #define CONFIG_SDRAM_PBI 0 /* By default, use bank-based interleaving */
190 #ifndef CONFIG_8260_CLKIN
191 #if CONFIG_ADSTYPE >= CONFIG_SYS_PQ2FADS
192 #define CONFIG_8260_CLKIN 100000000 /* in Hz */
194 #define CONFIG_8260_CLKIN 66000000 /* in Hz */
198 #define CONFIG_BAUDRATE 115200
200 #define CONFIG_OF_LIBFDT 1
201 #define CONFIG_OF_BOARD_SETUP 1
202 #if defined(CONFIG_OF_LIBFDT)
203 #define OF_TBCLK (bd->bi_busfreq / 4)
209 #define CONFIG_BOOTP_BOOTFILESIZE
210 #define CONFIG_BOOTP_BOOTPATH
211 #define CONFIG_BOOTP_GATEWAY
212 #define CONFIG_BOOTP_HOSTNAME
216 * Command line configuration.
218 #include <config_cmd_default.h>
220 #define CONFIG_CMD_ASKENV
221 #define CONFIG_CMD_CACHE
222 #define CONFIG_CMD_CDP
223 #define CONFIG_CMD_DHCP
224 #define CONFIG_CMD_DIAG
225 #define CONFIG_CMD_I2C
226 #define CONFIG_CMD_IMMAP
227 #define CONFIG_CMD_IRQ
228 #define CONFIG_CMD_JFFS2
229 #define CONFIG_CMD_MII
230 #define CONFIG_CMD_PCI
231 #define CONFIG_CMD_PING
232 #define CONFIG_CMD_PORTIO
233 #define CONFIG_CMD_REGINFO
234 #define CONFIG_CMD_SAVES
235 #define CONFIG_CMD_SDRAM
237 #undef CONFIG_CMD_XIMG
239 #if CONFIG_ADSTYPE == CONFIG_SYS_8272ADS
240 #undef CONFIG_CMD_SDRAM
241 #undef CONFIG_CMD_I2C
243 #elif CONFIG_ADSTYPE >= CONFIG_SYS_PQ2FADS
244 #undef CONFIG_CMD_SDRAM
245 #undef CONFIG_CMD_I2C
248 #undef CONFIG_CMD_PCI
250 #endif /* CONFIG_ADSTYPE >= CONFIG_SYS_PQ2FADS */
253 #define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
254 #define CONFIG_BOOTCOMMAND "bootm fff80000" /* autoboot command */
255 #define CONFIG_BOOTARGS "root=/dev/mtdblock2"
257 #if defined(CONFIG_CMD_KGDB)
258 #undef CONFIG_KGDB_ON_SMC /* define if kgdb on SMC */
259 #define CONFIG_KGDB_ON_SCC /* define if kgdb on SCC */
260 #undef CONFIG_KGDB_NONE /* define if kgdb on something else */
261 #define CONFIG_KGDB_INDEX 2 /* which serial channel for kgdb */
262 #define CONFIG_KGDB_BAUDRATE 115200 /* speed to run kgdb serial port at */
265 #define CONFIG_BZIP2 /* include support for bzip2 compressed images */
266 #undef CONFIG_WATCHDOG /* disable platform specific watchdog */
269 * Miscellaneous configurable options
271 #define CONFIG_SYS_HUSH_PARSER
272 #define CONFIG_SYS_LONGHELP /* undef to save memory */
273 #if defined(CONFIG_CMD_KGDB)
274 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
276 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
278 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
279 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */
280 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
282 #define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */
283 #define CONFIG_SYS_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */
285 #define CONFIG_SYS_LOAD_ADDR 0x400000 /* default load address */
287 #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
289 #define CONFIG_SYS_FLASH_BASE 0xff800000
290 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of memory banks */
291 #define CONFIG_SYS_MAX_FLASH_SECT 32 /* max num of sects on one chip */
292 #define CONFIG_SYS_FLASH_SIZE 8
293 #define CONFIG_SYS_FLASH_ERASE_TOUT 8000 /* Timeout for Flash Erase (in ms) */
294 #define CONFIG_SYS_FLASH_WRITE_TOUT 5 /* Timeout for Flash Write (in ms) */
295 #define CONFIG_SYS_FLASH_LOCK_TOUT 5 /* Timeout for Flash Set Lock Bit (in ms) */
296 #define CONFIG_SYS_FLASH_UNLOCK_TOUT 10000 /* Timeout for Flash Clear Lock Bits (in ms) */
297 #define CONFIG_SYS_FLASH_PROTECTION /* "Real" (hardware) sectors protection */
302 * Note: fake mtd_id used, no linux mtd map file
304 #define MTDIDS_DEFAULT "nor0=mpc8260ads-0"
305 #define MTDPARTS_DEFAULT "mtdparts=mpc8260ads-0:-@1m(jffs2)"
306 #define CONFIG_SYS_JFFS2_SORT_FRAGMENTS
308 /* this is stuff came out of the Motorola docs */
309 #ifndef CONFIG_SYS_LOWBOOT
310 #define CONFIG_SYS_DEFAULT_IMMR 0x0F010000
313 #define CONFIG_SYS_IMMR 0xF0000000
314 #define CONFIG_SYS_BCSR 0xF4500000
315 #if CONFIG_ADSTYPE >= CONFIG_SYS_PQ2FADS
316 #define CONFIG_SYS_PCI_INT 0xF8200000
318 #define CONFIG_SYS_SDRAM_BASE 0x00000000
319 #define CONFIG_SYS_LSDRAM_BASE 0xFD000000
321 #define RS232EN_1 0x02000002
322 #define RS232EN_2 0x01000001
323 #define FETHIEN1 0x08000008
324 #define FETH1_RST 0x04000004
325 #define FETHIEN2 0x10000000
326 #define FETH2_RST 0x08000000
327 #define BCSR_PCI_MODE 0x01000000
329 #define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR
330 #define CONFIG_SYS_INIT_RAM_SIZE 0x2000 /* Size of used area in DPRAM */
331 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
332 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
334 #ifdef CONFIG_SYS_LOWBOOT
335 /* PQ2FADS flash HRCW = 0x0EB4B645 */
336 #define CONFIG_SYS_HRCW_MASTER ( ( HRCW_BPS11 | HRCW_CIP ) |\
337 ( HRCW_L2CPC10 | HRCW_DPPC11 | HRCW_ISB100 ) |\
338 ( HRCW_BMS | HRCW_MMR11 | HRCW_LBPC01 | HRCW_APPC10 ) |\
339 ( HRCW_CS10PC01 | HRCW_MODCK_H0101 ) \
342 /* PQ2FADS BCSR HRCW = 0x0CB23645 */
343 #define CONFIG_SYS_HRCW_MASTER ( ( HRCW_BPS11 | HRCW_CIP ) |\
344 ( HRCW_L2CPC10 | HRCW_DPPC10 | HRCW_ISB010 ) |\
345 ( HRCW_BMS | HRCW_APPC10 ) |\
346 ( HRCW_MODCK_H0101 ) \
350 #define CONFIG_SYS_HRCW_SLAVE1 0
351 #define CONFIG_SYS_HRCW_SLAVE2 0
352 #define CONFIG_SYS_HRCW_SLAVE3 0
353 #define CONFIG_SYS_HRCW_SLAVE4 0
354 #define CONFIG_SYS_HRCW_SLAVE5 0
355 #define CONFIG_SYS_HRCW_SLAVE6 0
356 #define CONFIG_SYS_HRCW_SLAVE7 0
358 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
360 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
361 # define CONFIG_SYS_RAMBOOT
364 #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
365 #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
368 #define CONFIG_SYS_MALLOC_LEN (4096 << 10) /* Reserve 4 MB for malloc() */
370 #define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 KB for malloc() */
371 #endif /* CONFIG_BZIP2 */
373 #ifndef CONFIG_SYS_RAMBOOT
374 # define CONFIG_ENV_IS_IN_FLASH 1
375 # define CONFIG_ENV_SECT_SIZE 0x40000
376 # define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_ENV_SECT_SIZE)
378 # define CONFIG_ENV_IS_IN_NVRAM 1
379 # define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
380 # define CONFIG_ENV_SIZE 0x200
381 #endif /* CONFIG_SYS_RAMBOOT */
383 #define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC8260 CPU */
384 #if defined(CONFIG_CMD_KGDB)
385 # define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */
388 #define CONFIG_SYS_HID0_INIT 0
389 #define CONFIG_SYS_HID0_FINAL (HID0_ICE | HID0_IFEM | HID0_ABE )
391 #define CONFIG_SYS_HID2 0
393 #define CONFIG_SYS_SYPCR 0xFFFFFFC3
394 #define CONFIG_SYS_BCR 0x100C0000
395 #define CONFIG_SYS_SIUMCR 0x0A200000
396 #define CONFIG_SYS_SCCR SCCR_DFBRG01
397 #define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE | 0x00001801)
398 #define CONFIG_SYS_OR0_PRELIM 0xFF800876
399 #define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_BCSR | 0x00001801)
400 #define CONFIG_SYS_OR1_PRELIM 0xFFFF8010
402 /*We need to configure chip select to use CPLD PCI IC on MPC8272ADS*/
404 #if CONFIG_ADSTYPE == CONFIG_SYS_8272ADS
405 #define CONFIG_SYS_BR3_PRELIM (CONFIG_SYS_PCI_INT | 0x1801) /* PCI interrupt controller */
406 #define CONFIG_SYS_OR3_PRELIM 0xFFFF8010
407 #elif CONFIG_ADSTYPE == CONFIG_SYS_PQ2FADS
408 #define CONFIG_SYS_BR8_PRELIM (CONFIG_SYS_PCI_INT | 0x1801) /* PCI interrupt controller */
409 #define CONFIG_SYS_OR8_PRELIM 0xFFFF8010
412 #define CONFIG_SYS_RMR RMR_CSRE
413 #define CONFIG_SYS_TMCNTSC (TMCNTSC_SEC|TMCNTSC_ALR|TMCNTSC_TCF|TMCNTSC_TCE)
414 #define CONFIG_SYS_PISCR (PISCR_PS|PISCR_PTF|PISCR_PTE)
415 #define CONFIG_SYS_RCCR 0
417 #if (CONFIG_ADSTYPE == CONFIG_SYS_8266ADS) || (CONFIG_ADSTYPE == CONFIG_SYS_8272ADS)
418 #undef CONFIG_SYS_LSDRAM_BASE /* No local bus SDRAM on these boards */
419 #endif /* CONFIG_ADSTYPE == CONFIG_SYS_8266ADS */
421 #if CONFIG_ADSTYPE == CONFIG_SYS_PQ2FADS
422 #define CONFIG_SYS_OR2 0xFE002EC0
423 #define CONFIG_SYS_PSDMR 0x824B36A3
424 #define CONFIG_SYS_PSRT 0x13
425 #define CONFIG_SYS_LSDMR 0x828737A3
426 #define CONFIG_SYS_LSRT 0x13
427 #define CONFIG_SYS_MPTPR 0x2800
428 #elif CONFIG_ADSTYPE == CONFIG_SYS_8272ADS
429 #define CONFIG_SYS_OR2 0xFC002CC0
430 #define CONFIG_SYS_PSDMR 0x834E24A3
431 #define CONFIG_SYS_PSRT 0x13
432 #define CONFIG_SYS_MPTPR 0x2800
434 #define CONFIG_SYS_OR2 0xFF000CA0
435 #define CONFIG_SYS_PSDMR 0x016EB452
436 #define CONFIG_SYS_PSRT 0x21
437 #define CONFIG_SYS_LSDMR 0x0086A522
438 #define CONFIG_SYS_LSRT 0x21
439 #define CONFIG_SYS_MPTPR 0x1900
440 #endif /* CONFIG_ADSTYPE == CONFIG_SYS_PQ2FADS */
442 #define CONFIG_SYS_RESET_ADDRESS 0x04400000
444 #if CONFIG_ADSTYPE >= CONFIG_SYS_PQ2FADS
446 /* PCI Memory map (if different from default map */
447 #define CONFIG_SYS_PCI_SLV_MEM_LOCAL CONFIG_SYS_SDRAM_BASE /* Local base */
448 #define CONFIG_SYS_PCI_SLV_MEM_BUS 0x00000000 /* PCI base */
449 #define CONFIG_SYS_PICMR0_MASK_ATTRIB (PICMR_MASK_512MB | PICMR_ENABLE | \
453 * These are the windows that allow the CPU to access PCI address space.
454 * All three PCI master windows, which allow the CPU to access PCI
455 * prefetch, non prefetch, and IO space (see below), must all fit within
460 * Master window that allows the CPU to access PCI Memory (prefetch).
461 * This window will be setup with the second set of Outbound ATU registers
465 #define CONFIG_SYS_PCI_MSTR_MEM_LOCAL 0x80000000 /* Local base */
466 #define CONFIG_SYS_PCI_MSTR_MEM_BUS 0x80000000 /* PCI base */
467 #define CONFIG_SYS_CPU_PCI_MEM_START PCI_MSTR_MEM_LOCAL
468 #define CONFIG_SYS_PCI_MSTR_MEM_SIZE 0x20000000 /* 512MB */
469 #define CONFIG_SYS_POCMR0_MASK_ATTRIB (POCMR_MASK_512MB | POCMR_ENABLE | POCMR_PREFETCH_EN)
472 * Master window that allows the CPU to access PCI Memory (non-prefetch).
473 * This window will be setup with the second set of Outbound ATU registers
477 #define CONFIG_SYS_PCI_MSTR_MEMIO_LOCAL 0xA0000000 /* Local base */
478 #define CONFIG_SYS_PCI_MSTR_MEMIO_BUS 0xA0000000 /* PCI base */
479 #define CONFIG_SYS_CPU_PCI_MEMIO_START PCI_MSTR_MEMIO_LOCAL
480 #define CONFIG_SYS_PCI_MSTR_MEMIO_SIZE 0x20000000 /* 512MB */
481 #define CONFIG_SYS_POCMR1_MASK_ATTRIB (POCMR_MASK_512MB | POCMR_ENABLE)
484 * Master window that allows the CPU to access PCI IO space.
485 * This window will be setup with the first set of Outbound ATU registers
489 #define CONFIG_SYS_PCI_MSTR_IO_LOCAL 0xF6000000 /* Local base */
490 #define CONFIG_SYS_PCI_MSTR_IO_BUS 0x00000000 /* PCI base */
491 #define CONFIG_SYS_CPU_PCI_IO_START PCI_MSTR_IO_LOCAL
492 #define CONFIG_SYS_PCI_MSTR_IO_SIZE 0x02000000 /* 64MB */
493 #define CONFIG_SYS_POCMR2_MASK_ATTRIB (POCMR_MASK_32MB | POCMR_ENABLE | POCMR_PCI_IO)
496 /* PCIBR0 - for PCI IO*/
497 #define CONFIG_SYS_PCI_MSTR0_LOCAL CONFIG_SYS_PCI_MSTR_IO_LOCAL /* Local base */
498 #define CONFIG_SYS_PCIMSK0_MASK ~(CONFIG_SYS_PCI_MSTR_IO_SIZE - 1U) /* Size of window */
499 /* PCIBR1 - prefetch and non-prefetch regions joined together */
500 #define CONFIG_SYS_PCI_MSTR1_LOCAL CONFIG_SYS_PCI_MSTR_MEM_LOCAL
501 #define CONFIG_SYS_PCIMSK1_MASK ~(CONFIG_SYS_PCI_MSTR_MEM_SIZE + CONFIG_SYS_PCI_MSTR_MEMIO_SIZE - 1U)
503 #endif /* CONFIG_ADSTYPE == CONFIG_8272ADS*/
505 #define CONFIG_HAS_ETH0
507 #if CONFIG_ADSTYPE == CONFIG_SYS_8272ADS
508 #define CONFIG_HAS_ETH1
511 #define CONFIG_NETDEV eth0
512 #define CONFIG_LOADADDR 500000 /* default location for tftp and bootm */
514 #define CONFIG_EXTRA_ENV_SETTINGS \
515 "netdev=" __stringify(CONFIG_NETDEV) "\0" \
516 "tftpflash=tftpboot $loadaddr $uboot; " \
517 "protect off " __stringify(CONFIG_SYS_TEXT_BASE) \
519 "erase " __stringify(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
520 "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \
522 "protect on " __stringify(CONFIG_SYS_TEXT_BASE) \
524 "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \
527 "console=ttyCPM0\0" \
528 "setbootargs=setenv bootargs " \
529 "root=$rootdev rw console=$console,$baudrate $othbootargs\0" \
530 "setipargs=setenv bootargs nfsroot=$serverip:$rootpath " \
531 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
532 "root=$rootdev rw console=$console,$baudrate $othbootargs\0"
534 #define CONFIG_NFSBOOTCOMMAND \
535 "setenv rootdev /dev/nfs;" \
537 "tftp $loadaddr $bootfile;" \
538 "tftp $fdtaddr $fdtfile;" \
539 "bootm $loadaddr - $fdtaddr"
541 #define CONFIG_RAMBOOTCOMMAND \
542 "setenv rootdev /dev/ram;" \
544 "tftp $ramdiskaddr $ramdiskfile;" \
545 "tftp $loadaddr $bootfile;" \
546 "tftp $fdtaddr $fdtfile;" \
547 "bootm $loadaddr $ramdiskaddr $fdtaddr"
549 #endif /* __CONFIG_H */