3 * Stuart Hughes <stuarth@lineo.com>
4 * This file is based on similar values for other boards found in other
5 * U-Boot config files, and some that I found in the mpc8260ads manual.
7 * Note: my board is a PILOT rev.
8 * Note: the mpc8260ads doesn't come with a proper Ethernet MAC address.
10 * (C) Copyright 2003-2004 Arabella Software Ltd.
11 * Yuli Barcohen <yuli@arabellasw.com>
12 * Added support for SDRAM DIMMs SPD EEPROM, MII, JFFS2.
13 * Ported to PQ2FADS-ZU and PQ2FADS-VR boards.
14 * Ported to MPC8272ADS board.
16 * Copyright (c) 2005 MontaVista Software, Inc.
17 * Vitaly Bordug <vbordug@ru.mvista.com>
18 * Added support for PCI bridge on MPC8272ADS
20 * See file CREDITS for list of people who contributed to this
23 * This program is free software; you can redistribute it and/or
24 * modify it under the terms of the GNU General Public License as
25 * published by the Free Software Foundation; either version 2 of
26 * the License, or (at your option) any later version.
28 * This program is distributed in the hope that it will be useful,
29 * but WITHOUT ANY WARRANTY; without even the implied warranty of
30 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
31 * GNU General Public License for more details.
33 * You should have received a copy of the GNU General Public License
34 * along with this program; if not, write to the Free Software
35 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
43 * High Level Configuration Options
47 #define CONFIG_MPC8260ADS 1 /* Motorola PQ2 ADS family board */
49 #define CONFIG_CPM2 1 /* Has a CPM2 */
52 * Figure out if we are booting low via flash HRCW or high via the BCSR.
54 #if (TEXT_BASE != 0xFFF00000) /* Boot low (flash HRCW) */
55 # define CONFIG_SYS_LOWBOOT 1
59 #define CONFIG_SYS_8260ADS 1 /* MPC8260ADS */
60 #define CONFIG_SYS_8266ADS 2 /* MPC8266ADS */
61 #define CONFIG_SYS_PQ2FADS 3 /* PQ2FADS-ZU or PQ2FADS-VR */
62 #define CONFIG_SYS_8272ADS 4 /* MPC8272ADS */
64 #ifndef CONFIG_ADSTYPE
65 #define CONFIG_ADSTYPE CONFIG_SYS_8260ADS
66 #endif /* CONFIG_ADSTYPE */
68 #if CONFIG_ADSTYPE == CONFIG_SYS_8272ADS
69 #define CONFIG_MPC8272 1
70 #elif CONFIG_ADSTYPE == CONFIG_SYS_PQ2FADS
72 * Actually MPC8275, but the code is littered with ifdefs that
73 * apply to both, or which use this ifdef to assume board-specific
76 #define CONFIG_MPC8272 1
78 #define CONFIG_MPC8260 1
79 #endif /* CONFIG_ADSTYPE == CONFIG_SYS_8272ADS */
81 #define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */
83 /* allow serial and ethaddr to be overwritten */
84 #define CONFIG_ENV_OVERWRITE
87 * select serial console configuration
89 * if either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then
90 * CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4
93 * if CONFIG_CONS_NONE is defined, then the serial console routines must
94 * defined elsewhere (for example, on the cogent platform, there are serial
95 * ports on the motherboard which are used for the serial console - see
96 * cogent/cma101/serial.[ch]).
98 #undef CONFIG_CONS_ON_SMC /* define if console on SMC */
99 #define CONFIG_CONS_ON_SCC /* define if console on SCC */
100 #undef CONFIG_CONS_NONE /* define if console on something else */
101 #define CONFIG_CONS_INDEX 1 /* which serial channel for console */
104 * select ethernet configuration
106 * if either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected, then
107 * CONFIG_ETHER_INDEX must be set to the channel number (1-4 for SCC, 1-3
110 * if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be
111 * defined elsewhere (as for the console), or CONFIG_CMD_NET must be unset.
113 #undef CONFIG_ETHER_ON_SCC /* define if ether on SCC */
114 #define CONFIG_ETHER_ON_FCC /* define if ether on FCC */
115 #undef CONFIG_ETHER_NONE /* define if ether on something else */
117 #ifdef CONFIG_ETHER_ON_FCC
119 #define CONFIG_ETHER_INDEX 2 /* which SCC/FCC channel for ethernet */
121 #if CONFIG_ETHER_INDEX == 1
123 # define CONFIG_SYS_PHY_ADDR 0
124 # define CONFIG_SYS_CMXFCR_VALUE (CMXFCR_RF1CS_CLK11 | CMXFCR_TF1CS_CLK10)
125 # define CONFIG_SYS_CMXFCR_MASK (CMXFCR_FC1 | CMXFCR_RF1CS_MSK | CMXFCR_TF1CS_MSK)
127 #elif CONFIG_ETHER_INDEX == 2
129 #if CONFIG_ADSTYPE == CONFIG_SYS_8272ADS /* RxCLK is CLK15, TxCLK is CLK16 */
130 # define CONFIG_SYS_PHY_ADDR 3
131 # define CONFIG_SYS_CMXFCR_VALUE (CMXFCR_RF2CS_CLK15 | CMXFCR_TF2CS_CLK16)
132 #else /* RxCLK is CLK13, TxCLK is CLK14 */
133 # define CONFIG_SYS_PHY_ADDR 0
134 # define CONFIG_SYS_CMXFCR_VALUE (CMXFCR_RF2CS_CLK13 | CMXFCR_TF2CS_CLK14)
135 #endif /* CONFIG_ADSTYPE == CONFIG_SYS_8272ADS */
137 # define CONFIG_SYS_CMXFCR_MASK (CMXFCR_FC2 | CMXFCR_RF2CS_MSK | CMXFCR_TF2CS_MSK)
139 #endif /* CONFIG_ETHER_INDEX */
141 #define CONFIG_SYS_CPMFCR_RAMTYPE 0 /* BDs and buffers on 60x bus */
142 #define CONFIG_SYS_FCC_PSMR (FCC_PSMR_FDE | FCC_PSMR_LPB) /* Full duplex */
144 #define CONFIG_MII /* MII PHY management */
145 #define CONFIG_BITBANGMII /* bit-bang MII PHY management */
147 * GPIO pins used for bit-banged MII communications
149 #define MDIO_PORT 2 /* Port C */
151 #if CONFIG_ADSTYPE == CONFIG_SYS_8272ADS
152 #define CONFIG_SYS_MDIO_PIN 0x00002000 /* PC18 */
153 #define CONFIG_SYS_MDC_PIN 0x00001000 /* PC19 */
155 #define CONFIG_SYS_MDIO_PIN 0x00400000 /* PC9 */
156 #define CONFIG_SYS_MDC_PIN 0x00200000 /* PC10 */
157 #endif /* CONFIG_ADSTYPE == CONFIG_SYS_8272ADS */
159 #define MDIO_ACTIVE (iop->pdir |= CONFIG_SYS_MDIO_PIN)
160 #define MDIO_TRISTATE (iop->pdir &= ~CONFIG_SYS_MDIO_PIN)
161 #define MDIO_READ ((iop->pdat & CONFIG_SYS_MDIO_PIN) != 0)
163 #define MDIO(bit) if(bit) iop->pdat |= CONFIG_SYS_MDIO_PIN; \
164 else iop->pdat &= ~CONFIG_SYS_MDIO_PIN
166 #define MDC(bit) if(bit) iop->pdat |= CONFIG_SYS_MDC_PIN; \
167 else iop->pdat &= ~CONFIG_SYS_MDC_PIN
169 #define MIIDELAY udelay(1)
171 #endif /* CONFIG_ETHER_ON_FCC */
173 #if CONFIG_ADSTYPE >= CONFIG_SYS_PQ2FADS
174 #undef CONFIG_SPD_EEPROM /* On new boards, SDRAM is soldered */
176 #define CONFIG_HARD_I2C 1 /* To enable I2C support */
177 #define CONFIG_SYS_I2C_SPEED 100000 /* I2C speed and slave address */
178 #define CONFIG_SYS_I2C_SLAVE 0x7F
180 #if defined(CONFIG_SPD_EEPROM) && !defined(CONFIG_SPD_ADDR)
181 #define CONFIG_SPD_ADDR 0x50
183 #endif /* CONFIG_ADSTYPE >= CONFIG_SYS_PQ2FADS */
186 #if CONFIG_ADSTYPE >= CONFIG_SYS_PQ2FADS
188 #define CONFIG_PCI_PNP
189 #define CONFIG_PCI_BOOTDELAY 0
190 #define CONFIG_PCI_SCAN_SHOW
193 #ifndef CONFIG_SDRAM_PBI
194 #define CONFIG_SDRAM_PBI 0 /* By default, use bank-based interleaving */
197 #ifndef CONFIG_8260_CLKIN
198 #if CONFIG_ADSTYPE >= CONFIG_SYS_PQ2FADS
199 #define CONFIG_8260_CLKIN 100000000 /* in Hz */
201 #define CONFIG_8260_CLKIN 66000000 /* in Hz */
205 #define CONFIG_BAUDRATE 115200
207 #define CONFIG_OF_LIBFDT 1
208 #define CONFIG_OF_BOARD_SETUP 1
209 #if defined(CONFIG_OF_LIBFDT)
210 #define OF_CPU "cpu@0"
211 #define OF_TBCLK (bd->bi_busfreq / 4)
217 #define CONFIG_BOOTP_BOOTFILESIZE
218 #define CONFIG_BOOTP_BOOTPATH
219 #define CONFIG_BOOTP_GATEWAY
220 #define CONFIG_BOOTP_HOSTNAME
224 * Command line configuration.
226 #include <config_cmd_default.h>
228 #define CONFIG_CMD_ASKENV
229 #define CONFIG_CMD_CACHE
230 #define CONFIG_CMD_CDP
231 #define CONFIG_CMD_DHCP
232 #define CONFIG_CMD_DIAG
233 #define CONFIG_CMD_I2C
234 #define CONFIG_CMD_IMMAP
235 #define CONFIG_CMD_IRQ
236 #define CONFIG_CMD_JFFS2
237 #define CONFIG_CMD_MII
238 #define CONFIG_CMD_PCI
239 #define CONFIG_CMD_PING
240 #define CONFIG_CMD_PORTIO
241 #define CONFIG_CMD_REGINFO
242 #define CONFIG_CMD_SAVES
243 #define CONFIG_CMD_SDRAM
245 #undef CONFIG_CMD_XIMG
247 #if CONFIG_ADSTYPE == CONFIG_SYS_8272ADS
248 #undef CONFIG_CMD_SDRAM
249 #undef CONFIG_CMD_I2C
251 #elif CONFIG_ADSTYPE >= CONFIG_SYS_PQ2FADS
252 #undef CONFIG_CMD_SDRAM
253 #undef CONFIG_CMD_I2C
256 #undef CONFIG_CMD_PCI
258 #endif /* CONFIG_ADSTYPE >= CONFIG_SYS_PQ2FADS */
261 #define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
262 #define CONFIG_BOOTCOMMAND "bootm fff80000" /* autoboot command */
263 #define CONFIG_BOOTARGS "root=/dev/mtdblock2"
265 #if defined(CONFIG_CMD_KGDB)
266 #undef CONFIG_KGDB_ON_SMC /* define if kgdb on SMC */
267 #define CONFIG_KGDB_ON_SCC /* define if kgdb on SCC */
268 #undef CONFIG_KGDB_NONE /* define if kgdb on something else */
269 #define CONFIG_KGDB_INDEX 2 /* which serial channel for kgdb */
270 #define CONFIG_KGDB_BAUDRATE 115200 /* speed to run kgdb serial port at */
273 #define CONFIG_BZIP2 /* include support for bzip2 compressed images */
274 #undef CONFIG_WATCHDOG /* disable platform specific watchdog */
277 * Miscellaneous configurable options
279 #define CONFIG_SYS_HUSH_PARSER
280 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
281 #define CONFIG_SYS_LONGHELP /* undef to save memory */
282 #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
283 #if defined(CONFIG_CMD_KGDB)
284 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
286 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
288 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
289 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */
290 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
292 #define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */
293 #define CONFIG_SYS_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */
295 #define CONFIG_SYS_LOAD_ADDR 0x400000 /* default load address */
297 #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
299 #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
301 #define CONFIG_SYS_FLASH_BASE 0xff800000
302 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of memory banks */
303 #define CONFIG_SYS_MAX_FLASH_SECT 32 /* max num of sects on one chip */
304 #define CONFIG_SYS_FLASH_SIZE 8
305 #define CONFIG_SYS_FLASH_ERASE_TOUT 8000 /* Timeout for Flash Erase (in ms) */
306 #define CONFIG_SYS_FLASH_WRITE_TOUT 5 /* Timeout for Flash Write (in ms) */
307 #define CONFIG_SYS_FLASH_LOCK_TOUT 5 /* Timeout for Flash Set Lock Bit (in ms) */
308 #define CONFIG_SYS_FLASH_UNLOCK_TOUT 10000 /* Timeout for Flash Clear Lock Bits (in ms) */
309 #define CONFIG_SYS_FLASH_PROTECTION /* "Real" (hardware) sectors protection */
314 * Note: fake mtd_id used, no linux mtd map file
316 #define MTDIDS_DEFAULT "nor0=mpc8260ads-0"
317 #define MTDPARTS_DEFAULT "mtdparts=mpc8260ads-0:-@1m(jffs2)"
318 #define CONFIG_SYS_JFFS2_SORT_FRAGMENTS
320 /* this is stuff came out of the Motorola docs */
321 #ifndef CONFIG_SYS_LOWBOOT
322 #define CONFIG_SYS_DEFAULT_IMMR 0x0F010000
325 #define CONFIG_SYS_IMMR 0xF0000000
326 #define CONFIG_SYS_BCSR 0xF4500000
327 #if CONFIG_ADSTYPE >= CONFIG_SYS_PQ2FADS
328 #define CONFIG_SYS_PCI_INT 0xF8200000
330 #define CONFIG_SYS_SDRAM_BASE 0x00000000
331 #define CONFIG_SYS_LSDRAM_BASE 0xFD000000
333 #define RS232EN_1 0x02000002
334 #define RS232EN_2 0x01000001
335 #define FETHIEN1 0x08000008
336 #define FETH1_RST 0x04000004
337 #define FETHIEN2 0x10000000
338 #define FETH2_RST 0x08000000
339 #define BCSR_PCI_MODE 0x01000000
341 #define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR
342 #define CONFIG_SYS_INIT_RAM_END 0x2000 /* End of used area in DPRAM */
343 #define CONFIG_SYS_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
344 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
345 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
347 #ifdef CONFIG_SYS_LOWBOOT
348 /* PQ2FADS flash HRCW = 0x0EB4B645 */
349 #define CONFIG_SYS_HRCW_MASTER ( ( HRCW_BPS11 | HRCW_CIP ) |\
350 ( HRCW_L2CPC10 | HRCW_DPPC11 | HRCW_ISB100 ) |\
351 ( HRCW_BMS | HRCW_MMR11 | HRCW_LBPC01 | HRCW_APPC10 ) |\
352 ( HRCW_CS10PC01 | HRCW_MODCK_H0101 ) \
355 /* PQ2FADS BCSR HRCW = 0x0CB23645 */
356 #define CONFIG_SYS_HRCW_MASTER ( ( HRCW_BPS11 | HRCW_CIP ) |\
357 ( HRCW_L2CPC10 | HRCW_DPPC10 | HRCW_ISB010 ) |\
358 ( HRCW_BMS | HRCW_APPC10 ) |\
359 ( HRCW_MODCK_H0101 ) \
363 #define CONFIG_SYS_HRCW_SLAVE1 0
364 #define CONFIG_SYS_HRCW_SLAVE2 0
365 #define CONFIG_SYS_HRCW_SLAVE3 0
366 #define CONFIG_SYS_HRCW_SLAVE4 0
367 #define CONFIG_SYS_HRCW_SLAVE5 0
368 #define CONFIG_SYS_HRCW_SLAVE6 0
369 #define CONFIG_SYS_HRCW_SLAVE7 0
371 #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
372 #define BOOTFLAG_WARM 0x02 /* Software reboot */
374 #define CONFIG_SYS_MONITOR_BASE TEXT_BASE
375 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
376 # define CONFIG_SYS_RAMBOOT
379 #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
380 #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
383 #define CONFIG_SYS_MALLOC_LEN (4096 << 10) /* Reserve 4 MB for malloc() */
385 #define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 KB for malloc() */
386 #endif /* CONFIG_BZIP2 */
388 #ifndef CONFIG_SYS_RAMBOOT
389 # define CONFIG_ENV_IS_IN_FLASH 1
390 # define CONFIG_ENV_SECT_SIZE 0x40000
391 # define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_ENV_SECT_SIZE)
393 # define CONFIG_ENV_IS_IN_NVRAM 1
394 # define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
395 # define CONFIG_ENV_SIZE 0x200
396 #endif /* CONFIG_SYS_RAMBOOT */
398 #define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC8260 CPU */
399 #if defined(CONFIG_CMD_KGDB)
400 # define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */
403 #define CONFIG_SYS_HID0_INIT 0
404 #define CONFIG_SYS_HID0_FINAL (HID0_ICE | HID0_IFEM | HID0_ABE )
406 #define CONFIG_SYS_HID2 0
408 #define CONFIG_SYS_SYPCR 0xFFFFFFC3
409 #define CONFIG_SYS_BCR 0x100C0000
410 #define CONFIG_SYS_SIUMCR 0x0A200000
411 #define CONFIG_SYS_SCCR SCCR_DFBRG01
412 #define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE | 0x00001801)
413 #define CONFIG_SYS_OR0_PRELIM 0xFF800876
414 #define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_BCSR | 0x00001801)
415 #define CONFIG_SYS_OR1_PRELIM 0xFFFF8010
417 /*We need to configure chip select to use CPLD PCI IC on MPC8272ADS*/
419 #if CONFIG_ADSTYPE == CONFIG_SYS_8272ADS
420 #define CONFIG_SYS_BR3_PRELIM (CONFIG_SYS_PCI_INT | 0x1801) /* PCI interrupt controller */
421 #define CONFIG_SYS_OR3_PRELIM 0xFFFF8010
422 #elif CONFIG_ADSTYPE == CONFIG_SYS_PQ2FADS
423 #define CONFIG_SYS_BR8_PRELIM (CONFIG_SYS_PCI_INT | 0x1801) /* PCI interrupt controller */
424 #define CONFIG_SYS_OR8_PRELIM 0xFFFF8010
427 #define CONFIG_SYS_RMR RMR_CSRE
428 #define CONFIG_SYS_TMCNTSC (TMCNTSC_SEC|TMCNTSC_ALR|TMCNTSC_TCF|TMCNTSC_TCE)
429 #define CONFIG_SYS_PISCR (PISCR_PS|PISCR_PTF|PISCR_PTE)
430 #define CONFIG_SYS_RCCR 0
432 #if (CONFIG_ADSTYPE == CONFIG_SYS_8266ADS) || (CONFIG_ADSTYPE == CONFIG_SYS_8272ADS)
433 #undef CONFIG_SYS_LSDRAM_BASE /* No local bus SDRAM on these boards */
434 #endif /* CONFIG_ADSTYPE == CONFIG_SYS_8266ADS */
436 #if CONFIG_ADSTYPE == CONFIG_SYS_PQ2FADS
437 #define CONFIG_SYS_OR2 0xFE002EC0
438 #define CONFIG_SYS_PSDMR 0x824B36A3
439 #define CONFIG_SYS_PSRT 0x13
440 #define CONFIG_SYS_LSDMR 0x828737A3
441 #define CONFIG_SYS_LSRT 0x13
442 #define CONFIG_SYS_MPTPR 0x2800
443 #elif CONFIG_ADSTYPE == CONFIG_SYS_8272ADS
444 #define CONFIG_SYS_OR2 0xFC002CC0
445 #define CONFIG_SYS_PSDMR 0x834E24A3
446 #define CONFIG_SYS_PSRT 0x13
447 #define CONFIG_SYS_MPTPR 0x2800
449 #define CONFIG_SYS_OR2 0xFF000CA0
450 #define CONFIG_SYS_PSDMR 0x016EB452
451 #define CONFIG_SYS_PSRT 0x21
452 #define CONFIG_SYS_LSDMR 0x0086A522
453 #define CONFIG_SYS_LSRT 0x21
454 #define CONFIG_SYS_MPTPR 0x1900
455 #endif /* CONFIG_ADSTYPE == CONFIG_SYS_PQ2FADS */
457 #define CONFIG_SYS_RESET_ADDRESS 0x04400000
459 #if CONFIG_ADSTYPE >= CONFIG_SYS_PQ2FADS
461 /* PCI Memory map (if different from default map */
462 #define CONFIG_SYS_PCI_SLV_MEM_LOCAL CONFIG_SYS_SDRAM_BASE /* Local base */
463 #define CONFIG_SYS_PCI_SLV_MEM_BUS 0x00000000 /* PCI base */
464 #define CONFIG_SYS_PICMR0_MASK_ATTRIB (PICMR_MASK_512MB | PICMR_ENABLE | \
468 * These are the windows that allow the CPU to access PCI address space.
469 * All three PCI master windows, which allow the CPU to access PCI
470 * prefetch, non prefetch, and IO space (see below), must all fit within
475 * Master window that allows the CPU to access PCI Memory (prefetch).
476 * This window will be setup with the second set of Outbound ATU registers
480 #define CONFIG_SYS_PCI_MSTR_MEM_LOCAL 0x80000000 /* Local base */
481 #define CONFIG_SYS_PCI_MSTR_MEM_BUS 0x80000000 /* PCI base */
482 #define CONFIG_SYS_CPU_PCI_MEM_START PCI_MSTR_MEM_LOCAL
483 #define CONFIG_SYS_PCI_MSTR_MEM_SIZE 0x20000000 /* 512MB */
484 #define CONFIG_SYS_POCMR0_MASK_ATTRIB (POCMR_MASK_512MB | POCMR_ENABLE | POCMR_PREFETCH_EN)
487 * Master window that allows the CPU to access PCI Memory (non-prefetch).
488 * This window will be setup with the second set of Outbound ATU registers
492 #define CONFIG_SYS_PCI_MSTR_MEMIO_LOCAL 0xA0000000 /* Local base */
493 #define CONFIG_SYS_PCI_MSTR_MEMIO_BUS 0xA0000000 /* PCI base */
494 #define CONFIG_SYS_CPU_PCI_MEMIO_START PCI_MSTR_MEMIO_LOCAL
495 #define CONFIG_SYS_PCI_MSTR_MEMIO_SIZE 0x20000000 /* 512MB */
496 #define CONFIG_SYS_POCMR1_MASK_ATTRIB (POCMR_MASK_512MB | POCMR_ENABLE)
499 * Master window that allows the CPU to access PCI IO space.
500 * This window will be setup with the first set of Outbound ATU registers
504 #define CONFIG_SYS_PCI_MSTR_IO_LOCAL 0xF6000000 /* Local base */
505 #define CONFIG_SYS_PCI_MSTR_IO_BUS 0x00000000 /* PCI base */
506 #define CONFIG_SYS_CPU_PCI_IO_START PCI_MSTR_IO_LOCAL
507 #define CONFIG_SYS_PCI_MSTR_IO_SIZE 0x02000000 /* 64MB */
508 #define CONFIG_SYS_POCMR2_MASK_ATTRIB (POCMR_MASK_32MB | POCMR_ENABLE | POCMR_PCI_IO)
511 /* PCIBR0 - for PCI IO*/
512 #define CONFIG_SYS_PCI_MSTR0_LOCAL CONFIG_SYS_PCI_MSTR_IO_LOCAL /* Local base */
513 #define CONFIG_SYS_PCIMSK0_MASK ~(CONFIG_SYS_PCI_MSTR_IO_SIZE - 1U) /* Size of window */
514 /* PCIBR1 - prefetch and non-prefetch regions joined together */
515 #define CONFIG_SYS_PCI_MSTR1_LOCAL CONFIG_SYS_PCI_MSTR_MEM_LOCAL
516 #define CONFIG_SYS_PCIMSK1_MASK ~(CONFIG_SYS_PCI_MSTR_MEM_SIZE + CONFIG_SYS_PCI_MSTR_MEMIO_SIZE - 1U)
518 #endif /* CONFIG_ADSTYPE == CONFIG_8272ADS*/
520 #define CONFIG_HAS_ETH0
522 #if CONFIG_ADSTYPE == CONFIG_SYS_8272ADS
523 #define CONFIG_HAS_ETH1
526 #endif /* __CONFIG_H */