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[u-boot] / include / configs / MPC8308RDB.h
1 /* SPDX-License-Identifier: GPL-2.0+ */
2 /*
3  * Copyright (C) 2009-2010 Freescale Semiconductor, Inc.
4  * Copyright (C) 2010 Ilya Yanok, Emcraft Systems, yanok@emcraft.com
5  *
6  */
7
8 #ifndef __CONFIG_H
9 #define __CONFIG_H
10
11 /*
12  * High Level Configuration Options
13  */
14 #define CONFIG_E300             1 /* E300 family */
15 #define CONFIG_MPC830x          1 /* MPC830x family */
16 #define CONFIG_MPC8308          1 /* MPC8308 CPU specific */
17
18 #define CONFIG_MISC_INIT_R
19
20 #ifdef CONFIG_MMC
21 #define CONFIG_SYS_FSL_ESDHC_ADDR       CONFIG_SYS_MPC83xx_ESDHC_ADDR
22 #define CONFIG_SYS_FSL_ESDHC_USE_PIO
23 #endif
24
25 /*
26  * On-board devices
27  *
28  * TSEC1 is SoC TSEC
29  * TSEC2 is VSC switch
30  */
31 #define CONFIG_TSEC1
32 #define CONFIG_VSC7385_ENET
33
34 /*
35  * System Clock Setup
36  */
37 #define CONFIG_83XX_CLKIN       33333333 /* in Hz */
38 #define CONFIG_SYS_CLK_FREQ     CONFIG_83XX_CLKIN
39
40 /*
41  * Hardware Reset Configuration Word
42  * if CLKIN is 66.66MHz, then
43  * CSB = 133MHz, DDRC = 266MHz, LBC = 133MHz
44  * We choose the A type silicon as default, so the core is 400Mhz.
45  */
46 #define CONFIG_SYS_HRCW_LOW (\
47         HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
48         HRCWL_DDR_TO_SCB_CLK_2X1 |\
49         HRCWL_SVCOD_DIV_2 |\
50         HRCWL_CSB_TO_CLKIN_4X1 |\
51         HRCWL_CORE_TO_CSB_3X1)
52 /*
53  * There are neither HRCWH_PCI_HOST nor HRCWH_PCI1_ARBITER_ENABLE bits
54  * in 8308's HRCWH according to the manual, but original Freescale's
55  * code has them and I've expirienced some problems using the board
56  * with BDI3000 attached when I've tried to set these bits to zero
57  * (UART doesn't work after the 'reset run' command).
58  */
59 #define CONFIG_SYS_HRCW_HIGH (\
60         HRCWH_PCI_HOST |\
61         HRCWH_PCI1_ARBITER_ENABLE |\
62         HRCWH_CORE_ENABLE |\
63         HRCWH_FROM_0X00000100 |\
64         HRCWH_BOOTSEQ_DISABLE |\
65         HRCWH_SW_WATCHDOG_DISABLE |\
66         HRCWH_ROM_LOC_LOCAL_16BIT |\
67         HRCWH_RL_EXT_LEGACY |\
68         HRCWH_TSEC1M_IN_RGMII |\
69         HRCWH_TSEC2M_IN_RGMII |\
70         HRCWH_BIG_ENDIAN)
71
72 /*
73  * System IO Config
74  */
75 #define CONFIG_SYS_SICRH (\
76         SICRH_ESDHC_A_SD |\
77         SICRH_ESDHC_B_SD |\
78         SICRH_ESDHC_C_SD |\
79         SICRH_GPIO_A_TSEC2 |\
80         SICRH_GPIO_B_TSEC2_GTX_CLK125 |\
81         SICRH_IEEE1588_A_GPIO |\
82         SICRH_USB |\
83         SICRH_GTM_GPIO |\
84         SICRH_IEEE1588_B_GPIO |\
85         SICRH_ETSEC2_CRS |\
86         SICRH_GPIOSEL_1 |\
87         SICRH_TMROBI_V3P3 |\
88         SICRH_TSOBI1_V2P5 |\
89         SICRH_TSOBI2_V2P5)      /* 0x01b7d103 */
90 #define CONFIG_SYS_SICRL (\
91         SICRL_SPI_PF0 |\
92         SICRL_UART_PF0 |\
93         SICRL_IRQ_PF0 |\
94         SICRL_I2C2_PF0 |\
95         SICRL_ETSEC1_GTX_CLK125)        /* 0x00000040 */
96
97 /*
98  * IMMR new address
99  */
100 #define CONFIG_SYS_IMMR         0xE0000000
101
102 /*
103  * SERDES
104  */
105 #define CONFIG_FSL_SERDES
106 #define CONFIG_FSL_SERDES1      0xe3000
107
108 /*
109  * Arbiter Setup
110  */
111 #define CONFIG_SYS_ACR_PIPE_DEP 3 /* Arbiter pipeline depth is 4 */
112 #define CONFIG_SYS_ACR_RPTCNT   3 /* Arbiter repeat count is 4 */
113 #define CONFIG_SYS_SPCR_TSECEP  3 /* eTSEC emergency priority is highest */
114
115 /*
116  * DDR Setup
117  */
118 #define CONFIG_SYS_DDR_BASE             0x00000000 /* DDR is system memory */
119 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_BASE
120 #define CONFIG_SYS_DDR_SDRAM_BASE       CONFIG_SYS_DDR_BASE
121 #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL   DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05
122 #define CONFIG_SYS_DDRCDR_VALUE (DDRCDR_EN \
123                                 | DDRCDR_PZ_LOZ \
124                                 | DDRCDR_NZ_LOZ \
125                                 | DDRCDR_ODT \
126                                 | DDRCDR_Q_DRN)
127                                 /* 0x7b880001 */
128 /*
129  * Manually set up DDR parameters
130  * consist of two chips HY5PS12621BFP-C4 from HYNIX
131  */
132
133 #define CONFIG_SYS_DDR_SIZE             128 /* MB */
134
135 #define CONFIG_SYS_DDR_CS0_BNDS 0x00000007
136 #define CONFIG_SYS_DDR_CS0_CONFIG       (CSCONFIG_EN \
137                                 | CSCONFIG_ODT_RD_NEVER \
138                                 | CSCONFIG_ODT_WR_ONLY_CURRENT \
139                                 | CSCONFIG_ROW_BIT_13 | CSCONFIG_COL_BIT_10)
140                                 /* 0x80010102 */
141 #define CONFIG_SYS_DDR_TIMING_3 0x00000000
142 #define CONFIG_SYS_DDR_TIMING_0 ((0 << TIMING_CFG0_RWT_SHIFT) \
143                                 | (0 << TIMING_CFG0_WRT_SHIFT) \
144                                 | (0 << TIMING_CFG0_RRT_SHIFT) \
145                                 | (0 << TIMING_CFG0_WWT_SHIFT) \
146                                 | (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) \
147                                 | (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) \
148                                 | (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \
149                                 | (2 << TIMING_CFG0_MRS_CYC_SHIFT))
150                                 /* 0x00220802 */
151 #define CONFIG_SYS_DDR_TIMING_1 ((2 << TIMING_CFG1_PRETOACT_SHIFT) \
152                                 | (7 << TIMING_CFG1_ACTTOPRE_SHIFT) \
153                                 | (2 << TIMING_CFG1_ACTTORW_SHIFT) \
154                                 | (5 << TIMING_CFG1_CASLAT_SHIFT) \
155                                 | (6 << TIMING_CFG1_REFREC_SHIFT) \
156                                 | (2 << TIMING_CFG1_WRREC_SHIFT) \
157                                 | (2 << TIMING_CFG1_ACTTOACT_SHIFT) \
158                                 | (2 << TIMING_CFG1_WRTORD_SHIFT))
159                                 /* 0x27256222 */
160 #define CONFIG_SYS_DDR_TIMING_2 ((1 << TIMING_CFG2_ADD_LAT_SHIFT) \
161                                 | (4 << TIMING_CFG2_CPO_SHIFT) \
162                                 | (2 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) \
163                                 | (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) \
164                                 | (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) \
165                                 | (3 << TIMING_CFG2_CKE_PLS_SHIFT) \
166                                 | (5 << TIMING_CFG2_FOUR_ACT_SHIFT))
167                                 /* 0x121048c5 */
168 #define CONFIG_SYS_DDR_INTERVAL ((0x0360 << SDRAM_INTERVAL_REFINT_SHIFT) \
169                                 | (0x0100 << SDRAM_INTERVAL_BSTOPRE_SHIFT))
170                                 /* 0x03600100 */
171 #define CONFIG_SYS_DDR_SDRAM_CFG        (SDRAM_CFG_SREN \
172                                 | SDRAM_CFG_SDRAM_TYPE_DDR2 \
173                                 | SDRAM_CFG_DBW_32)
174                                 /* 0x43080000 */
175
176 #define CONFIG_SYS_DDR_SDRAM_CFG2       0x00401000 /* 1 posted refresh */
177 #define CONFIG_SYS_DDR_MODE             ((0x0448 << SDRAM_MODE_ESD_SHIFT) \
178                                 | (0x0232 << SDRAM_MODE_SD_SHIFT))
179                                 /* ODT 150ohm CL=3, AL=1 on SDRAM */
180 #define CONFIG_SYS_DDR_MODE2            0x00000000
181
182 /*
183  * Memory test
184  */
185 #define CONFIG_SYS_MEMTEST_START        0x00001000 /* memtest region */
186 #define CONFIG_SYS_MEMTEST_END          0x07f00000
187
188 /*
189  * The reserved memory
190  */
191 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
192
193 #define CONFIG_SYS_MONITOR_LEN  (512 * 1024) /* Reserve 512 kB for Mon */
194 #define CONFIG_SYS_MALLOC_LEN   (512 * 1024) /* Reserved for malloc */
195
196 /*
197  * Initial RAM Base Address Setup
198  */
199 #define CONFIG_SYS_INIT_RAM_LOCK        1
200 #define CONFIG_SYS_INIT_RAM_ADDR        0xE6000000 /* Initial RAM address */
201 #define CONFIG_SYS_INIT_RAM_SIZE        0x1000 /* Size of used area in RAM */
202 #define CONFIG_SYS_GBL_DATA_OFFSET      \
203         (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
204
205 /*
206  * Local Bus Configuration & Clock Setup
207  */
208 #define CONFIG_SYS_LCRR_DBYP            LCRR_DBYP
209 #define CONFIG_SYS_LCRR_CLKDIV          LCRR_CLKDIV_2
210 #define CONFIG_SYS_LBC_LBCR             0x00040000
211
212 /*
213  * FLASH on the Local Bus
214  */
215 #define CONFIG_SYS_FLASH_CFI            /* use the Common Flash Interface */
216 #define CONFIG_FLASH_CFI_DRIVER         /* use the CFI driver */
217 #define CONFIG_SYS_FLASH_CFI_WIDTH      FLASH_CFI_16BIT
218
219 #define CONFIG_SYS_FLASH_BASE           0xFE000000 /* FLASH base address */
220 #define CONFIG_SYS_FLASH_SIZE           8 /* FLASH size is 8M */
221 #define CONFIG_SYS_FLASH_PROTECTION     1 /* Use h/w Flash protection. */
222
223 /* Window base at flash base */
224 #define CONFIG_SYS_LBLAWBAR0_PRELIM     CONFIG_SYS_FLASH_BASE
225 #define CONFIG_SYS_LBLAWAR0_PRELIM      (LBLAWAR_EN | LBLAWAR_8MB)
226
227 #define CONFIG_SYS_BR0_PRELIM   (CONFIG_SYS_FLASH_BASE \
228                                 | BR_PS_16      /* 16 bit port */ \
229                                 | BR_MS_GPCM    /* MSEL = GPCM */ \
230                                 | BR_V)         /* valid */
231 #define CONFIG_SYS_OR0_PRELIM   (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \
232                                 | OR_UPM_XAM \
233                                 | OR_GPCM_CSNT \
234                                 | OR_GPCM_ACS_DIV2 \
235                                 | OR_GPCM_XACS \
236                                 | OR_GPCM_SCY_15 \
237                                 | OR_GPCM_TRLX_SET \
238                                 | OR_GPCM_EHTR_SET)
239
240 #define CONFIG_SYS_MAX_FLASH_BANKS      1 /* number of banks */
241 /* 127 64KB sectors and 8 8KB top sectors per device */
242 #define CONFIG_SYS_MAX_FLASH_SECT       135
243
244 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000 /* Flash Erase Timeout (ms) */
245 #define CONFIG_SYS_FLASH_WRITE_TOUT     500 /* Flash Write Timeout (ms) */
246
247 /*
248  * NAND Flash on the Local Bus
249  */
250 #define CONFIG_SYS_NAND_BASE    0xE0600000              /* 0xE0600000 */
251 #define CONFIG_SYS_NAND_WINDOW_SIZE     (32 * 1024)     /* 0x00008000 */
252 #define CONFIG_SYS_BR1_PRELIM   (CONFIG_SYS_NAND_BASE \
253                                 | BR_DECC_CHK_GEN       /* Use HW ECC */ \
254                                 | BR_PS_8               /* 8 bit Port */ \
255                                 | BR_MS_FCM             /* MSEL = FCM */ \
256                                 | BR_V)                 /* valid */
257 #define CONFIG_SYS_OR1_PRELIM   (P2SZ_TO_AM(CONFIG_SYS_NAND_WINDOW_SIZE) \
258                                 | OR_FCM_CSCT \
259                                 | OR_FCM_CST \
260                                 | OR_FCM_CHT \
261                                 | OR_FCM_SCY_1 \
262                                 | OR_FCM_TRLX \
263                                 | OR_FCM_EHTR)
264                                 /* 0xFFFF8396 */
265
266 #define CONFIG_SYS_LBLAWBAR1_PRELIM     CONFIG_SYS_NAND_BASE
267 #define CONFIG_SYS_LBLAWAR1_PRELIM      (LBLAWAR_EN | LBLAWAR_32KB)
268
269 #ifdef CONFIG_VSC7385_ENET
270 #define CONFIG_TSEC2
271                                         /* VSC7385 Base address on CS2 */
272 #define CONFIG_SYS_VSC7385_BASE         0xF0000000
273 #define CONFIG_SYS_VSC7385_SIZE         (128 * 1024) /* 0x00020000 */
274 #define CONFIG_SYS_BR2_PRELIM           (CONFIG_SYS_VSC7385_BASE \
275                                         | BR_PS_8       /* 8-bit port */ \
276                                         | BR_MS_GPCM    /* MSEL = GPCM */ \
277                                         | BR_V)         /* valid */
278                                         /* 0xF0000801 */
279 #define CONFIG_SYS_OR2_PRELIM           (P2SZ_TO_AM(CONFIG_SYS_VSC7385_SIZE) \
280                                         | OR_GPCM_CSNT \
281                                         | OR_GPCM_XACS \
282                                         | OR_GPCM_SCY_15 \
283                                         | OR_GPCM_SETA \
284                                         | OR_GPCM_TRLX_SET \
285                                         | OR_GPCM_EHTR_SET)
286                                         /* 0xFFFE09FF */
287 /* Access window base at VSC7385 base */
288 #define CONFIG_SYS_LBLAWBAR2_PRELIM     CONFIG_SYS_VSC7385_BASE
289 /* Access window size 128K */
290 #define CONFIG_SYS_LBLAWAR2_PRELIM      (LBLAWAR_EN | LBLAWAR_128KB)
291 /* The flash address and size of the VSC7385 firmware image */
292 #define CONFIG_VSC7385_IMAGE            0xFE7FE000
293 #define CONFIG_VSC7385_IMAGE_SIZE       8192
294 #endif
295 /*
296  * Serial Port
297  */
298 #define CONFIG_SYS_NS16550_SERIAL
299 #define CONFIG_SYS_NS16550_REG_SIZE     1
300 #define CONFIG_SYS_NS16550_CLK          get_bus_freq(0)
301
302 #define CONFIG_SYS_BAUDRATE_TABLE  \
303         {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
304
305 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x4500)
306 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x4600)
307
308 /* I2C */
309 #define CONFIG_SYS_I2C
310 #define CONFIG_SYS_I2C_FSL
311 #define CONFIG_SYS_FSL_I2C_SPEED        400000
312 #define CONFIG_SYS_FSL_I2C_SLAVE        0x7F
313 #define CONFIG_SYS_FSL_I2C_OFFSET       0x3000
314 #define CONFIG_SYS_FSL_I2C2_SPEED       400000
315 #define CONFIG_SYS_FSL_I2C2_SLAVE       0x7F
316 #define CONFIG_SYS_FSL_I2C2_OFFSET      0x3100
317 #define CONFIG_SYS_I2C_NOPROBES         { {0, 0x51} }
318
319 /*
320  * SPI on header J8
321  *
322  * WARNING: enabling this will break TSEC2 (connected to the Vitesse switch)
323  * due to a pinmux conflict between GPIO9 (SPI chip select )and the TSEC2 pins.
324  */
325 #ifdef CONFIG_MPC8XXX_SPI
326 #define CONFIG_USE_SPIFLASH
327 #endif
328
329 /*
330  * Board info - revision and where boot from
331  */
332 #define CONFIG_SYS_I2C_PCF8574A_ADDR    0x39
333
334 /*
335  * Config on-board RTC
336  */
337 #define CONFIG_RTC_DS1337       /* ds1339 on board, use ds1337 rtc via i2c */
338 #define CONFIG_SYS_I2C_RTC_ADDR 0x68 /* at address 0x68 */
339
340 /*
341  * General PCI
342  * Addresses are mapped 1-1.
343  */
344 #define CONFIG_SYS_PCIE1_BASE           0xA0000000
345 #define CONFIG_SYS_PCIE1_MEM_BASE       0xA0000000
346 #define CONFIG_SYS_PCIE1_MEM_PHYS       0xA0000000
347 #define CONFIG_SYS_PCIE1_MEM_SIZE       0x10000000
348 #define CONFIG_SYS_PCIE1_CFG_BASE       0xB0000000
349 #define CONFIG_SYS_PCIE1_CFG_SIZE       0x01000000
350 #define CONFIG_SYS_PCIE1_IO_BASE        0x00000000
351 #define CONFIG_SYS_PCIE1_IO_PHYS        0xB1000000
352 #define CONFIG_SYS_PCIE1_IO_SIZE        0x00800000
353
354 /* enable PCIE clock */
355 #define CONFIG_SYS_SCCR_PCIEXP1CM       1
356
357 #define CONFIG_PCI_INDIRECT_BRIDGE
358 #define CONFIG_PCIE
359
360 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957   /* Freescale */
361 #define CONFIG_83XX_GENERIC_PCIE_REGISTER_HOSES 1
362
363 /*
364  * TSEC
365  */
366 #define CONFIG_SYS_TSEC1_OFFSET 0x24000
367 #define CONFIG_SYS_TSEC1        (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC1_OFFSET)
368 #define CONFIG_SYS_TSEC2_OFFSET 0x25000
369 #define CONFIG_SYS_TSEC2        (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC2_OFFSET)
370
371 /*
372  * TSEC ethernet configuration
373  */
374 #define CONFIG_MII              1 /* MII PHY management */
375 #define CONFIG_TSEC1_NAME       "eTSEC0"
376 #define CONFIG_TSEC2_NAME       "eTSEC1"
377 #define TSEC1_PHY_ADDR          2
378 #define TSEC2_PHY_ADDR          1
379 #define TSEC1_PHYIDX            0
380 #define TSEC2_PHYIDX            0
381 #define TSEC1_FLAGS             TSEC_GIGABIT
382 #define TSEC2_FLAGS             TSEC_GIGABIT
383
384 /* Options are: eTSEC[0-1] */
385 #define CONFIG_ETHPRIME         "eTSEC0"
386
387 /*
388  * Environment
389  */
390 #define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE + \
391                                  CONFIG_SYS_MONITOR_LEN)
392 #define CONFIG_ENV_SECT_SIZE    0x10000 /* 64K(one sector) for env */
393 #define CONFIG_ENV_SIZE         0x2000
394 #define CONFIG_ENV_ADDR_REDUND  (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE)
395 #define CONFIG_ENV_SIZE_REDUND  CONFIG_ENV_SIZE
396
397 #define CONFIG_LOADS_ECHO       1       /* echo on for serial download */
398 #define CONFIG_SYS_LOADS_BAUD_CHANGE    1       /* allow baudrate change */
399
400 /*
401  * BOOTP options
402  */
403 #define CONFIG_BOOTP_BOOTFILESIZE
404
405 /*
406  * Command line configuration.
407  */
408
409 /*
410  * Miscellaneous configurable options
411  */
412 #define CONFIG_SYS_LOAD_ADDR            0x2000000 /* default load address */
413
414 #define CONFIG_SYS_CBSIZE       1024 /* Console I/O Buffer Size */
415
416 /* Boot Argument Buffer Size */
417 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE
418
419 /*
420  * For booting Linux, the board info and command line data
421  * have to be in the first 256 MB of memory, since this is
422  * the maximum mapped by the Linux kernel during initialization.
423  */
424 #define CONFIG_SYS_BOOTMAPSZ    (256 << 20) /* Initial Memory map for Linux */
425 #define CONFIG_SYS_BOOTM_LEN    (64 << 20)      /* Increase max gunzip size */
426
427 /*
428  * Core HID Setup
429  */
430 #define CONFIG_SYS_HID0_INIT    0x000000000
431 #define CONFIG_SYS_HID0_FINAL   (HID0_ENABLE_MACHINE_CHECK | \
432                                  HID0_ENABLE_INSTRUCTION_CACHE | \
433                                  HID0_ENABLE_DYNAMIC_POWER_MANAGMENT)
434 #define CONFIG_SYS_HID2         HID2_HBE
435
436 /*
437  * MMU Setup
438  */
439
440 /* DDR: cache cacheable */
441 #define CONFIG_SYS_IBAT0L       (CONFIG_SYS_SDRAM_BASE | BATL_PP_RW | \
442                                         BATL_MEMCOHERENCE)
443 #define CONFIG_SYS_IBAT0U       (CONFIG_SYS_SDRAM_BASE | BATU_BL_128M | \
444                                         BATU_VS | BATU_VP)
445 #define CONFIG_SYS_DBAT0L       CONFIG_SYS_IBAT0L
446 #define CONFIG_SYS_DBAT0U       CONFIG_SYS_IBAT0U
447
448 /* IMMRBAR, PCI IO and NAND: cache-inhibit and guarded */
449 #define CONFIG_SYS_IBAT1L       (CONFIG_SYS_IMMR | BATL_PP_RW | \
450                         BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
451 #define CONFIG_SYS_IBAT1U       (CONFIG_SYS_IMMR | BATU_BL_8M | BATU_VS | \
452                                         BATU_VP)
453 #define CONFIG_SYS_DBAT1L       CONFIG_SYS_IBAT1L
454 #define CONFIG_SYS_DBAT1U       CONFIG_SYS_IBAT1U
455
456 /* FLASH: icache cacheable, but dcache-inhibit and guarded */
457 #define CONFIG_SYS_IBAT2L       (CONFIG_SYS_FLASH_BASE | BATL_PP_RW | \
458                                         BATL_MEMCOHERENCE)
459 #define CONFIG_SYS_IBAT2U       (CONFIG_SYS_FLASH_BASE | BATU_BL_8M | \
460                                         BATU_VS | BATU_VP)
461 #define CONFIG_SYS_DBAT2L       (CONFIG_SYS_FLASH_BASE | BATL_PP_RW | \
462                                         BATL_CACHEINHIBIT | \
463                                         BATL_GUARDEDSTORAGE)
464 #define CONFIG_SYS_DBAT2U       CONFIG_SYS_IBAT2U
465
466 /* Stack in dcache: cacheable, no memory coherence */
467 #define CONFIG_SYS_IBAT3L       (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW)
468 #define CONFIG_SYS_IBAT3U       (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | \
469                                         BATU_VS | BATU_VP)
470 #define CONFIG_SYS_DBAT3L       CONFIG_SYS_IBAT3L
471 #define CONFIG_SYS_DBAT3U       CONFIG_SYS_IBAT3U
472
473 /*
474  * Environment Configuration
475  */
476
477 #define CONFIG_ENV_OVERWRITE
478
479 #if defined(CONFIG_TSEC_ENET)
480 #define CONFIG_HAS_ETH0
481 #define CONFIG_HAS_ETH1
482 #endif
483
484 #define CONFIG_LOADADDR 800000  /* default location for tftp and bootm */
485
486
487 #define CONFIG_EXTRA_ENV_SETTINGS                                       \
488         "netdev=eth0\0"                                                 \
489         "consoledev=ttyS0\0"                                            \
490         "nfsargs=setenv bootargs root=/dev/nfs rw "                     \
491                 "nfsroot=${serverip}:${rootpath}\0"                     \
492         "ramargs=setenv bootargs root=/dev/ram rw\0"                    \
493         "addip=setenv bootargs ${bootargs} "                            \
494                 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"      \
495                 ":${hostname}:${netdev}:off panic=1\0"                  \
496         "addtty=setenv bootargs ${bootargs}"                            \
497                 " console=${consoledev},${baudrate}\0"                  \
498         "addmtd=setenv bootargs ${bootargs} ${mtdparts}\0"              \
499         "addmisc=setenv bootargs ${bootargs}\0"                         \
500         "kernel_addr=FE080000\0"                                        \
501         "fdt_addr=FE280000\0"                                           \
502         "ramdisk_addr=FE290000\0"                                       \
503         "u-boot=mpc8308rdb/u-boot.bin\0"                                \
504         "kernel_addr_r=1000000\0"                                       \
505         "fdt_addr_r=C00000\0"                                           \
506         "hostname=mpc8308rdb\0"                                         \
507         "bootfile=mpc8308rdb/uImage\0"                                  \
508         "fdtfile=mpc8308rdb/mpc8308rdb.dtb\0"                           \
509         "rootpath=/opt/eldk-4.2/ppc_6xx\0"                              \
510         "flash_self=run ramargs addip addtty addmtd addmisc;"           \
511                 "bootm ${kernel_addr} ${ramdisk_addr} ${fdt_addr}\0"    \
512         "flash_nfs=run nfsargs addip addtty addmtd addmisc;"            \
513                 "bootm ${kernel_addr} - ${fdt_addr}\0"                  \
514         "net_nfs=tftp ${kernel_addr_r} ${bootfile};"                    \
515                 "tftp ${fdt_addr_r} ${fdtfile};"                        \
516                 "run nfsargs addip addtty addmtd addmisc;"              \
517                 "bootm ${kernel_addr_r} - ${fdt_addr_r}\0"              \
518         "bootcmd=run flash_self\0"                                      \
519         "load=tftp ${loadaddr} ${u-boot}\0"                             \
520         "update=protect off " __stringify(CONFIG_SYS_MONITOR_BASE)      \
521                 " +${filesize};era " __stringify(CONFIG_SYS_MONITOR_BASE)\
522                 " +${filesize};cp.b ${fileaddr} "                       \
523                 __stringify(CONFIG_SYS_MONITOR_BASE) " ${filesize}\0"   \
524         "upd=run load update\0"                                         \
525
526 #endif  /* __CONFIG_H */