2 * Copyright (C) Freescale Semiconductor, Inc. 2006, 2010.
4 * SPDX-License-Identifier: GPL-2.0+
7 * mpc8313epb board configuration file
14 * High Level Configuration Options
17 #define CONFIG_MPC831x 1
18 #define CONFIG_MPC8313 1
19 #define CONFIG_MPC8313ERDB 1
22 #define CONFIG_SPL_INIT_MINIMAL
23 #define CONFIG_SPL_FLUSH_IMAGE
24 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
25 #define CONFIG_SPL_MPC83XX_WAIT_FOR_NAND
27 #ifdef CONFIG_SPL_BUILD
28 #define CONFIG_NS16550_MIN_FUNCTIONS
31 #define CONFIG_SYS_TEXT_BASE_SPL 0xfff00000
32 #define CONFIG_SPL_MAX_SIZE (4 * 1024)
33 #define CONFIG_SPL_PAD_TO 0x4000
35 #define CONFIG_SYS_NAND_U_BOOT_SIZE (512 << 10)
36 #define CONFIG_SYS_NAND_U_BOOT_DST 0x00100000
37 #define CONFIG_SYS_NAND_U_BOOT_START 0x00100100
38 #define CONFIG_SYS_NAND_U_BOOT_OFFS 16384
39 #define CONFIG_SYS_NAND_U_BOOT_RELOC 0x00010000
40 #define CONFIG_SYS_NAND_U_BOOT_RELOC_SP (CONFIG_SYS_NAND_U_BOOT_RELOC + 0x10000)
42 #ifdef CONFIG_SPL_BUILD
43 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE_SPL /* start of monitor */
46 #endif /* CONFIG_NAND */
48 #ifndef CONFIG_SYS_MONITOR_BASE
49 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
52 #define CONFIG_PCI_INDIRECT_BRIDGE
53 #define CONFIG_FSL_ELBC 1
55 #define CONFIG_MISC_INIT_R
63 #define CONFIG_VSC7385_ENET
66 #ifdef CONFIG_SYS_66MHZ
67 #define CONFIG_83XX_CLKIN 66666667 /* in Hz */
68 #elif defined(CONFIG_SYS_33MHZ)
69 #define CONFIG_83XX_CLKIN 33333333 /* in Hz */
71 #error Unknown oscillator frequency.
74 #define CONFIG_SYS_CLK_FREQ CONFIG_83XX_CLKIN
76 #define CONFIG_SYS_IMMR 0xE0000000
78 #if defined(CONFIG_NAND) && !defined(CONFIG_SPL_BUILD)
79 #define CONFIG_DEFAULT_IMMR CONFIG_SYS_IMMR
82 #define CONFIG_SYS_MEMTEST_START 0x00001000
83 #define CONFIG_SYS_MEMTEST_END 0x07f00000
85 /* Early revs of this board will lock up hard when attempting
86 * to access the PMC registers, unless a JTAG debugger is
87 * connected, or some resistor modifications are made.
89 #define CONFIG_SYS_8313ERDB_BROKEN_PMC 1
91 #define CONFIG_SYS_ACR_PIPE_DEP 3 /* Arbiter pipeline depth (0-3) */
92 #define CONFIG_SYS_ACR_RPTCNT 3 /* Arbiter repeat count (0-7) */
95 * Device configurations
100 #ifdef CONFIG_VSC7385_ENET
104 /* The flash address and size of the VSC7385 firmware image */
105 #define CONFIG_VSC7385_IMAGE 0xFE7FE000
106 #define CONFIG_VSC7385_IMAGE_SIZE 8192
113 #define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory*/
114 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE
115 #define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE
118 * Manually set up DDR parameters, as this board does not
119 * seem to have the SPD connected to I2C.
121 #define CONFIG_SYS_DDR_SIZE 128 /* MB */
122 #define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN \
123 | CSCONFIG_ODT_RD_NEVER \
124 | CSCONFIG_ODT_WR_ONLY_CURRENT \
125 | CSCONFIG_ROW_BIT_13 \
126 | CSCONFIG_COL_BIT_10)
129 #define CONFIG_SYS_DDR_TIMING_3 0x00000000
130 #define CONFIG_SYS_DDR_TIMING_0 ((0 << TIMING_CFG0_RWT_SHIFT) \
131 | (0 << TIMING_CFG0_WRT_SHIFT) \
132 | (0 << TIMING_CFG0_RRT_SHIFT) \
133 | (0 << TIMING_CFG0_WWT_SHIFT) \
134 | (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) \
135 | (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) \
136 | (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \
137 | (2 << TIMING_CFG0_MRS_CYC_SHIFT))
139 #define CONFIG_SYS_DDR_TIMING_1 ((3 << TIMING_CFG1_PRETOACT_SHIFT) \
140 | (8 << TIMING_CFG1_ACTTOPRE_SHIFT) \
141 | (3 << TIMING_CFG1_ACTTORW_SHIFT) \
142 | (5 << TIMING_CFG1_CASLAT_SHIFT) \
143 | (10 << TIMING_CFG1_REFREC_SHIFT) \
144 | (3 << TIMING_CFG1_WRREC_SHIFT) \
145 | (2 << TIMING_CFG1_ACTTOACT_SHIFT) \
146 | (2 << TIMING_CFG1_WRTORD_SHIFT))
148 #define CONFIG_SYS_DDR_TIMING_2 ((1 << TIMING_CFG2_ADD_LAT_SHIFT) \
149 | (5 << TIMING_CFG2_CPO_SHIFT) \
150 | (2 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) \
151 | (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) \
152 | (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) \
153 | (3 << TIMING_CFG2_CKE_PLS_SHIFT) \
154 | (6 << TIMING_CFG2_FOUR_ACT_SHIFT))
155 /* 0x129048c6 */ /* P9-45,may need tuning */
156 #define CONFIG_SYS_DDR_INTERVAL ((1296 << SDRAM_INTERVAL_REFINT_SHIFT) \
157 | (1280 << SDRAM_INTERVAL_BSTOPRE_SHIFT))
159 #if defined(CONFIG_DDR_2T_TIMING)
160 #define CONFIG_SYS_SDRAM_CFG (SDRAM_CFG_SREN \
161 | SDRAM_CFG_SDRAM_TYPE_DDR2 \
166 #define CONFIG_SYS_SDRAM_CFG (SDRAM_CFG_SREN \
167 | SDRAM_CFG_SDRAM_TYPE_DDR2 \
171 #define CONFIG_SYS_SDRAM_CFG2 0x00401000
172 /* set burst length to 8 for 32-bit data path */
173 #define CONFIG_SYS_DDR_MODE ((0x4448 << SDRAM_MODE_ESD_SHIFT) \
174 | (0x0632 << SDRAM_MODE_SD_SHIFT))
176 #define CONFIG_SYS_DDR_MODE_2 0x8000C000
178 #define CONFIG_SYS_DDR_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05
180 #define CONFIG_SYS_DDRCDR_VALUE (DDRCDR_EN \
186 * FLASH on the Local Bus
188 #define CONFIG_SYS_FLASH_CFI /* use the Common Flash Interface */
189 #define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */
190 #define CONFIG_SYS_FLASH_BASE 0xFE000000 /* start of FLASH */
191 #define CONFIG_SYS_FLASH_SIZE 8 /* flash size in MB */
192 #define CONFIG_SYS_FLASH_PROTECTION 1 /* Use h/w Flash protection. */
193 #define CONFIG_SYS_FLASH_EMPTY_INFO /* display empty sectors */
194 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE /* buffer up multiple bytes */
196 #define CONFIG_SYS_NOR_BR_PRELIM (CONFIG_SYS_FLASH_BASE \
197 | BR_PS_16 /* 16 bit port */ \
198 | BR_MS_GPCM /* MSEL = GPCM */ \
200 #define CONFIG_SYS_NOR_OR_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \
205 /* 0xFF006FF7 TODO SLOW 16 MB flash size */
206 /* window base at flash base */
207 #define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE
208 /* 16 MB window size */
209 #define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_16MB)
211 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
212 #define CONFIG_SYS_MAX_FLASH_SECT 135 /* sectors per device */
214 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
215 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
217 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) && \
218 !defined(CONFIG_SPL_BUILD)
219 #define CONFIG_SYS_RAMBOOT
222 #define CONFIG_SYS_INIT_RAM_LOCK 1
223 #define CONFIG_SYS_INIT_RAM_ADDR 0xFD000000 /* Initial RAM addr */
224 #define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM*/
226 #define CONFIG_SYS_GBL_DATA_OFFSET \
227 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
228 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
230 /* CONFIG_SYS_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */
231 #define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 kB for Mon */
232 #define CONFIG_SYS_MALLOC_LEN (512 * 1024) /* Reserved for malloc */
235 * Local Bus LCRR and LBCR regs
237 #define CONFIG_SYS_LCRR_EADC LCRR_EADC_1
238 #define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_4
239 #define CONFIG_SYS_LBC_LBCR (0x00040000 /* TODO */ \
240 | (0xFF << LBCR_BMT_SHIFT) \
241 | 0xF) /* 0x0004ff0f */
243 /* LB refresh timer prescal, 266MHz/32 */
244 #define CONFIG_SYS_LBC_MRTPR 0x20000000 /*TODO */
246 /* drivers/mtd/nand/nand.c */
247 #if defined(CONFIG_NAND) && defined(CONFIG_SPL_BUILD)
248 #define CONFIG_SYS_NAND_BASE 0xFFF00000
250 #define CONFIG_SYS_NAND_BASE 0xE2800000
253 #define CONFIG_MTD_DEVICE
254 #define CONFIG_MTD_PARTITION
256 #define CONFIG_SYS_MAX_NAND_DEVICE 1
257 #define CONFIG_NAND_FSL_ELBC 1
258 #define CONFIG_SYS_NAND_BLOCK_SIZE 16384
259 #define CONFIG_SYS_NAND_WINDOW_SIZE (32 * 1024)
261 #define CONFIG_SYS_NAND_BR_PRELIM (CONFIG_SYS_NAND_BASE \
262 | BR_DECC_CHK_GEN /* Use HW ECC */ \
263 | BR_PS_8 /* 8 bit port */ \
264 | BR_MS_FCM /* MSEL = FCM */ \
266 #define CONFIG_SYS_NAND_OR_PRELIM \
267 (P2SZ_TO_AM(CONFIG_SYS_NAND_WINDOW_SIZE) \
277 #define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NAND_BR_PRELIM
278 #define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_NAND_OR_PRELIM
279 #define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_NOR_BR_PRELIM
280 #define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_NOR_OR_PRELIM
282 #define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NOR_BR_PRELIM
283 #define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_NOR_OR_PRELIM
284 #define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_NAND_BR_PRELIM
285 #define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_NAND_OR_PRELIM
288 #define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_NAND_BASE
289 #define CONFIG_SYS_LBLAWAR1_PRELIM (LBLAWAR_EN | LBLAWAR_32KB)
291 #define CONFIG_SYS_NAND_LBLAWBAR_PRELIM CONFIG_SYS_LBLAWBAR1_PRELIM
292 #define CONFIG_SYS_NAND_LBLAWAR_PRELIM CONFIG_SYS_LBLAWAR1_PRELIM
294 /* local bus write LED / read status buffer (BCSR) mapping */
295 #define CONFIG_SYS_BCSR_ADDR 0xFA000000
296 #define CONFIG_SYS_BCSR_SIZE (32 * 1024) /* 0x00008000 */
297 /* map at 0xFA000000 on LCS3 */
298 #define CONFIG_SYS_BR3_PRELIM (CONFIG_SYS_BCSR_ADDR \
299 | BR_PS_8 /* 8 bit port */ \
300 | BR_MS_GPCM /* MSEL = GPCM */ \
303 #define CONFIG_SYS_OR3_PRELIM (P2SZ_TO_AM(CONFIG_SYS_BCSR_SIZE) \
312 #define CONFIG_SYS_LBLAWBAR3_PRELIM CONFIG_SYS_BCSR_ADDR
313 #define CONFIG_SYS_LBLAWAR3_PRELIM (LBLAWAR_EN | LBLAWAR_32KB)
317 #ifdef CONFIG_VSC7385_ENET
319 /* VSC7385 Base address on LCS2 */
320 #define CONFIG_SYS_VSC7385_BASE 0xF0000000
321 #define CONFIG_SYS_VSC7385_SIZE (128 * 1024) /* 0x00020000 */
323 #define CONFIG_SYS_BR2_PRELIM (CONFIG_SYS_VSC7385_BASE \
324 | BR_PS_8 /* 8 bit port */ \
325 | BR_MS_GPCM /* MSEL = GPCM */ \
327 #define CONFIG_SYS_OR2_PRELIM (P2SZ_TO_AM(CONFIG_SYS_VSC7385_SIZE) \
337 /* Access window base at VSC7385 base */
338 #define CONFIG_SYS_LBLAWBAR2_PRELIM CONFIG_SYS_VSC7385_BASE
339 #define CONFIG_SYS_LBLAWAR2_PRELIM (LBLAWAR_EN | LBLAWAR_128KB)
343 #define CONFIG_MPC83XX_GPIO 1
348 #define CONFIG_SYS_NS16550_SERIAL
349 #define CONFIG_SYS_NS16550_REG_SIZE 1
351 #define CONFIG_SYS_BAUDRATE_TABLE \
352 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
354 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500)
355 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600)
358 #define CONFIG_SYS_I2C
359 #define CONFIG_SYS_I2C_FSL
360 #define CONFIG_SYS_FSL_I2C_SPEED 400000
361 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
362 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
363 #define CONFIG_SYS_FSL_I2C2_SPEED 400000
364 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
365 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
366 #define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} }
370 * Addresses are mapped 1-1.
372 #define CONFIG_SYS_PCI1_MEM_BASE 0x80000000
373 #define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE
374 #define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000 /* 256M */
375 #define CONFIG_SYS_PCI1_MMIO_BASE 0x90000000
376 #define CONFIG_SYS_PCI1_MMIO_PHYS CONFIG_SYS_PCI1_MMIO_BASE
377 #define CONFIG_SYS_PCI1_MMIO_SIZE 0x10000000 /* 256M */
378 #define CONFIG_SYS_PCI1_IO_BASE 0x00000000
379 #define CONFIG_SYS_PCI1_IO_PHYS 0xE2000000
380 #define CONFIG_SYS_PCI1_IO_SIZE 0x00100000 /* 1M */
382 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */
388 #define CONFIG_GMII /* MII PHY management */
391 #define CONFIG_HAS_ETH0
392 #define CONFIG_TSEC1_NAME "TSEC0"
393 #define CONFIG_SYS_TSEC1_OFFSET 0x24000
394 #define TSEC1_PHY_ADDR 0x1c
395 #define TSEC1_FLAGS TSEC_GIGABIT
396 #define TSEC1_PHYIDX 0
400 #define CONFIG_HAS_ETH1
401 #define CONFIG_TSEC2_NAME "TSEC1"
402 #define CONFIG_SYS_TSEC2_OFFSET 0x25000
403 #define TSEC2_PHY_ADDR 4
404 #define TSEC2_FLAGS TSEC_GIGABIT
405 #define TSEC2_PHYIDX 0
408 /* Options are: TSEC[0-1] */
409 #define CONFIG_ETHPRIME "TSEC1"
412 * Configure on-board RTC
414 #define CONFIG_RTC_DS1337
415 #define CONFIG_SYS_I2C_RTC_ADDR 0x68
420 #if defined(CONFIG_NAND)
421 #define CONFIG_ENV_OFFSET (512 * 1024)
422 #define CONFIG_ENV_SECT_SIZE CONFIG_SYS_NAND_BLOCK_SIZE
423 #define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE
424 #define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE
425 #define CONFIG_ENV_RANGE (CONFIG_ENV_SECT_SIZE * 4)
426 #define CONFIG_ENV_OFFSET_REDUND \
427 (CONFIG_ENV_OFFSET + CONFIG_ENV_RANGE)
428 #elif !defined(CONFIG_SYS_RAMBOOT)
429 #define CONFIG_ENV_ADDR \
430 (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
431 #define CONFIG_ENV_SECT_SIZE 0x10000 /* 64K(one sector) for env */
432 #define CONFIG_ENV_SIZE 0x2000
434 /* Address and size of Redundant Environment Sector */
436 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
437 #define CONFIG_ENV_SIZE 0x2000
440 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
441 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
446 #define CONFIG_BOOTP_BOOTFILESIZE
449 * Command line configuration.
453 * Miscellaneous configurable options
455 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
456 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
458 /* Boot Argument Buffer Size */
459 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
462 * For booting Linux, the board info and command line data
463 * have to be in the first 256 MB of memory, since this is
464 * the maximum mapped by the Linux kernel during initialization.
466 /* Initial Memory map for Linux*/
467 #define CONFIG_SYS_BOOTMAPSZ (256 << 20)
468 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
470 #define CONFIG_SYS_RCWH_PCIHOST 0x80000000 /* PCIHOST */
472 #ifdef CONFIG_SYS_66MHZ
474 /* 66MHz IN, 133MHz CSB, 266 DDR, 266 CORE */
476 #define CONFIG_SYS_HRCW_LOW (\
477 0x20000000 /* reserved, must be set */ |\
479 HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
480 HRCWL_DDR_TO_SCB_CLK_2X1 |\
481 HRCWL_CSB_TO_CLKIN_2X1 |\
482 HRCWL_CORE_TO_CSB_2X1)
484 #define CONFIG_SYS_NS16550_CLK (CONFIG_83XX_CLKIN * 2)
486 #elif defined(CONFIG_SYS_33MHZ)
488 /* 33MHz IN, 165MHz CSB, 330 DDR, 330 CORE */
490 #define CONFIG_SYS_HRCW_LOW (\
491 0x20000000 /* reserved, must be set */ |\
493 HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
494 HRCWL_DDR_TO_SCB_CLK_2X1 |\
495 HRCWL_CSB_TO_CLKIN_5X1 |\
496 HRCWL_CORE_TO_CSB_2X1)
498 #define CONFIG_SYS_NS16550_CLK (CONFIG_83XX_CLKIN * 5)
502 #define CONFIG_SYS_HRCW_HIGH_BASE (\
504 HRCWH_PCI1_ARBITER_ENABLE |\
506 HRCWH_BOOTSEQ_DISABLE |\
507 HRCWH_SW_WATCHDOG_DISABLE |\
508 HRCWH_TSEC1M_IN_RGMII |\
509 HRCWH_TSEC2M_IN_RGMII |\
513 #define CONFIG_SYS_HRCW_HIGH (CONFIG_SYS_HRCW_HIGH_BASE |\
514 HRCWH_FROM_0XFFF00100 |\
515 HRCWH_ROM_LOC_NAND_SP_8BIT |\
518 #define CONFIG_SYS_HRCW_HIGH (CONFIG_SYS_HRCW_HIGH_BASE |\
519 HRCWH_FROM_0X00000100 |\
520 HRCWH_ROM_LOC_LOCAL_16BIT |\
524 /* System IO Config */
525 #define CONFIG_SYS_SICRH (SICRH_TSOBI1 | SICRH_TSOBI2) /* RGMII */
526 /* Enable Internal USB Phy and GPIO on LCD Connector */
527 #define CONFIG_SYS_SICRL (SICRL_USBDR_10 | SICRL_LBC)
529 #define CONFIG_SYS_HID0_INIT 0x000000000
530 #define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | \
531 HID0_ENABLE_INSTRUCTION_CACHE | \
532 HID0_ENABLE_DYNAMIC_POWER_MANAGMENT)
534 #define CONFIG_SYS_HID2 HID2_HBE
536 #define CONFIG_HIGH_BATS 1 /* High BATs supported */
538 /* DDR @ 0x00000000 */
539 #define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_RW)
540 #define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE \
545 /* PCI @ 0x80000000 */
546 #define CONFIG_SYS_IBAT1L (CONFIG_SYS_PCI1_MEM_BASE | BATL_PP_RW)
547 #define CONFIG_SYS_IBAT1U (CONFIG_SYS_PCI1_MEM_BASE \
551 #define CONFIG_SYS_IBAT2L (CONFIG_SYS_PCI1_MMIO_BASE \
553 | BATL_CACHEINHIBIT \
554 | BATL_GUARDEDSTORAGE)
555 #define CONFIG_SYS_IBAT2U (CONFIG_SYS_PCI1_MMIO_BASE \
560 /* PCI2 not supported on 8313 */
561 #define CONFIG_SYS_IBAT3L (0)
562 #define CONFIG_SYS_IBAT3U (0)
563 #define CONFIG_SYS_IBAT4L (0)
564 #define CONFIG_SYS_IBAT4U (0)
566 /* IMMRBAR @ 0xE0000000, PCI IO @ 0xE2000000 & BCSR @ 0xE2400000 */
567 #define CONFIG_SYS_IBAT5L (CONFIG_SYS_IMMR \
569 | BATL_CACHEINHIBIT \
570 | BATL_GUARDEDSTORAGE)
571 #define CONFIG_SYS_IBAT5U (CONFIG_SYS_IMMR \
576 /* SDRAM @ 0xF0000000, stack in DCACHE 0xFDF00000 & FLASH @ 0xFE000000 */
577 #define CONFIG_SYS_IBAT6L (0xF0000000 | BATL_PP_RW | BATL_GUARDEDSTORAGE)
578 #define CONFIG_SYS_IBAT6U (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP)
580 #define CONFIG_SYS_IBAT7L (0)
581 #define CONFIG_SYS_IBAT7U (0)
583 #define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L
584 #define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U
585 #define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L
586 #define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U
587 #define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L
588 #define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U
589 #define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L
590 #define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U
591 #define CONFIG_SYS_DBAT4L CONFIG_SYS_IBAT4L
592 #define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U
593 #define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L
594 #define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U
595 #define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L
596 #define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U
597 #define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L
598 #define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U
601 * Environment Configuration
603 #define CONFIG_ENV_OVERWRITE
605 #define CONFIG_NETDEV "eth1"
607 #define CONFIG_HOSTNAME "mpc8313erdb"
608 #define CONFIG_ROOTPATH "/nfs/root/path"
609 #define CONFIG_BOOTFILE "uImage"
610 /* U-Boot image on TFTP server */
611 #define CONFIG_UBOOTPATH "u-boot.bin"
612 #define CONFIG_FDTFILE "mpc8313erdb.dtb"
614 /* default location for tftp and bootm */
615 #define CONFIG_LOADADDR 800000
617 #define CONFIG_EXTRA_ENV_SETTINGS \
618 "netdev=" CONFIG_NETDEV "\0" \
620 "uboot=" CONFIG_UBOOTPATH "\0" \
621 "tftpflash=tftpboot $loadaddr $uboot; " \
622 "protect off " __stringify(CONFIG_SYS_TEXT_BASE) \
624 "erase " __stringify(CONFIG_SYS_TEXT_BASE) \
626 "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \
628 "protect on " __stringify(CONFIG_SYS_TEXT_BASE) \
630 "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \
633 "fdtfile=" CONFIG_FDTFILE "\0" \
635 "setbootargs=setenv bootargs " \
636 "root=$rootdev rw console=$console,$baudrate $othbootargs\0" \
637 "setipargs=setenv bootargs nfsroot=$serverip:$rootpath " \
638 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:"\
640 "root=$rootdev rw console=$console,$baudrate $othbootargs\0"
642 #define CONFIG_NFSBOOTCOMMAND \
643 "setenv rootdev /dev/nfs;" \
646 "tftp $loadaddr $bootfile;" \
647 "tftp $fdtaddr $fdtfile;" \
648 "bootm $loadaddr - $fdtaddr"
650 #define CONFIG_RAMBOOTCOMMAND \
651 "setenv rootdev /dev/ram;" \
653 "tftp $ramdiskaddr $ramdiskfile;" \
654 "tftp $loadaddr $bootfile;" \
655 "tftp $fdtaddr $fdtfile;" \
656 "bootm $loadaddr $ramdiskaddr $fdtaddr"
658 #endif /* __CONFIG_H */