2 * Copyright (C) Freescale Semiconductor, Inc. 2006.
4 * See file CREDITS for list of people who contributed to this
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of
10 * the License, or (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
23 * mpc8313epb board configuration file
30 * High Level Configuration Options
33 #define CONFIG_MPC83XX 1
34 #define CONFIG_MPC831X 1
35 #define CONFIG_MPC8313 1
36 #define CONFIG_MPC8313ERDB 1
39 #define CONFIG_83XX_GENERIC_PCI
42 #define CONFIG_83XX_CLKIN 66666667 /* in Hz */
43 #elif defined(CFG_33MHZ)
44 #define CONFIG_83XX_CLKIN 33333333 /* in Hz */
46 #error Unknown oscillator frequency.
49 #define CONFIG_SYS_CLK_FREQ CONFIG_83XX_CLKIN
51 #define CONFIG_BOARD_EARLY_INIT_F /* call board_pre_init */
53 #define CFG_IMMR 0xE0000000
55 #define CFG_MEMTEST_START 0x00001000
56 #define CFG_MEMTEST_END 0x07f00000
58 /* Early revs of this board will lock up hard when attempting
59 * to access the PMC registers, unless a JTAG debugger is
60 * connected, or some resistor modifications are made.
62 #define CFG_8313ERDB_BROKEN_PMC 1
64 #define CFG_ACR_PIPE_DEP 3 /* Arbiter pipeline depth (0-3) */
65 #define CFG_ACR_RPTCNT 3 /* Arbiter repeat count (0-7) */
70 #define CFG_DDR_BASE 0x00000000 /* DDR is system memory*/
71 #define CFG_SDRAM_BASE CFG_DDR_BASE
72 #define CFG_DDR_SDRAM_BASE CFG_DDR_BASE
75 * Manually set up DDR parameters, as this board does not
76 * seem to have the SPD connected to I2C.
78 #define CFG_DDR_SIZE 128 /* MB */
79 #define CFG_DDR_CONFIG ( CSCONFIG_EN | CSCONFIG_AP \
80 | 0x00040000 /* TODO */ \
81 | CSCONFIG_ROW_BIT_13 | CSCONFIG_COL_BIT_10 )
84 #define CFG_DDR_TIMING_3 0x00000000
85 #define CFG_DDR_TIMING_0 ( ( 0 << TIMING_CFG0_RWT_SHIFT ) \
86 | ( 0 << TIMING_CFG0_WRT_SHIFT ) \
87 | ( 0 << TIMING_CFG0_RRT_SHIFT ) \
88 | ( 0 << TIMING_CFG0_WWT_SHIFT ) \
89 | ( 2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT ) \
90 | ( 2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT ) \
91 | ( 8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT ) \
92 | ( 2 << TIMING_CFG0_MRS_CYC_SHIFT ) )
94 #define CFG_DDR_TIMING_1 ( ( 3 << TIMING_CFG1_PRETOACT_SHIFT ) \
95 | ( 9 << TIMING_CFG1_ACTTOPRE_SHIFT ) \
96 | ( 3 << TIMING_CFG1_ACTTORW_SHIFT ) \
97 | ( 5 << TIMING_CFG1_CASLAT_SHIFT ) \
98 | (13 << TIMING_CFG1_REFREC_SHIFT ) \
99 | ( 3 << TIMING_CFG1_WRREC_SHIFT ) \
100 | ( 2 << TIMING_CFG1_ACTTOACT_SHIFT ) \
101 | ( 2 << TIMING_CFG1_WRTORD_SHIFT ) )
103 #define CFG_DDR_TIMING_2 ( ( 0 << TIMING_CFG2_ADD_LAT_SHIFT ) \
104 | (31 << TIMING_CFG2_CPO_SHIFT ) \
105 | ( 2 << TIMING_CFG2_WR_LAT_DELAY_SHIFT ) \
106 | ( 2 << TIMING_CFG2_RD_TO_PRE_SHIFT ) \
107 | ( 2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT ) \
108 | ( 3 << TIMING_CFG2_CKE_PLS_SHIFT ) \
109 | (10 << TIMING_CFG2_FOUR_ACT_SHIFT) )
110 /* 0x0f9048ca */ /* P9-45,may need tuning */
111 #define CFG_DDR_INTERVAL ( ( 800 << SDRAM_INTERVAL_REFINT_SHIFT ) \
112 | ( 100 << SDRAM_INTERVAL_BSTOPRE_SHIFT ) )
114 #if defined(CONFIG_DDR_2T_TIMING)
115 #define CFG_SDRAM_CFG ( SDRAM_CFG_SREN \
116 | 3 << SDRAM_CFG_SDRAM_TYPE_SHIFT \
120 #define CFG_SDRAM_CFG ( SDRAM_CFG_SREN \
121 | 3 << SDRAM_CFG_SDRAM_TYPE_SHIFT \
125 #define CFG_SDRAM_CFG2 0x00401000;
126 /* set burst length to 8 for 32-bit data path */
127 #define CFG_DDR_MODE ( ( 0x4440 << SDRAM_MODE_ESD_SHIFT ) \
128 | ( 0x0232 << SDRAM_MODE_SD_SHIFT ) )
130 #define CFG_DDR_MODE_2 0x8000C000;
132 #define CFG_DDR_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05
134 #define CFG_DDRCDR_VALUE ( DDRCDR_EN \
140 * FLASH on the Local Bus
142 #define CFG_FLASH_CFI /* use the Common Flash Interface */
143 #define CFG_FLASH_CFI_DRIVER /* use the CFI driver */
144 #define CFG_FLASH_BASE 0xFE000000 /* start of FLASH */
145 #define CFG_FLASH_SIZE 8 /* flash size in MB */
146 #define CFG_FLASH_EMPTY_INFO /* display empty sectors */
147 #define CFG_FLASH_USE_BUFFER_WRITE /* buffer up multiple bytes */
149 #define CFG_BR0_PRELIM (CFG_FLASH_BASE | /* flash Base address */ \
150 (2 << BR_PS_SHIFT) | /* 16 bit port size */ \
152 #define CFG_OR0_PRELIM ( 0xFF000000 /* 16 MByte */ \
157 /* 0xFF006FF7 TODO SLOW 16 MB flash size */
158 #define CFG_LBLAWBAR0_PRELIM CFG_FLASH_BASE /* window base at flash base */
159 #define CFG_LBLAWAR0_PRELIM 0x80000017 /* 16 MB window size */
161 #define CFG_MAX_FLASH_BANKS 1 /* number of banks */
162 #define CFG_MAX_FLASH_SECT 135 /* sectors per device */
164 #define CFG_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
165 #define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
167 #define CFG_MONITOR_BASE TEXT_BASE /* start of monitor */
169 #if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
173 #define CFG_INIT_RAM_LOCK 1
174 #define CFG_INIT_RAM_ADDR 0xFD000000 /* Initial RAM address */
175 #define CFG_INIT_RAM_END 0x1000 /* End of used area in RAM*/
177 #define CFG_GBL_DATA_SIZE 0x100 /* num bytes initial data */
178 #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
179 #define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
181 #define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */
182 #define CFG_MALLOC_LEN (512 * 1024) /* Reserved for malloc */
185 * Local Bus LCRR and LBCR regs
187 #define CFG_LCRR LCRR_EADC_1 | LCRR_CLKDIV_2 /* 0x00010002 */
188 #define CFG_LBC_LBCR ( 0x00040000 /* TODO */ \
189 | (0xFF << LBCR_BMT_SHIFT) \
190 | 0xF ) /* 0x0004ff0f */
192 #define CFG_LBC_MRTPR 0x20000000 /*TODO */ /* LB refresh timer prescal, 266MHz/32 */
194 /* drivers/nand/nand.c */
195 #define CFG_NAND_BASE 0xE2800000 /* 0xF0000000 */
196 #define CFG_MAX_NAND_DEVICE 1
197 #define NAND_MAX_CHIPS 1
198 #define CONFIG_MTD_NAND_VERIFY_WRITE
200 #define CFG_BR1_PRELIM ( CFG_NAND_BASE \
201 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
202 | BR_PS_8 /* Port Size = 8 bit */ \
203 | BR_MS_FCM /* MSEL = FCM */ \
205 #define CFG_OR1_PRELIM ( 0xFFFF8000 /* length 32K */ \
213 #define CFG_LBLAWBAR1_PRELIM CFG_NAND_BASE
214 #define CFG_LBLAWAR1_PRELIM 0x8000000E /* 32KB */
216 #define CFG_VSC7385_BASE 0xF0000000
218 #define CONFIG_VSC7385_ENET /* VSC7385 ethernet support */
219 #define CFG_BR2_PRELIM 0xf0000801 /* VSC7385 Base address */
220 #define CFG_OR2_PRELIM 0xfffe09ff /* VSC7385, 128K bytes*/
221 #define CFG_LBLAWBAR2_PRELIM CFG_VSC7385_BASE/* Access window base at VSC7385 base */
222 #define CFG_LBLAWAR2_PRELIM 0x80000010 /* Access window size 128K */
224 /* local bus read write buffer mapping */
225 #define CFG_BR3_PRELIM 0xFA000801 /* map at 0xFA000000 */
226 #define CFG_OR3_PRELIM 0xFFFF8FF7 /* 32kB */
227 #define CFG_LBLAWBAR3_PRELIM 0xFA000000
228 #define CFG_LBLAWAR3_PRELIM 0x8000000E /* 32KB */
230 /* pass open firmware flat tree */
231 #define CONFIG_OF_FLAT_TREE 1
232 #define CONFIG_OF_BOARD_SETUP 1
234 /* maximum size of the flat tree (8K) */
235 #define OF_FLAT_TREE_MAX_SIZE 8192
237 #define OF_CPU "PowerPC,8313@0"
238 #define OF_SOC "soc8313@e0000000"
239 #define OF_TBCLK (bd->bi_busfreq / 4)
240 #define OF_STDOUT_PATH "/soc8313@e0000000/serial@4500"
245 #define CONFIG_CONS_INDEX 1
247 #define CFG_NS16550_SERIAL
248 #define CFG_NS16550_REG_SIZE 1
249 #define CFG_NS16550_CLK get_bus_freq(0)
251 #define CFG_BAUDRATE_TABLE \
252 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
254 #define CFG_NS16550_COM1 (CFG_IMMR+0x4500)
255 #define CFG_NS16550_COM2 (CFG_IMMR+0x4600)
257 /* Use the HUSH parser */
258 #define CFG_HUSH_PARSER
259 #define CFG_PROMPT_HUSH_PS2 "> "
262 #define CONFIG_HARD_I2C /* I2C with hardware support*/
263 #define CONFIG_FSL_I2C
264 #define CONFIG_I2C_MULTI_BUS
265 #define CONFIG_I2C_CMD_TREE
266 #define CFG_I2C_SPEED 400000 /* I2C speed and slave address */
267 #define CFG_I2C_SLAVE 0x7F
268 #define CFG_I2C_NOPROBES {0x69} /* Don't probe these addrs */
269 #define CFG_I2C_OFFSET 0x3000
270 #define CFG_I2C2_OFFSET 0x3100
273 #define CFG_TSEC1_OFFSET 0x24000
274 #define CFG_TSEC1 (CFG_IMMR+CFG_TSEC1_OFFSET)
275 #define CFG_TSEC2_OFFSET 0x25000
276 #define CFG_TSEC2 (CFG_IMMR+CFG_TSEC2_OFFSET)
277 #define CONFIG_NET_MULTI
281 * Addresses are mapped 1-1.
283 #define CFG_PCI1_MEM_BASE 0x80000000
284 #define CFG_PCI1_MEM_PHYS CFG_PCI1_MEM_BASE
285 #define CFG_PCI1_MEM_SIZE 0x10000000 /* 256M */
286 #define CFG_PCI1_MMIO_BASE 0x90000000
287 #define CFG_PCI1_MMIO_PHYS CFG_PCI1_MMIO_BASE
288 #define CFG_PCI1_MMIO_SIZE 0x10000000 /* 256M */
289 #define CFG_PCI1_IO_BASE 0x00000000
290 #define CFG_PCI1_IO_PHYS 0xE2000000
291 #define CFG_PCI1_IO_SIZE 0x00100000 /* 1M */
293 #define CONFIG_PCI_PNP /* do pci plug-and-play */
294 #define CFG_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */
299 #define CONFIG_TSEC_ENET /* TSEC ethernet support */
301 #ifndef CONFIG_NET_MULTI
302 #define CONFIG_NET_MULTI 1
305 #define CONFIG_GMII 1 /* MII PHY management */
306 #define CONFIG_MPC83XX_TSEC1 1
308 #define CONFIG_MPC83XX_TSEC1_NAME "TSEC0"
309 #define CONFIG_MPC83XX_TSEC2 1
310 #define CONFIG_MPC83XX_TSEC2_NAME "TSEC1"
311 #define TSEC1_PHY_ADDR 0x1c
312 #define TSEC2_PHY_ADDR 4
313 #define TSEC1_PHYIDX 0
314 #define TSEC2_PHYIDX 0
316 /* Options are: TSEC[0-1] */
317 #define CONFIG_ETHPRIME "TSEC1"
320 * Configure on-board RTC
322 #define CONFIG_RTC_DS1337
323 #define CFG_I2C_RTC_ADDR 0x68
329 #define CFG_ENV_IS_IN_FLASH 1
330 #define CFG_ENV_ADDR (CFG_MONITOR_BASE + 0x40000)
331 #define CFG_ENV_SECT_SIZE 0x10000 /* 64K(one sector) for env */
332 #define CFG_ENV_SIZE 0x2000
334 /* Address and size of Redundant Environment Sector */
336 #define CFG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */
337 #define CFG_ENV_ADDR (CFG_MONITOR_BASE - 0x1000)
338 #define CFG_ENV_SIZE 0x2000
341 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
342 #define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
344 #define CFG_BASE_COMMANDS ( CONFIG_CMD_DFL \
352 #define CONFIG_CMDLINE_EDITING 1
354 #define CFG_RAMBOOT_COMMANDS (CFG_BASE_COMMANDS & \
355 ~(CFG_CMD_ENV | CFG_CMD_LOADS))
357 #if defined(CFG_RAMBOOT)
358 #define CONFIG_COMMANDS CFG_RAMBOOT_COMMANDS
360 #define CONFIG_COMMANDS CFG_BASE_COMMANDS
363 #include <cmd_confdefs.h>
366 * Miscellaneous configurable options
368 #define CFG_LONGHELP /* undef to save memory */
369 #define CFG_LOAD_ADDR 0x2000000 /* default load address */
370 #define CFG_PROMPT "=> " /* Monitor Command Prompt */
371 #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
373 #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
374 #define CFG_MAXARGS 16 /* max number of command args */
375 #define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
376 #define CFG_HZ 1000 /* decrementer freq: 1ms ticks */
379 * For booting Linux, the board info and command line data
380 * have to be in the first 8 MB of memory, since this is
381 * the maximum mapped by the Linux kernel during initialization.
383 #define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/
385 /* Cache Configuration */
386 #define CFG_DCACHE_SIZE 16384
387 #define CFG_CACHELINE_SIZE 32
388 #define CFG_CACHELINE_SHIFT 5 /*log base 2 of the above value*/
390 #define CFG_RCWH_PCIHOST 0x80000000 /* PCIHOST */
394 /* 66MHz IN, 133MHz CSB, 266 DDR, 266 CORE */
396 #define CFG_HRCW_LOW (\
397 0x20000000 /* reserved, must be set */ |\
399 HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
400 HRCWL_DDR_TO_SCB_CLK_2X1 |\
401 HRCWL_CSB_TO_CLKIN_2X1 |\
402 HRCWL_CORE_TO_CSB_2X1)
404 #elif defined(CFG_33MHZ)
406 /* 33MHz IN, 165MHz CSB, 330 DDR, 330 CORE */
408 #define CFG_HRCW_LOW (\
409 0x20000000 /* reserved, must be set */ |\
411 HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
412 HRCWL_DDR_TO_SCB_CLK_2X1 |\
413 HRCWL_CSB_TO_CLKIN_5X1 |\
414 HRCWL_CORE_TO_CSB_2X1)
419 #define CFG_HRCW_HIGH (\
421 HRCWH_PCI1_ARBITER_ENABLE |\
423 HRCWH_FROM_0X00000100 |\
424 HRCWH_BOOTSEQ_DISABLE |\
425 HRCWH_SW_WATCHDOG_DISABLE |\
426 HRCWH_ROM_LOC_LOCAL_16BIT |\
427 HRCWH_RL_EXT_LEGACY |\
428 HRCWH_TSEC1M_IN_RGMII |\
429 HRCWH_TSEC2M_IN_RGMII |\
433 /* System IO Config */
434 #define CFG_SICRH (SICRH_TSOBI1 | SICRH_TSOBI2) /* RGMII */
435 #define CFG_SICRL SICRL_USBDR /* Enable Internal USB Phy */
437 #define CFG_HID0_INIT 0x000000000
438 #define CFG_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | \
439 HID0_ENABLE_DYNAMIC_POWER_MANAGMENT)
441 #define CFG_HID2 HID2_HBE
443 /* DDR @ 0x00000000 */
444 #define CFG_IBAT0L (CFG_SDRAM_BASE | BATL_PP_10)
445 #define CFG_IBAT0U (CFG_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
447 /* PCI @ 0x80000000 */
448 #define CFG_IBAT1L (CFG_PCI1_MEM_BASE | BATL_PP_10)
449 #define CFG_IBAT1U (CFG_PCI1_MEM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
450 #define CFG_IBAT2L (CFG_PCI1_MMIO_BASE | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
451 #define CFG_IBAT2U (CFG_PCI1_MMIO_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
453 /* PCI2 not supported on 8313 */
454 #define CFG_IBAT3L (0)
455 #define CFG_IBAT3U (0)
456 #define CFG_IBAT4L (0)
457 #define CFG_IBAT4U (0)
459 /* IMMRBAR @ 0xE0000000, PCI IO @ 0xE2000000 & BCSR @ 0xE2400000 */
460 #define CFG_IBAT5L (CFG_IMMR | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
461 #define CFG_IBAT5U (CFG_IMMR | BATU_BL_256M | BATU_VS | BATU_VP)
463 /* SDRAM @ 0xF0000000, stack in DCACHE 0xFDF00000 & FLASH @ 0xFE000000 */
464 #define CFG_IBAT6L (0xF0000000 | BATL_PP_10)
465 #define CFG_IBAT6U (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP)
467 #define CFG_IBAT7L (0)
468 #define CFG_IBAT7U (0)
470 #define CFG_DBAT0L CFG_IBAT0L
471 #define CFG_DBAT0U CFG_IBAT0U
472 #define CFG_DBAT1L CFG_IBAT1L
473 #define CFG_DBAT1U CFG_IBAT1U
474 #define CFG_DBAT2L CFG_IBAT2L
475 #define CFG_DBAT2U CFG_IBAT2U
476 #define CFG_DBAT3L CFG_IBAT3L
477 #define CFG_DBAT3U CFG_IBAT3U
478 #define CFG_DBAT4L CFG_IBAT4L
479 #define CFG_DBAT4U CFG_IBAT4U
480 #define CFG_DBAT5L CFG_IBAT5L
481 #define CFG_DBAT5U CFG_IBAT5U
482 #define CFG_DBAT6L CFG_IBAT6L
483 #define CFG_DBAT6U CFG_IBAT6U
484 #define CFG_DBAT7L CFG_IBAT7L
485 #define CFG_DBAT7U CFG_IBAT7U
488 * Internal Definitions
492 #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
493 #define BOOTFLAG_WARM 0x02 /* Software reboot */
496 * Environment Configuration
498 #define CONFIG_ENV_OVERWRITE
500 #define CONFIG_ETHADDR 00:E0:0C:00:95:01
501 #define CONFIG_HAS_ETH1
502 #define CONFIG_ETH1ADDR 00:E0:0C:00:95:02
504 #define CONFIG_IPADDR 10.0.0.2
505 #define CONFIG_SERVERIP 10.0.0.1
506 #define CONFIG_GATEWAYIP 10.0.0.1
507 #define CONFIG_NETMASK 255.0.0.0
508 #define CONFIG_NETDEV eth1
510 #define CONFIG_HOSTNAME mpc8313erdb
511 #define CONFIG_ROOTPATH /nfs/root/path
512 #define CONFIG_BOOTFILE uImage
513 #define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */
514 #define CONFIG_FDTFILE mpc8313erdb.dtb
516 #define CONFIG_LOADADDR 200000 /* default location for tftp and bootm */
517 #define CONFIG_BOOTDELAY -1 /* -1 disables auto-boot */
518 #define CONFIG_BAUDRATE 115200
520 #define XMK_STR(x) #x
521 #define MK_STR(x) XMK_STR(x)
523 #define CONFIG_EXTRA_ENV_SETTINGS \
524 "netdev=" MK_STR(CONFIG_NETDEV) "\0" \
526 "uboot=" MK_STR(CONFIG_UBOOTPATH) "\0" \
527 "tftpflash=tftpboot $loadaddr $uboot; " \
528 "protect off " MK_STR(TEXT_BASE) " +$filesize; " \
529 "erase " MK_STR(TEXT_BASE) " +$filesize; " \
530 "cp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize; " \
531 "protect on " MK_STR(TEXT_BASE) " +$filesize; " \
532 "cmp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize\0" \
534 "fdtfile=" MK_STR(CONFIG_FDTFILE) "\0" \
536 "setbootargs=setenv bootargs " \
537 "root=$rootdev rw console=$console,$baudrate $othbootargs\0" \
538 "setipargs=setenv bootargs nfsroot=$serverip:$rootpath " \
539 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
540 "root=$rootdev rw console=$console,$baudrate $othbootargs\0"
542 #define CONFIG_NFSBOOTCOMMAND \
543 "setenv rootdev /dev/nfs;" \
546 "tftp $loadaddr $bootfile;" \
547 "tftp $fdtaddr $fdtfile;" \
548 "bootm $loadaddr - $fdtaddr"
550 #define CONFIG_RAMBOOTCOMMAND \
551 "setenv rootdev /dev/ram;" \
553 "tftp $ramdiskaddr $ramdiskfile;" \
554 "tftp $loadaddr $bootfile;" \
555 "tftp $fdtaddr $fdtfile;" \
556 "bootm $loadaddr $ramdiskaddr $fdtaddr"
561 #endif /* __CONFIG_H */