2 * Copyright (C) 2007-2010 Freescale Semiconductor, Inc.
4 * Dave Liu <daveliu@freescale.com>
6 * SPDX-License-Identifier: GPL-2.0+
12 #define CONFIG_SYS_GENERIC_BOARD
13 #define CONFIG_DISPLAY_BOARDINFO
15 #define CONFIG_SYS_NAND_U_BOOT_SIZE (512 << 10)
16 #define CONFIG_SYS_NAND_U_BOOT_DST 0x00100000
17 #define CONFIG_SYS_NAND_U_BOOT_START 0x00100100
18 #define CONFIG_SYS_NAND_U_BOOT_OFFS 16384
19 #define CONFIG_SYS_NAND_U_BOOT_RELOC 0x00010000
21 #ifndef CONFIG_SYS_TEXT_BASE
22 #define CONFIG_SYS_TEXT_BASE 0xFE000000
25 #ifndef CONFIG_SYS_MONITOR_BASE
26 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
30 * High Level Configuration Options
32 #define CONFIG_E300 1 /* E300 family */
33 #define CONFIG_MPC831x 1 /* MPC831x CPU family */
34 #define CONFIG_MPC8315 1 /* MPC8315 CPU specific */
35 #define CONFIG_MPC8315ERDB 1 /* MPC8315ERDB board specific */
40 #define CONFIG_83XX_CLKIN 66666667 /* in Hz */
41 #define CONFIG_SYS_CLK_FREQ CONFIG_83XX_CLKIN
44 * Hardware Reset Configuration Word
45 * if CLKIN is 66.66MHz, then
46 * CSB = 133MHz, CORE = 400MHz, DDRC = 266MHz, LBC = 133MHz
48 #define CONFIG_SYS_HRCW_LOW (\
49 HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
50 HRCWL_DDR_TO_SCB_CLK_2X1 |\
52 HRCWL_CSB_TO_CLKIN_2X1 |\
53 HRCWL_CORE_TO_CSB_3X1)
54 #define CONFIG_SYS_HRCW_HIGH_BASE (\
56 HRCWH_PCI1_ARBITER_ENABLE |\
58 HRCWH_BOOTSEQ_DISABLE |\
59 HRCWH_SW_WATCHDOG_DISABLE |\
60 HRCWH_TSEC1M_IN_RGMII |\
61 HRCWH_TSEC2M_IN_RGMII |\
65 #ifdef CONFIG_NAND_SPL
66 #define CONFIG_SYS_HRCW_HIGH (CONFIG_SYS_HRCW_HIGH_BASE |\
67 HRCWH_FROM_0XFFF00100 |\
68 HRCWH_ROM_LOC_NAND_SP_8BIT |\
71 #define CONFIG_SYS_HRCW_HIGH (CONFIG_SYS_HRCW_HIGH_BASE |\
72 HRCWH_FROM_0X00000100 |\
73 HRCWH_ROM_LOC_LOCAL_16BIT |\
80 #define CONFIG_SYS_SICRH 0x00000000
81 #define CONFIG_SYS_SICRL 0x00000000 /* 3.3V, no delay */
83 #define CONFIG_BOARD_EARLY_INIT_F /* call board_pre_init */
84 #define CONFIG_HWCONFIG
89 #define CONFIG_SYS_IMMR 0xE0000000
94 #define CONFIG_SYS_ACR_PIPE_DEP 3 /* Arbiter pipeline depth is 4 */
95 #define CONFIG_SYS_ACR_RPTCNT 3 /* Arbiter repeat count is 4 */
96 #define CONFIG_SYS_SPCR_TSECEP 3 /* eTSEC emergency priority is highest */
101 #define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory */
102 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE
103 #define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE
104 #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05
105 #define CONFIG_SYS_DDRCDR_VALUE (DDRCDR_EN \
112 * Manually set up DDR parameters
113 * consist of two chips HY5PS12621BFP-C4 from HYNIX
115 #define CONFIG_SYS_DDR_SIZE 128 /* MB */
116 #define CONFIG_SYS_DDR_CS0_BNDS 0x00000007
117 #define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN \
118 | CSCONFIG_ODT_RD_NEVER \
119 | CSCONFIG_ODT_WR_ONLY_CURRENT \
120 | CSCONFIG_ROW_BIT_13 \
121 | CSCONFIG_COL_BIT_10)
123 #define CONFIG_SYS_DDR_TIMING_3 0x00000000
124 #define CONFIG_SYS_DDR_TIMING_0 ((0 << TIMING_CFG0_RWT_SHIFT) \
125 | (0 << TIMING_CFG0_WRT_SHIFT) \
126 | (0 << TIMING_CFG0_RRT_SHIFT) \
127 | (0 << TIMING_CFG0_WWT_SHIFT) \
128 | (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) \
129 | (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) \
130 | (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \
131 | (2 << TIMING_CFG0_MRS_CYC_SHIFT))
133 #define CONFIG_SYS_DDR_TIMING_1 ((2 << TIMING_CFG1_PRETOACT_SHIFT) \
134 | (7 << TIMING_CFG1_ACTTOPRE_SHIFT) \
135 | (2 << TIMING_CFG1_ACTTORW_SHIFT) \
136 | (5 << TIMING_CFG1_CASLAT_SHIFT) \
137 | (6 << TIMING_CFG1_REFREC_SHIFT) \
138 | (2 << TIMING_CFG1_WRREC_SHIFT) \
139 | (2 << TIMING_CFG1_ACTTOACT_SHIFT) \
140 | (2 << TIMING_CFG1_WRTORD_SHIFT))
142 #define CONFIG_SYS_DDR_TIMING_2 ((1 << TIMING_CFG2_ADD_LAT_SHIFT) \
143 | (4 << TIMING_CFG2_CPO_SHIFT) \
144 | (2 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) \
145 | (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) \
146 | (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) \
147 | (3 << TIMING_CFG2_CKE_PLS_SHIFT) \
148 | (5 << TIMING_CFG2_FOUR_ACT_SHIFT))
150 #define CONFIG_SYS_DDR_INTERVAL ((0x0360 << SDRAM_INTERVAL_REFINT_SHIFT) \
151 | (0x0100 << SDRAM_INTERVAL_BSTOPRE_SHIFT))
153 #define CONFIG_SYS_DDR_SDRAM_CFG (SDRAM_CFG_SREN \
154 | SDRAM_CFG_SDRAM_TYPE_DDR2 \
157 #define CONFIG_SYS_DDR_SDRAM_CFG2 0x00401000 /* 1 posted refresh */
158 #define CONFIG_SYS_DDR_MODE ((0x0448 << SDRAM_MODE_ESD_SHIFT) \
159 | (0x0232 << SDRAM_MODE_SD_SHIFT))
160 /* ODT 150ohm CL=3, AL=1 on SDRAM */
161 #define CONFIG_SYS_DDR_MODE2 0x00000000
166 #undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */
167 #define CONFIG_SYS_MEMTEST_START 0x00040000 /* memtest region */
168 #define CONFIG_SYS_MEMTEST_END 0x00140000
171 * The reserved memory
173 #define CONFIG_SYS_MONITOR_LEN (384 * 1024) /* Reserve 384 kB for Mon */
174 #define CONFIG_SYS_MALLOC_LEN (512 * 1024) /* Reserved for malloc */
177 * Initial RAM Base Address Setup
179 #define CONFIG_SYS_INIT_RAM_LOCK 1
180 #define CONFIG_SYS_INIT_RAM_ADDR 0xE6000000 /* Initial RAM address */
181 #define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM */
182 #define CONFIG_SYS_GBL_DATA_OFFSET \
183 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
186 * Local Bus Configuration & Clock Setup
188 #define CONFIG_SYS_LCRR_DBYP LCRR_DBYP
189 #define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_2
190 #define CONFIG_SYS_LBC_LBCR 0x00040000
191 #define CONFIG_FSL_ELBC 1
194 * FLASH on the Local Bus
196 #define CONFIG_SYS_FLASH_CFI /* use the Common Flash Interface */
197 #define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */
198 #define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
200 #define CONFIG_SYS_FLASH_BASE 0xFE000000 /* FLASH base address */
201 #define CONFIG_SYS_FLASH_SIZE 8 /* FLASH size is 8M */
202 #define CONFIG_SYS_FLASH_PROTECTION 1 /* Use h/w Flash protection. */
204 /* Window base at flash base */
205 #define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE
206 #define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_8MB)
208 #define CONFIG_SYS_NOR_BR_PRELIM (CONFIG_SYS_FLASH_BASE \
209 | BR_PS_16 /* 16 bit port */ \
210 | BR_MS_GPCM /* MSEL = GPCM */ \
212 #define CONFIG_SYS_NOR_OR_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \
222 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
223 /* 127 64KB sectors and 8 8KB top sectors per device */
224 #define CONFIG_SYS_MAX_FLASH_SECT 135
226 #undef CONFIG_SYS_FLASH_CHECKSUM
227 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
228 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
231 * NAND Flash on the Local Bus
234 #ifdef CONFIG_NAND_SPL
235 #define CONFIG_SYS_NAND_BASE 0xFFF00000
237 #define CONFIG_SYS_NAND_BASE 0xE0600000
240 #define CONFIG_MTD_DEVICE
241 #define CONFIG_MTD_PARTITION
242 #define CONFIG_CMD_MTDPARTS
243 #define MTDIDS_DEFAULT "nand0=e0600000.flash"
244 #define MTDPARTS_DEFAULT \
245 "mtdparts=e0600000.flash:512k(uboot),128k(env),3m@1m(kernel),-(fs)"
247 #define CONFIG_SYS_MAX_NAND_DEVICE 1
248 #define CONFIG_MTD_NAND_VERIFY_WRITE 1
249 #define CONFIG_CMD_NAND 1
250 #define CONFIG_NAND_FSL_ELBC 1
251 #define CONFIG_SYS_NAND_BLOCK_SIZE 16384
252 #define CONFIG_SYS_NAND_WINDOW_SIZE (32 * 1024) /* 0x00008000 */
254 #define CONFIG_SYS_NAND_U_BOOT_SIZE (512 << 10)
255 #define CONFIG_SYS_NAND_U_BOOT_DST 0x00100000
256 #define CONFIG_SYS_NAND_U_BOOT_START 0x00100100
257 #define CONFIG_SYS_NAND_U_BOOT_OFFS 16384
258 #define CONFIG_SYS_NAND_U_BOOT_RELOC 0x00010000
260 #define CONFIG_SYS_NAND_BR_PRELIM (CONFIG_SYS_NAND_BASE \
261 | BR_DECC_CHK_GEN /* Use HW ECC */ \
262 | BR_PS_8 /* 8 bit port */ \
263 | BR_MS_FCM /* MSEL = FCM */ \
265 #define CONFIG_SYS_NAND_OR_PRELIM \
266 (P2SZ_TO_AM(CONFIG_SYS_NAND_WINDOW_SIZE) \
275 #define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NOR_BR_PRELIM
276 #define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_NOR_OR_PRELIM
277 #define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_NAND_BR_PRELIM
278 #define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_NAND_OR_PRELIM
280 #define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_NAND_BASE
281 #define CONFIG_SYS_LBLAWAR1_PRELIM (LBLAWAR_EN | LBLAWAR_32KB)
283 #define CONFIG_SYS_NAND_LBLAWBAR_PRELIM CONFIG_SYS_LBLAWBAR1_PRELIM
284 #define CONFIG_SYS_NAND_LBLAWAR_PRELIM CONFIG_SYS_LBLAWAR1_PRELIM
286 #if CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE && \
287 !defined(CONFIG_NAND_SPL)
288 #define CONFIG_SYS_RAMBOOT
290 #undef CONFIG_SYS_RAMBOOT
296 #define CONFIG_CONS_INDEX 1
297 #define CONFIG_SYS_NS16550
298 #define CONFIG_SYS_NS16550_SERIAL
299 #define CONFIG_SYS_NS16550_REG_SIZE 1
300 #define CONFIG_SYS_NS16550_CLK (CONFIG_83XX_CLKIN * 2)
302 #define CONFIG_SYS_BAUDRATE_TABLE \
303 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
305 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500)
306 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600)
308 /* Use the HUSH parser */
309 #define CONFIG_SYS_HUSH_PARSER
311 /* Pass open firmware flat tree */
312 #define CONFIG_OF_LIBFDT 1
313 #define CONFIG_OF_BOARD_SETUP 1
314 #define CONFIG_OF_STDOUT_VIA_ALIAS 1
317 #define CONFIG_SYS_I2C
318 #define CONFIG_SYS_I2C_FSL
319 #define CONFIG_SYS_FSL_I2C_SPEED 400000
320 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
321 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
322 #define CONFIG_SYS_I2C_NOPROBES { {0, 0x51} }
325 * Board info - revision and where boot from
327 #define CONFIG_SYS_I2C_PCF8574A_ADDR 0x39
330 * Config on-board RTC
332 #define CONFIG_RTC_DS1337 /* ds1339 on board, use ds1337 rtc via i2c */
333 #define CONFIG_SYS_I2C_RTC_ADDR 0x68 /* at address 0x68 */
337 * Addresses are mapped 1-1.
339 #define CONFIG_SYS_PCI_MEM_BASE 0x80000000
340 #define CONFIG_SYS_PCI_MEM_PHYS CONFIG_SYS_PCI_MEM_BASE
341 #define CONFIG_SYS_PCI_MEM_SIZE 0x10000000 /* 256M */
342 #define CONFIG_SYS_PCI_MMIO_BASE 0x90000000
343 #define CONFIG_SYS_PCI_MMIO_PHYS CONFIG_SYS_PCI_MMIO_BASE
344 #define CONFIG_SYS_PCI_MMIO_SIZE 0x10000000 /* 256M */
345 #define CONFIG_SYS_PCI_IO_BASE 0x00000000
346 #define CONFIG_SYS_PCI_IO_PHYS 0xE0300000
347 #define CONFIG_SYS_PCI_IO_SIZE 0x100000 /* 1M */
349 #define CONFIG_SYS_PCI_SLV_MEM_LOCAL CONFIG_SYS_SDRAM_BASE
350 #define CONFIG_SYS_PCI_SLV_MEM_BUS 0x00000000
351 #define CONFIG_SYS_PCI_SLV_MEM_SIZE 0x80000000
353 #define CONFIG_SYS_PCIE1_BASE 0xA0000000
354 #define CONFIG_SYS_PCIE1_MEM_BASE 0xA0000000
355 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xA0000000
356 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000
357 #define CONFIG_SYS_PCIE1_CFG_BASE 0xB0000000
358 #define CONFIG_SYS_PCIE1_CFG_SIZE 0x01000000
359 #define CONFIG_SYS_PCIE1_IO_BASE 0x00000000
360 #define CONFIG_SYS_PCIE1_IO_PHYS 0xB1000000
361 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00800000
363 #define CONFIG_SYS_PCIE2_BASE 0xC0000000
364 #define CONFIG_SYS_PCIE2_MEM_BASE 0xC0000000
365 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xC0000000
366 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000
367 #define CONFIG_SYS_PCIE2_CFG_BASE 0xD0000000
368 #define CONFIG_SYS_PCIE2_CFG_SIZE 0x01000000
369 #define CONFIG_SYS_PCIE2_IO_BASE 0x00000000
370 #define CONFIG_SYS_PCIE2_IO_PHYS 0xD1000000
371 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00800000
374 #define CONFIG_PCI_INDIRECT_BRIDGE
377 #define CONFIG_PCI_PNP /* do pci plug-and-play */
379 #define CONFIG_EEPRO100
380 #undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
381 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */
383 #define CONFIG_HAS_FSL_DR_USB
384 #define CONFIG_SYS_SCCR_USBDRCM 3
386 #define CONFIG_CMD_USB
387 #define CONFIG_USB_STORAGE
388 #define CONFIG_USB_EHCI
389 #define CONFIG_USB_EHCI_FSL
390 #define CONFIG_USB_PHY_TYPE "utmi"
391 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
396 #define CONFIG_TSEC_ENET /* TSEC ethernet support */
397 #define CONFIG_SYS_TSEC1_OFFSET 0x24000
398 #define CONFIG_SYS_TSEC1 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC1_OFFSET)
399 #define CONFIG_SYS_TSEC2_OFFSET 0x25000
400 #define CONFIG_SYS_TSEC2 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC2_OFFSET)
403 * TSEC ethernet configuration
405 #define CONFIG_MII 1 /* MII PHY management */
406 #define CONFIG_TSEC1 1
407 #define CONFIG_TSEC1_NAME "eTSEC0"
408 #define CONFIG_TSEC2 1
409 #define CONFIG_TSEC2_NAME "eTSEC1"
410 #define TSEC1_PHY_ADDR 0
411 #define TSEC2_PHY_ADDR 1
412 #define TSEC1_PHYIDX 0
413 #define TSEC2_PHYIDX 0
414 #define TSEC1_FLAGS TSEC_GIGABIT
415 #define TSEC2_FLAGS TSEC_GIGABIT
417 /* Options are: eTSEC[0-1] */
418 #define CONFIG_ETHPRIME "eTSEC1"
423 #define CONFIG_LIBATA
424 #define CONFIG_FSL_SATA
426 #define CONFIG_SYS_SATA_MAX_DEVICE 2
428 #define CONFIG_SYS_SATA1_OFFSET 0x18000
429 #define CONFIG_SYS_SATA1 (CONFIG_SYS_IMMR + CONFIG_SYS_SATA1_OFFSET)
430 #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA
432 #define CONFIG_SYS_SATA2_OFFSET 0x19000
433 #define CONFIG_SYS_SATA2 (CONFIG_SYS_IMMR + CONFIG_SYS_SATA2_OFFSET)
434 #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA
436 #ifdef CONFIG_FSL_SATA
438 #define CONFIG_CMD_SATA
439 #define CONFIG_DOS_PARTITION
440 #define CONFIG_CMD_EXT2
446 #if !defined(CONFIG_SYS_RAMBOOT)
447 #define CONFIG_ENV_IS_IN_FLASH 1
448 #define CONFIG_ENV_ADDR \
449 (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
450 #define CONFIG_ENV_SECT_SIZE 0x10000 /* 64K(one sector) for env */
451 #define CONFIG_ENV_SIZE 0x2000
453 #define CONFIG_SYS_NO_FLASH 1 /* Flash is not usable now */
454 #define CONFIG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */
455 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
456 #define CONFIG_ENV_SIZE 0x2000
459 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
460 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
465 #define CONFIG_BOOTP_BOOTFILESIZE
466 #define CONFIG_BOOTP_BOOTPATH
467 #define CONFIG_BOOTP_GATEWAY
468 #define CONFIG_BOOTP_HOSTNAME
471 * Command line configuration.
473 #include <config_cmd_default.h>
475 #define CONFIG_CMD_PING
476 #define CONFIG_CMD_I2C
477 #define CONFIG_CMD_MII
478 #define CONFIG_CMD_DATE
479 #define CONFIG_CMD_PCI
481 #if defined(CONFIG_SYS_RAMBOOT)
482 #undef CONFIG_CMD_SAVEENV
483 #undef CONFIG_CMD_LOADS
486 #define CONFIG_CMDLINE_EDITING 1 /* add command line history */
487 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */
489 #undef CONFIG_WATCHDOG /* watchdog disabled */
492 * Miscellaneous configurable options
494 #define CONFIG_SYS_LONGHELP /* undef to save memory */
495 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
497 #if defined(CONFIG_CMD_KGDB)
498 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
500 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
503 /* Print Buffer Size */
504 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
505 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */
506 /* Boot Argument Buffer Size */
507 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
510 * For booting Linux, the board info and command line data
511 * have to be in the first 256 MB of memory, since this is
512 * the maximum mapped by the Linux kernel during initialization.
514 #define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* Initial Memory map for Linux */
519 #define CONFIG_SYS_HID0_INIT 0x000000000
520 #define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | \
521 HID0_ENABLE_INSTRUCTION_CACHE | \
522 HID0_ENABLE_DYNAMIC_POWER_MANAGMENT)
523 #define CONFIG_SYS_HID2 HID2_HBE
528 #define CONFIG_HIGH_BATS 1 /* High BATs supported */
530 /* DDR: cache cacheable */
531 #define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE \
534 #define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE \
538 #define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L
539 #define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U
541 /* IMMRBAR, PCI IO and NAND: cache-inhibit and guarded */
542 #define CONFIG_SYS_IBAT1L (CONFIG_SYS_IMMR \
544 | BATL_CACHEINHIBIT \
545 | BATL_GUARDEDSTORAGE)
546 #define CONFIG_SYS_IBAT1U (CONFIG_SYS_IMMR \
550 #define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L
551 #define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U
553 /* FLASH: icache cacheable, but dcache-inhibit and guarded */
554 #define CONFIG_SYS_IBAT2L (CONFIG_SYS_FLASH_BASE \
557 #define CONFIG_SYS_IBAT2U (CONFIG_SYS_FLASH_BASE \
561 #define CONFIG_SYS_DBAT2L (CONFIG_SYS_FLASH_BASE \
563 | BATL_CACHEINHIBIT \
564 | BATL_GUARDEDSTORAGE)
565 #define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U
567 /* Stack in dcache: cacheable, no memory coherence */
568 #define CONFIG_SYS_IBAT3L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW)
569 #define CONFIG_SYS_IBAT3U (CONFIG_SYS_INIT_RAM_ADDR \
573 #define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L
574 #define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U
576 /* PCI MEM space: cacheable */
577 #define CONFIG_SYS_IBAT4L (CONFIG_SYS_PCI_MEM_PHYS \
580 #define CONFIG_SYS_IBAT4U (CONFIG_SYS_PCI_MEM_PHYS \
584 #define CONFIG_SYS_DBAT4L CONFIG_SYS_IBAT4L
585 #define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U
587 /* PCI MMIO space: cache-inhibit and guarded */
588 #define CONFIG_SYS_IBAT5L (CONFIG_SYS_PCI_MMIO_PHYS \
590 | BATL_CACHEINHIBIT \
591 | BATL_GUARDEDSTORAGE)
592 #define CONFIG_SYS_IBAT5U (CONFIG_SYS_PCI_MMIO_PHYS \
596 #define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L
597 #define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U
599 #define CONFIG_SYS_IBAT6L 0
600 #define CONFIG_SYS_IBAT6U 0
601 #define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L
602 #define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U
604 #define CONFIG_SYS_IBAT7L 0
605 #define CONFIG_SYS_IBAT7U 0
606 #define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L
607 #define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U
609 #if defined(CONFIG_CMD_KGDB)
610 #define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */
614 * Environment Configuration
617 #define CONFIG_ENV_OVERWRITE
619 #if defined(CONFIG_TSEC_ENET)
620 #define CONFIG_HAS_ETH0
621 #define CONFIG_HAS_ETH1
624 #define CONFIG_BAUDRATE 115200
626 #define CONFIG_LOADADDR 800000 /* default location for tftp and bootm */
628 #define CONFIG_BOOTDELAY 6 /* -1 disables auto-boot */
629 #undef CONFIG_BOOTARGS /* the boot command will set bootargs */
631 #define CONFIG_EXTRA_ENV_SETTINGS \
633 "consoledev=ttyS0\0" \
634 "ramdiskaddr=1000000\0" \
635 "ramdiskfile=ramfs.83xx\0" \
637 "fdtfile=mpc8315erdb.dtb\0" \
638 "usb_phy_type=utmi\0" \
641 #define CONFIG_NFSBOOTCOMMAND \
642 "setenv bootargs root=/dev/nfs rw " \
643 "nfsroot=$serverip:$rootpath " \
644 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:" \
646 "console=$consoledev,$baudrate $othbootargs;" \
647 "tftp $loadaddr $bootfile;" \
648 "tftp $fdtaddr $fdtfile;" \
649 "bootm $loadaddr - $fdtaddr"
651 #define CONFIG_RAMBOOTCOMMAND \
652 "setenv bootargs root=/dev/ram rw " \
653 "console=$consoledev,$baudrate $othbootargs;" \
654 "tftp $ramdiskaddr $ramdiskfile;" \
655 "tftp $loadaddr $bootfile;" \
656 "tftp $fdtaddr $fdtfile;" \
657 "bootm $loadaddr $ramdiskaddr $fdtaddr"
660 #define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND
662 #endif /* __CONFIG_H */