2 * Copyright (C) 2006 Freescale Semiconductor, Inc.
4 * SPDX-License-Identifier: GPL-2.0+
11 * High Level Configuration Options
13 #define CONFIG_E300 1 /* E300 family */
14 #define CONFIG_QE 1 /* Has QE */
15 #define CONFIG_MPC832x 1 /* MPC832x CPU specific */
16 #define CONFIG_MPC832XEMDS 1 /* MPC832XEMDS board specific */
21 #ifdef CONFIG_PCISLAVE
22 #define CONFIG_83XX_PCICLK 66000000 /* in HZ */
24 #define CONFIG_83XX_CLKIN 66000000 /* in Hz */
27 #ifndef CONFIG_SYS_CLK_FREQ
28 #define CONFIG_SYS_CLK_FREQ 66000000
32 * Hardware Reset Configuration Word
34 #define CONFIG_SYS_HRCW_LOW (\
35 HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
36 HRCWL_DDR_TO_SCB_CLK_2X1 |\
38 HRCWL_CSB_TO_CLKIN_2X1 |\
39 HRCWL_CORE_TO_CSB_2X1 |\
40 HRCWL_CE_PLL_VCO_DIV_2 |\
41 HRCWL_CE_PLL_DIV_1X1 |\
44 #ifdef CONFIG_PCISLAVE
45 #define CONFIG_SYS_HRCW_HIGH (\
47 HRCWH_PCI1_ARBITER_DISABLE |\
49 HRCWH_FROM_0XFFF00100 |\
50 HRCWH_BOOTSEQ_DISABLE |\
51 HRCWH_SW_WATCHDOG_DISABLE |\
52 HRCWH_ROM_LOC_LOCAL_16BIT |\
56 #define CONFIG_SYS_HRCW_HIGH (\
58 HRCWH_PCI1_ARBITER_ENABLE |\
60 HRCWH_FROM_0X00000100 |\
61 HRCWH_BOOTSEQ_DISABLE |\
62 HRCWH_SW_WATCHDOG_DISABLE |\
63 HRCWH_ROM_LOC_LOCAL_16BIT |\
71 #define CONFIG_SYS_SICRL 0x00000000
73 #define CONFIG_BOARD_EARLY_INIT_R
78 #define CONFIG_SYS_IMMR 0xE0000000
83 #define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory */
84 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE
85 #define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE
86 #define CONFIG_SYS_DDRCDR 0x73000002 /* DDR II voltage is 1.8V */
88 #undef CONFIG_SPD_EEPROM
89 #if defined(CONFIG_SPD_EEPROM)
90 /* Determine DDR configuration from I2C interface
92 #define SPD_EEPROM_ADDRESS 0x51 /* DDR SODIMM */
94 /* Manually set up DDR parameters
96 #define CONFIG_SYS_DDR_SIZE 128 /* MB */
97 #define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN \
99 | CSCONFIG_ODT_WR_CFG \
100 | CSCONFIG_ROW_BIT_13 \
101 | CSCONFIG_COL_BIT_10)
103 #define CONFIG_SYS_DDR_TIMING_0 ((0 << TIMING_CFG0_RWT_SHIFT) \
104 | (0 << TIMING_CFG0_WRT_SHIFT) \
105 | (0 << TIMING_CFG0_RRT_SHIFT) \
106 | (0 << TIMING_CFG0_WWT_SHIFT) \
107 | (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) \
108 | (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) \
109 | (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \
110 | (2 << TIMING_CFG0_MRS_CYC_SHIFT))
112 #define CONFIG_SYS_DDR_TIMING_1 ((3 << TIMING_CFG1_PRETOACT_SHIFT) \
113 | (9 << TIMING_CFG1_ACTTOPRE_SHIFT) \
114 | (3 << TIMING_CFG1_ACTTORW_SHIFT) \
115 | (5 << TIMING_CFG1_CASLAT_SHIFT) \
116 | (13 << TIMING_CFG1_REFREC_SHIFT) \
117 | (3 << TIMING_CFG1_WRREC_SHIFT) \
118 | (2 << TIMING_CFG1_ACTTOACT_SHIFT) \
119 | (2 << TIMING_CFG1_WRTORD_SHIFT))
121 #define CONFIG_SYS_DDR_TIMING_2 ((0 << TIMING_CFG2_ADD_LAT_SHIFT) \
122 | (31 << TIMING_CFG2_CPO_SHIFT) \
123 | (2 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) \
124 | (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) \
125 | (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) \
126 | (3 << TIMING_CFG2_CKE_PLS_SHIFT) \
127 | (10 << TIMING_CFG2_FOUR_ACT_SHIFT))
129 #define CONFIG_SYS_DDR_TIMING_3 0x00000000
130 #define CONFIG_SYS_DDR_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05
132 #define CONFIG_SYS_DDR_MODE ((0x4440 << SDRAM_MODE_ESD_SHIFT) \
133 | (0x0232 << SDRAM_MODE_SD_SHIFT))
135 #define CONFIG_SYS_DDR_MODE2 0x8000c000
136 #define CONFIG_SYS_DDR_INTERVAL ((800 << SDRAM_INTERVAL_REFINT_SHIFT) \
137 | (100 << SDRAM_INTERVAL_BSTOPRE_SHIFT))
139 #define CONFIG_SYS_DDR_CS0_BNDS 0x00000007
140 #define CONFIG_SYS_DDR_SDRAM_CFG (SDRAM_CFG_SREN \
141 | SDRAM_CFG_SDRAM_TYPE_DDR2 \
144 #define CONFIG_SYS_DDR_SDRAM_CFG2 0x00401000
150 #undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */
151 #define CONFIG_SYS_MEMTEST_START 0x00000000 /* memtest region */
152 #define CONFIG_SYS_MEMTEST_END 0x00100000
155 * The reserved memory
157 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
159 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
160 #define CONFIG_SYS_RAMBOOT
162 #undef CONFIG_SYS_RAMBOOT
165 /* CONFIG_SYS_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */
166 #define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 kB for Mon */
167 #define CONFIG_SYS_MALLOC_LEN (256 * 1024) /* Reserved for malloc */
170 * Initial RAM Base Address Setup
172 #define CONFIG_SYS_INIT_RAM_LOCK 1
173 #define CONFIG_SYS_INIT_RAM_ADDR 0xE6000000 /* Initial RAM addr */
174 #define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM */
175 #define CONFIG_SYS_GBL_DATA_OFFSET \
176 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
179 * Local Bus Configuration & Clock Setup
181 #define CONFIG_SYS_LCRR_DBYP LCRR_DBYP
182 #define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_2
183 #define CONFIG_SYS_LBC_LBCR 0x00000000
186 * FLASH on the Local Bus
188 #define CONFIG_SYS_FLASH_CFI /* use the Common Flash Interface */
189 #define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */
190 #define CONFIG_SYS_FLASH_BASE 0xFE000000 /* FLASH base address */
191 #define CONFIG_SYS_FLASH_SIZE 16 /* FLASH size is 16M */
192 #define CONFIG_SYS_FLASH_PROTECTION 1 /* Use h/w Flash protection. */
194 /* Window base at flash base */
195 #define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE
196 #define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_32MB)
198 #define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE \
199 | BR_PS_16 /* 16 bit port */ \
200 | BR_MS_GPCM /* MSEL = GPCM */ \
202 #define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \
213 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
214 #define CONFIG_SYS_MAX_FLASH_SECT 128 /* sectors per device */
216 #undef CONFIG_SYS_FLASH_CHECKSUM
219 * BCSR on the Local Bus
221 #define CONFIG_SYS_BCSR 0xF8000000
222 /* Access window base at BCSR base */
223 #define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_BCSR
224 #define CONFIG_SYS_LBLAWAR1_PRELIM (LBLAWAR_EN | LBLAWAR_32KB)
226 #define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_BCSR \
230 #define CONFIG_SYS_OR1_PRELIM (OR_AM_32KB \
241 * Windows to access PIB via local bus
243 /* PIB window base 0xF8008000 */
244 #define CONFIG_SYS_PIB_BASE 0xF8008000
245 #define CONFIG_SYS_PIB_WINDOW_SIZE (32 * 1024)
246 #define CONFIG_SYS_LBLAWBAR3_PRELIM CONFIG_SYS_PIB_BASE
247 #define CONFIG_SYS_LBLAWAR3_PRELIM (LBLAWAR_EN | LBLAWAR_64KB)
250 * CS2 on Local Bus, to PIB
252 #define CONFIG_SYS_BR2_PRELIM (CONFIG_SYS_PIB_BASE \
257 #define CONFIG_SYS_OR2_PRELIM (P2SZ_TO_AM(CONFIG_SYS_PIB_WINDOW_SIZE) \
268 * CS3 on Local Bus, to PIB
270 #define CONFIG_SYS_BR3_PRELIM ((CONFIG_SYS_PIB_BASE + \
271 CONFIG_SYS_PIB_WINDOW_SIZE) \
276 #define CONFIG_SYS_OR3_PRELIM (P2SZ_TO_AM(CONFIG_SYS_PIB_WINDOW_SIZE) \
289 #define CONFIG_SYS_NS16550_SERIAL
290 #define CONFIG_SYS_NS16550_REG_SIZE 1
291 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
293 #define CONFIG_SYS_BAUDRATE_TABLE \
294 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
296 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500)
297 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600)
300 #define CONFIG_SYS_I2C
301 #define CONFIG_SYS_I2C_FSL
302 #define CONFIG_SYS_FSL_I2C_SPEED 400000
303 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
304 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
305 #define CONFIG_SYS_I2C_NOPROBES { {0, 0x51} }
308 * Config on-board RTC
310 #define CONFIG_RTC_DS1374 /* use ds1374 rtc via i2c */
311 #define CONFIG_SYS_I2C_RTC_ADDR 0x68 /* at address 0x68 */
315 * Addresses are mapped 1-1.
317 #define CONFIG_SYS_PCI1_MEM_BASE 0x80000000
318 #define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE
319 #define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000 /* 256M */
320 #define CONFIG_SYS_PCI1_MMIO_BASE 0x90000000
321 #define CONFIG_SYS_PCI1_MMIO_PHYS CONFIG_SYS_PCI1_MMIO_BASE
322 #define CONFIG_SYS_PCI1_MMIO_SIZE 0x10000000 /* 256M */
323 #define CONFIG_SYS_PCI1_IO_BASE 0x00000000
324 #define CONFIG_SYS_PCI1_IO_PHYS 0xE0300000
325 #define CONFIG_SYS_PCI1_IO_SIZE 0x100000 /* 1M */
327 #define CONFIG_SYS_PCI_SLV_MEM_LOCAL CONFIG_SYS_SDRAM_BASE
328 #define CONFIG_SYS_PCI_SLV_MEM_BUS 0x00000000
329 #define CONFIG_SYS_PCI_SLV_MEM_SIZE 0x80000000
332 #define CONFIG_PCI_INDIRECT_BRIDGE
334 #define CONFIG_83XX_PCI_STREAMING
336 #undef CONFIG_EEPRO100
337 #undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
338 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */
340 #endif /* CONFIG_PCI */
343 * QE UEC ethernet configuration
345 #define CONFIG_UEC_ETH
346 #define CONFIG_ETHPRIME "UEC0"
348 #define CONFIG_UEC_ETH1 /* ETH3 */
350 #ifdef CONFIG_UEC_ETH1
351 #define CONFIG_SYS_UEC1_UCC_NUM 2 /* UCC3 */
352 #define CONFIG_SYS_UEC1_RX_CLK QE_CLK9
353 #define CONFIG_SYS_UEC1_TX_CLK QE_CLK10
354 #define CONFIG_SYS_UEC1_ETH_TYPE FAST_ETH
355 #define CONFIG_SYS_UEC1_PHY_ADDR 3
356 #define CONFIG_SYS_UEC1_INTERFACE_TYPE PHY_INTERFACE_MODE_MII
357 #define CONFIG_SYS_UEC1_INTERFACE_SPEED 100
360 #define CONFIG_UEC_ETH2 /* ETH4 */
362 #ifdef CONFIG_UEC_ETH2
363 #define CONFIG_SYS_UEC2_UCC_NUM 3 /* UCC4 */
364 #define CONFIG_SYS_UEC2_RX_CLK QE_CLK7
365 #define CONFIG_SYS_UEC2_TX_CLK QE_CLK8
366 #define CONFIG_SYS_UEC2_ETH_TYPE FAST_ETH
367 #define CONFIG_SYS_UEC2_PHY_ADDR 4
368 #define CONFIG_SYS_UEC2_INTERFACE_TYPE PHY_INTERFACE_MODE_MII
369 #define CONFIG_SYS_UEC2_INTERFACE_SPEED 100
375 #ifndef CONFIG_SYS_RAMBOOT
376 #define CONFIG_ENV_ADDR \
377 (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
378 #define CONFIG_ENV_SECT_SIZE 0x20000
379 #define CONFIG_ENV_SIZE 0x2000
381 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
382 #define CONFIG_ENV_SIZE 0x2000
385 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
386 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
391 #define CONFIG_BOOTP_BOOTFILESIZE
394 * Command line configuration.
397 #undef CONFIG_WATCHDOG /* watchdog disabled */
400 * Miscellaneous configurable options
402 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
405 * For booting Linux, the board info and command line data
406 * have to be in the first 256 MB of memory, since this is
407 * the maximum mapped by the Linux kernel during initialization.
409 /* Initial Memory map for Linux */
410 #define CONFIG_SYS_BOOTMAPSZ (256 << 20)
411 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
416 #define CONFIG_SYS_HID0_INIT 0x000000000
417 #define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | \
418 HID0_ENABLE_INSTRUCTION_CACHE)
419 #define CONFIG_SYS_HID2 HID2_HBE
425 #define CONFIG_HIGH_BATS 1 /* High BATs supported */
427 /* DDR: cache cacheable */
428 #define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE \
431 #define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE \
435 #define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L
436 #define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U
438 /* IMMRBAR & PCI IO: cache-inhibit and guarded */
439 #define CONFIG_SYS_IBAT1L (CONFIG_SYS_IMMR \
441 | BATL_CACHEINHIBIT \
442 | BATL_GUARDEDSTORAGE)
443 #define CONFIG_SYS_IBAT1U (CONFIG_SYS_IMMR \
447 #define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L
448 #define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U
450 /* BCSR: cache-inhibit and guarded */
451 #define CONFIG_SYS_IBAT2L (CONFIG_SYS_BCSR \
453 | BATL_CACHEINHIBIT \
454 | BATL_GUARDEDSTORAGE)
455 #define CONFIG_SYS_IBAT2U (CONFIG_SYS_BCSR \
459 #define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L
460 #define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U
462 /* FLASH: icache cacheable, but dcache-inhibit and guarded */
463 #define CONFIG_SYS_IBAT3L (CONFIG_SYS_FLASH_BASE \
466 #define CONFIG_SYS_IBAT3U (CONFIG_SYS_FLASH_BASE \
470 #define CONFIG_SYS_DBAT3L (CONFIG_SYS_FLASH_BASE \
472 | BATL_CACHEINHIBIT \
473 | BATL_GUARDEDSTORAGE)
474 #define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U
476 #define CONFIG_SYS_IBAT4L (0)
477 #define CONFIG_SYS_IBAT4U (0)
478 #define CONFIG_SYS_DBAT4L CONFIG_SYS_IBAT4L
479 #define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U
481 /* Stack in dcache: cacheable, no memory coherence */
482 #define CONFIG_SYS_IBAT5L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW)
483 #define CONFIG_SYS_IBAT5U (CONFIG_SYS_INIT_RAM_ADDR \
487 #define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L
488 #define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U
491 /* PCI MEM space: cacheable */
492 #define CONFIG_SYS_IBAT6L (CONFIG_SYS_PCI1_MEM_PHYS \
495 #define CONFIG_SYS_IBAT6U (CONFIG_SYS_PCI1_MEM_PHYS \
499 #define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L
500 #define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U
501 /* PCI MMIO space: cache-inhibit and guarded */
502 #define CONFIG_SYS_IBAT7L (CONFIG_SYS_PCI1_MMIO_PHYS \
504 | BATL_CACHEINHIBIT \
505 | BATL_GUARDEDSTORAGE)
506 #define CONFIG_SYS_IBAT7U (CONFIG_SYS_PCI1_MMIO_PHYS \
510 #define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L
511 #define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U
513 #define CONFIG_SYS_IBAT6L (0)
514 #define CONFIG_SYS_IBAT6U (0)
515 #define CONFIG_SYS_IBAT7L (0)
516 #define CONFIG_SYS_IBAT7U (0)
517 #define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L
518 #define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U
519 #define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L
520 #define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U
523 #if defined(CONFIG_CMD_KGDB)
524 #define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */
528 * Environment Configuration
529 */ #define CONFIG_ENV_OVERWRITE
531 #if defined(CONFIG_UEC_ETH)
532 #define CONFIG_HAS_ETH0
533 #define CONFIG_HAS_ETH1
536 #define CONFIG_LOADADDR 800000 /* default location for tftp and bootm */
538 #define CONFIG_EXTRA_ENV_SETTINGS \
540 "consoledev=ttyS0\0" \
541 "ramdiskaddr=1000000\0" \
542 "ramdiskfile=ramfs.83xx\0" \
544 "fdtfile=mpc832x_mds.dtb\0" \
547 #define CONFIG_NFSBOOTCOMMAND \
548 "setenv bootargs root=/dev/nfs rw " \
549 "nfsroot=$serverip:$rootpath " \
550 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:" \
552 "console=$consoledev,$baudrate $othbootargs;" \
553 "tftp $loadaddr $bootfile;" \
554 "tftp $fdtaddr $fdtfile;" \
555 "bootm $loadaddr - $fdtaddr"
557 #define CONFIG_RAMBOOTCOMMAND \
558 "setenv bootargs root=/dev/ram rw " \
559 "console=$consoledev,$baudrate $othbootargs;" \
560 "tftp $ramdiskaddr $ramdiskfile;" \
561 "tftp $loadaddr $bootfile;" \
562 "tftp $fdtaddr $fdtfile;" \
563 "bootm $loadaddr $ramdiskaddr $fdtaddr"
565 #define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND
567 #endif /* __CONFIG_H */