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[u-boot] / include / configs / MPC837XEMDS.h
1 /* SPDX-License-Identifier: GPL-2.0+ */
2 /*
3  * Copyright (C) 2007 Freescale Semiconductor, Inc.
4  * Dave Liu <daveliu@freescale.com>
5  */
6
7 #ifndef __CONFIG_H
8 #define __CONFIG_H
9
10 /*
11  * High Level Configuration Options
12  */
13 #define CONFIG_E300             1 /* E300 family */
14 #define CONFIG_MPC837x          1 /* MPC837x CPU specific */
15 #define CONFIG_MPC837XEMDS      1 /* MPC837XEMDS board specific */
16
17 /*
18  * System Clock Setup
19  */
20 #ifdef CONFIG_PCISLAVE
21 #define CONFIG_83XX_PCICLK      66000000 /* in HZ */
22 #else
23 #define CONFIG_83XX_CLKIN       66000000 /* in Hz */
24 #endif
25
26 #ifndef CONFIG_SYS_CLK_FREQ
27 #define CONFIG_SYS_CLK_FREQ     66000000
28 #endif
29
30 /*
31  * Hardware Reset Configuration Word
32  * if CLKIN is 66MHz, then
33  * CSB = 396MHz, CORE = 594MHz, DDRC = 396MHz, LBC = 396MHz
34  */
35 #define CONFIG_SYS_HRCW_LOW (\
36         HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
37         HRCWL_DDR_TO_SCB_CLK_1X1 |\
38         HRCWL_SVCOD_DIV_2 |\
39         HRCWL_CSB_TO_CLKIN_6X1 |\
40         HRCWL_CORE_TO_CSB_1_5X1)
41
42 #ifdef CONFIG_PCISLAVE
43 #define CONFIG_SYS_HRCW_HIGH (\
44         HRCWH_PCI_AGENT |\
45         HRCWH_PCI1_ARBITER_DISABLE |\
46         HRCWH_CORE_ENABLE |\
47         HRCWH_FROM_0XFFF00100 |\
48         HRCWH_BOOTSEQ_DISABLE |\
49         HRCWH_SW_WATCHDOG_DISABLE |\
50         HRCWH_ROM_LOC_LOCAL_16BIT |\
51         HRCWH_RL_EXT_LEGACY |\
52         HRCWH_TSEC1M_IN_RGMII |\
53         HRCWH_TSEC2M_IN_RGMII |\
54         HRCWH_BIG_ENDIAN |\
55         HRCWH_LDP_CLEAR)
56 #else
57 #define CONFIG_SYS_HRCW_HIGH (\
58         HRCWH_PCI_HOST |\
59         HRCWH_PCI1_ARBITER_ENABLE |\
60         HRCWH_CORE_ENABLE |\
61         HRCWH_FROM_0X00000100 |\
62         HRCWH_BOOTSEQ_DISABLE |\
63         HRCWH_SW_WATCHDOG_DISABLE |\
64         HRCWH_ROM_LOC_LOCAL_16BIT |\
65         HRCWH_RL_EXT_LEGACY |\
66         HRCWH_TSEC1M_IN_RGMII |\
67         HRCWH_TSEC2M_IN_RGMII |\
68         HRCWH_BIG_ENDIAN |\
69         HRCWH_LDP_CLEAR)
70 #endif
71
72 /* Arbiter Configuration Register */
73 #define CONFIG_SYS_ACR_PIPE_DEP 3       /* Arbiter pipeline depth is 4 */
74 #define CONFIG_SYS_ACR_RPTCNT   3       /* Arbiter repeat count is 4 */
75
76 /* System Priority Control Register */
77 #define CONFIG_SYS_SPCR_TSECEP  3 /* eTSEC1/2 emergency has highest priority */
78
79 /*
80  * IP blocks clock configuration
81  */
82 #define CONFIG_SYS_SCCR_TSEC1CM 1       /* CSB:eTSEC1 = 1:1 */
83 #define CONFIG_SYS_SCCR_TSEC2CM 1       /* CSB:eTSEC2 = 1:1 */
84 #define CONFIG_SYS_SCCR_SATACM  SCCR_SATACM_2   /* CSB:SATA[0:3] = 2:1 */
85
86 /*
87  * System IO Config
88  */
89 #define CONFIG_SYS_SICRH                0x00000000
90 #define CONFIG_SYS_SICRL                0x00000000
91
92 /*
93  * Output Buffer Impedance
94  */
95 #define CONFIG_SYS_OBIR         0x31100000
96
97 #define CONFIG_HWCONFIG
98
99 /*
100  * IMMR new address
101  */
102 #define CONFIG_SYS_IMMR         0xE0000000
103
104 /*
105  * DDR Setup
106  */
107 #define CONFIG_SYS_DDR_BASE             0x00000000 /* DDR is system memory */
108 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_BASE
109 #define CONFIG_SYS_DDR_SDRAM_BASE       CONFIG_SYS_DDR_BASE
110 #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL   DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05
111 #define CONFIG_SYS_83XX_DDR_USES_CS0
112 #define CONFIG_SYS_DDRCDR_VALUE         (DDRCDR_DHC_EN \
113                                         | DDRCDR_ODT \
114                                         | DDRCDR_Q_DRN)
115                                         /* 0x80080001 */ /* ODT 150ohm on SoC */
116
117 #undef CONFIG_DDR_ECC           /* support DDR ECC function */
118 #undef CONFIG_DDR_ECC_CMD       /* Use DDR ECC user commands */
119
120 #define CONFIG_SPD_EEPROM       /* Use SPD EEPROM for DDR setup */
121 #define CONFIG_NEVER_ASSERT_ODT_TO_CPU /* Never assert ODT to internal IOs */
122
123 #if defined(CONFIG_SPD_EEPROM)
124 #define SPD_EEPROM_ADDRESS      0x51 /* I2C address of DDR SODIMM SPD */
125 #else
126 /*
127  * Manually set up DDR parameters
128  * WHITE ELECTRONIC DESIGNS - W3HG64M72EEU403PD4 SO-DIMM
129  * consist of nine chips from SAMSUNG K4T51083QE-ZC(L)D5
130  */
131 #define CONFIG_SYS_DDR_SIZE             512 /* MB */
132 #define CONFIG_SYS_DDR_CS0_BNDS 0x0000001f
133 #define CONFIG_SYS_DDR_CS0_CONFIG       (CSCONFIG_EN \
134                         | CSCONFIG_ODT_RD_NEVER  /* ODT_RD to none */ \
135                         | CSCONFIG_ODT_WR_ONLY_CURRENT  /* ODT_WR to CSn */ \
136                         | CSCONFIG_ROW_BIT_14 \
137                         | CSCONFIG_COL_BIT_10)
138                         /* 0x80010202 */
139 #define CONFIG_SYS_DDR_TIMING_3 0x00000000
140 #define CONFIG_SYS_DDR_TIMING_0 ((0 << TIMING_CFG0_RWT_SHIFT) \
141                                 | (0 << TIMING_CFG0_WRT_SHIFT) \
142                                 | (0 << TIMING_CFG0_RRT_SHIFT) \
143                                 | (0 << TIMING_CFG0_WWT_SHIFT) \
144                                 | (6 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) \
145                                 | (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) \
146                                 | (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \
147                                 | (2 << TIMING_CFG0_MRS_CYC_SHIFT))
148                                 /* 0x00620802 */
149 #define CONFIG_SYS_DDR_TIMING_1 ((3 << TIMING_CFG1_PRETOACT_SHIFT) \
150                                 | (9 << TIMING_CFG1_ACTTOPRE_SHIFT) \
151                                 | (3 << TIMING_CFG1_ACTTORW_SHIFT) \
152                                 | (5 << TIMING_CFG1_CASLAT_SHIFT) \
153                                 | (13 << TIMING_CFG1_REFREC_SHIFT) \
154                                 | (3 << TIMING_CFG1_WRREC_SHIFT) \
155                                 | (2 << TIMING_CFG1_ACTTOACT_SHIFT) \
156                                 | (2 << TIMING_CFG1_WRTORD_SHIFT))
157                                 /* 0x3935d322 */
158 #define CONFIG_SYS_DDR_TIMING_2 ((1 << TIMING_CFG2_ADD_LAT_SHIFT) \
159                                 | (6 << TIMING_CFG2_CPO_SHIFT) \
160                                 | (2 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) \
161                                 | (4 << TIMING_CFG2_RD_TO_PRE_SHIFT) \
162                                 | (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) \
163                                 | (3 << TIMING_CFG2_CKE_PLS_SHIFT) \
164                                 | (8 << TIMING_CFG2_FOUR_ACT_SHIFT))
165                                 /* 0x131088c8 */
166 #define CONFIG_SYS_DDR_INTERVAL ((0x03E0 << SDRAM_INTERVAL_REFINT_SHIFT) \
167                                 | (0x0100 << SDRAM_INTERVAL_BSTOPRE_SHIFT))
168                                 /* 0x03E00100 */
169 #define CONFIG_SYS_DDR_SDRAM_CFG        0x43000000
170 #define CONFIG_SYS_DDR_SDRAM_CFG2       0x00001000 /* 1 posted refresh */
171 #define CONFIG_SYS_DDR_MODE     ((0x0448 << SDRAM_MODE_ESD_SHIFT) \
172                                 | (0x1432 << SDRAM_MODE_SD_SHIFT))
173                                 /* ODT 150ohm CL=3, AL=1 on SDRAM */
174 #define CONFIG_SYS_DDR_MODE2    0x00000000
175 #endif
176
177 /*
178  * Memory test
179  */
180 #undef CONFIG_SYS_DRAM_TEST             /* memory test, takes time */
181 #define CONFIG_SYS_MEMTEST_START        0x00040000 /* memtest region */
182 #define CONFIG_SYS_MEMTEST_END          0x00140000
183
184 /*
185  * The reserved memory
186  */
187 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
188
189 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
190 #define CONFIG_SYS_RAMBOOT
191 #else
192 #undef CONFIG_SYS_RAMBOOT
193 #endif
194
195 /* CONFIG_SYS_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */
196 #define CONFIG_SYS_MONITOR_LEN  (512 * 1024) /* Reserve 512 kB for Mon */
197 #define CONFIG_SYS_MALLOC_LEN   (512 * 1024) /* Reserved for malloc */
198
199 /*
200  * Initial RAM Base Address Setup
201  */
202 #define CONFIG_SYS_INIT_RAM_LOCK        1
203 #define CONFIG_SYS_INIT_RAM_ADDR        0xE6000000 /* Initial RAM address */
204 #define CONFIG_SYS_INIT_RAM_SIZE        0x1000 /* Size of used area in RAM */
205 #define CONFIG_SYS_GBL_DATA_OFFSET      \
206                         (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
207
208 /*
209  * Local Bus Configuration & Clock Setup
210  */
211 #define CONFIG_SYS_LCRR_DBYP    LCRR_DBYP
212 #define CONFIG_SYS_LCRR_CLKDIV  LCRR_CLKDIV_8
213 #define CONFIG_SYS_LBC_LBCR             0x00000000
214 #define CONFIG_FSL_ELBC         1
215
216 /*
217  * FLASH on the Local Bus
218  */
219 #define CONFIG_SYS_FLASH_CFI    /* use the Common Flash Interface */
220 #define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */
221 #define CONFIG_SYS_FLASH_BASE   0xFE000000 /* FLASH base address */
222 #define CONFIG_SYS_FLASH_SIZE   32 /* max FLASH size is 32M */
223 #define CONFIG_SYS_FLASH_PROTECTION     1       /* Use h/w Flash protection. */
224
225                                         /* Window base at flash base */
226 #define CONFIG_SYS_LBLAWBAR0_PRELIM     CONFIG_SYS_FLASH_BASE
227 #define CONFIG_SYS_LBLAWAR0_PRELIM      (LBLAWAR_EN | LBLAWAR_32MB)
228
229 #define CONFIG_SYS_BR0_PRELIM   (CONFIG_SYS_FLASH_BASE \
230                                 | BR_PS_16      /* 16 bit port */ \
231                                 | BR_MS_GPCM    /* MSEL = GPCM */ \
232                                 | BR_V)         /* valid */
233 #define CONFIG_SYS_OR0_PRELIM   (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \
234                                 | OR_UPM_XAM \
235                                 | OR_GPCM_CSNT \
236                                 | OR_GPCM_ACS_DIV2 \
237                                 | OR_GPCM_XACS \
238                                 | OR_GPCM_SCY_15 \
239                                 | OR_GPCM_TRLX_SET \
240                                 | OR_GPCM_EHTR_SET \
241                                 | OR_GPCM_EAD)
242                                 /* 0xFE000FF7 */
243
244 #define CONFIG_SYS_MAX_FLASH_BANKS      1 /* number of banks */
245 #define CONFIG_SYS_MAX_FLASH_SECT       256 /* max sectors per device */
246
247 #undef CONFIG_SYS_FLASH_CHECKSUM
248 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000 /* Flash Erase Timeout (ms) */
249 #define CONFIG_SYS_FLASH_WRITE_TOUT     500 /* Flash Write Timeout (ms) */
250
251 /*
252  * BCSR on the Local Bus
253  */
254 #define CONFIG_SYS_BCSR         0xF8000000
255                                         /* Access window base at BCSR base */
256 #define CONFIG_SYS_LBLAWBAR1_PRELIM     CONFIG_SYS_BCSR
257 #define CONFIG_SYS_LBLAWAR1_PRELIM      (LBLAWAR_EN | LBLAWAR_32KB)
258
259 #define CONFIG_SYS_BR1_PRELIM   (CONFIG_SYS_BCSR \
260                                 | BR_PS_8 \
261                                 | BR_MS_GPCM \
262                                 | BR_V)
263                                 /* 0xF8000801 */
264 #define CONFIG_SYS_OR1_PRELIM   (OR_AM_32KB \
265                                 | OR_GPCM_XAM \
266                                 | OR_GPCM_CSNT \
267                                 | OR_GPCM_XACS \
268                                 | OR_GPCM_SCY_15 \
269                                 | OR_GPCM_TRLX_SET \
270                                 | OR_GPCM_EHTR_SET \
271                                 | OR_GPCM_EAD)
272                                 /* 0xFFFFE9F7 */
273
274 /*
275  * NAND Flash on the Local Bus
276  */
277 #define CONFIG_SYS_MAX_NAND_DEVICE      1
278 #define CONFIG_NAND_FSL_ELBC    1
279
280 #define CONFIG_SYS_NAND_BASE    0xE0600000
281 #define CONFIG_SYS_BR3_PRELIM   (CONFIG_SYS_NAND_BASE \
282                                 | BR_DECC_CHK_GEN       /* Use HW ECC */ \
283                                 | BR_PS_8               /* 8 bit port */ \
284                                 | BR_MS_FCM             /* MSEL = FCM */ \
285                                 | BR_V)                 /* valid */
286 #define CONFIG_SYS_OR3_PRELIM   (OR_AM_32KB \
287                                 | OR_FCM_BCTLD \
288                                 | OR_FCM_CST \
289                                 | OR_FCM_CHT \
290                                 | OR_FCM_SCY_1 \
291                                 | OR_FCM_RST \
292                                 | OR_FCM_TRLX \
293                                 | OR_FCM_EHTR)
294                                 /* 0xFFFF919E */
295
296 #define CONFIG_SYS_LBLAWBAR3_PRELIM     CONFIG_SYS_NAND_BASE
297 #define CONFIG_SYS_LBLAWAR3_PRELIM      (LBLAWAR_EN | LBLAWAR_32KB)
298
299 /*
300  * Serial Port
301  */
302 #define CONFIG_SYS_NS16550_SERIAL
303 #define CONFIG_SYS_NS16550_REG_SIZE     1
304 #define CONFIG_SYS_NS16550_CLK          get_bus_freq(0)
305
306 #define CONFIG_SYS_BAUDRATE_TABLE  \
307                 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
308
309 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500)
310 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600)
311
312 /* I2C */
313 #define CONFIG_SYS_I2C
314 #define CONFIG_SYS_I2C_FSL
315 #define CONFIG_SYS_FSL_I2C_SPEED        400000
316 #define CONFIG_SYS_FSL_I2C_SLAVE        0x7F
317 #define CONFIG_SYS_FSL_I2C_OFFSET       0x3000
318 #define CONFIG_SYS_I2C_NOPROBES         { {0, 0x51} }
319
320 /*
321  * Config on-board RTC
322  */
323 #define CONFIG_RTC_DS1374       /* use ds1374 rtc via i2c */
324 #define CONFIG_SYS_I2C_RTC_ADDR 0x68 /* at address 0x68 */
325
326 /*
327  * General PCI
328  * Addresses are mapped 1-1.
329  */
330 #define CONFIG_SYS_PCI_MEM_BASE         0x80000000
331 #define CONFIG_SYS_PCI_MEM_PHYS         CONFIG_SYS_PCI_MEM_BASE
332 #define CONFIG_SYS_PCI_MEM_SIZE         0x10000000 /* 256M */
333 #define CONFIG_SYS_PCI_MMIO_BASE        0x90000000
334 #define CONFIG_SYS_PCI_MMIO_PHYS        CONFIG_SYS_PCI_MMIO_BASE
335 #define CONFIG_SYS_PCI_MMIO_SIZE        0x10000000 /* 256M */
336 #define CONFIG_SYS_PCI_IO_BASE          0x00000000
337 #define CONFIG_SYS_PCI_IO_PHYS          0xE0300000
338 #define CONFIG_SYS_PCI_IO_SIZE          0x100000 /* 1M */
339
340 #define CONFIG_SYS_PCI_SLV_MEM_LOCAL    CONFIG_SYS_SDRAM_BASE
341 #define CONFIG_SYS_PCI_SLV_MEM_BUS      0x00000000
342 #define CONFIG_SYS_PCI_SLV_MEM_SIZE     0x80000000
343
344 #define CONFIG_SYS_PCIE1_BASE           0xA0000000
345 #define CONFIG_SYS_PCIE1_CFG_BASE       0xA0000000
346 #define CONFIG_SYS_PCIE1_CFG_SIZE       0x08000000
347 #define CONFIG_SYS_PCIE1_MEM_BASE       0xA8000000
348 #define CONFIG_SYS_PCIE1_MEM_PHYS       0xA8000000
349 #define CONFIG_SYS_PCIE1_MEM_SIZE       0x10000000
350 #define CONFIG_SYS_PCIE1_IO_BASE        0x00000000
351 #define CONFIG_SYS_PCIE1_IO_PHYS        0xB8000000
352 #define CONFIG_SYS_PCIE1_IO_SIZE        0x00800000
353
354 #define CONFIG_SYS_PCIE2_BASE           0xC0000000
355 #define CONFIG_SYS_PCIE2_CFG_BASE       0xC0000000
356 #define CONFIG_SYS_PCIE2_CFG_SIZE       0x08000000
357 #define CONFIG_SYS_PCIE2_MEM_BASE       0xC8000000
358 #define CONFIG_SYS_PCIE2_MEM_PHYS       0xC8000000
359 #define CONFIG_SYS_PCIE2_MEM_SIZE       0x10000000
360 #define CONFIG_SYS_PCIE2_IO_BASE        0x00000000
361 #define CONFIG_SYS_PCIE2_IO_PHYS        0xD8000000
362 #define CONFIG_SYS_PCIE2_IO_SIZE        0x00800000
363
364 #ifdef CONFIG_PCI
365 #define CONFIG_PCI_INDIRECT_BRIDGE
366 #ifndef __ASSEMBLY__
367 extern int board_pci_host_broken(void);
368 #endif
369 #define CONFIG_PCIE
370 #define CONFIG_PQ_MDS_PIB       1 /* PQ MDS Platform IO Board */
371
372 #define CONFIG_HAS_FSL_DR_USB   1 /* fixup device tree for the DR USB */
373 #define CONFIG_USB_EHCI_FSL
374 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
375
376 #undef CONFIG_EEPRO100
377 #undef CONFIG_PCI_SCAN_SHOW     /* show pci devices on startup */
378 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957   /* Freescale */
379 #endif /* CONFIG_PCI */
380
381 /*
382  * TSEC
383  */
384 #define CONFIG_SYS_TSEC1_OFFSET 0x24000
385 #define CONFIG_SYS_TSEC1        (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC1_OFFSET)
386 #define CONFIG_SYS_TSEC2_OFFSET 0x25000
387 #define CONFIG_SYS_TSEC2        (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC2_OFFSET)
388
389 /*
390  * TSEC ethernet configuration
391  */
392 #define CONFIG_MII              1 /* MII PHY management */
393 #define CONFIG_TSEC1            1
394 #define CONFIG_TSEC1_NAME       "eTSEC0"
395 #define CONFIG_TSEC2            1
396 #define CONFIG_TSEC2_NAME       "eTSEC1"
397 #define TSEC1_PHY_ADDR          2
398 #define TSEC2_PHY_ADDR          3
399 #define TSEC1_PHY_ADDR_SGMII    8
400 #define TSEC2_PHY_ADDR_SGMII    4
401 #define TSEC1_PHYIDX            0
402 #define TSEC2_PHYIDX            0
403 #define TSEC1_FLAGS             (TSEC_GIGABIT | TSEC_REDUCED)
404 #define TSEC2_FLAGS             (TSEC_GIGABIT | TSEC_REDUCED)
405
406 /* Options are: TSEC[0-1] */
407 #define CONFIG_ETHPRIME         "eTSEC1"
408
409 /* SERDES */
410 #define CONFIG_FSL_SERDES
411 #define CONFIG_FSL_SERDES1      0xe3000
412 #define CONFIG_FSL_SERDES2      0xe3100
413
414 /*
415  * SATA
416  */
417 #define CONFIG_SYS_SATA_MAX_DEVICE      2
418 #define CONFIG_SATA1
419 #define CONFIG_SYS_SATA1_OFFSET 0x18000
420 #define CONFIG_SYS_SATA1        (CONFIG_SYS_IMMR + CONFIG_SYS_SATA1_OFFSET)
421 #define CONFIG_SYS_SATA1_FLAGS  FLAGS_DMA
422 #define CONFIG_SATA2
423 #define CONFIG_SYS_SATA2_OFFSET 0x19000
424 #define CONFIG_SYS_SATA2        (CONFIG_SYS_IMMR + CONFIG_SYS_SATA2_OFFSET)
425 #define CONFIG_SYS_SATA2_FLAGS  FLAGS_DMA
426
427 #ifdef CONFIG_FSL_SATA
428 #define CONFIG_LBA48
429 #endif
430
431 /*
432  * Environment
433  */
434 #ifndef CONFIG_SYS_RAMBOOT
435         #define CONFIG_ENV_ADDR         \
436                         (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
437         #define CONFIG_ENV_SECT_SIZE    0x20000 /* 128K(one sector) for env */
438         #define CONFIG_ENV_SIZE         0x2000
439 #else
440         #define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE - 0x1000)
441         #define CONFIG_ENV_SIZE         0x2000
442 #endif
443
444 #define CONFIG_LOADS_ECHO       1       /* echo on for serial download */
445 #define CONFIG_SYS_LOADS_BAUD_CHANGE    1       /* allow baudrate change */
446
447 /*
448  * BOOTP options
449  */
450 #define CONFIG_BOOTP_BOOTFILESIZE
451
452 /*
453  * Command line configuration.
454  */
455
456 #undef CONFIG_WATCHDOG          /* watchdog disabled */
457
458 #ifdef CONFIG_MMC
459 #define CONFIG_FSL_ESDHC_PIN_MUX
460 #define CONFIG_SYS_FSL_ESDHC_ADDR       CONFIG_SYS_MPC83xx_ESDHC_ADDR
461 #endif
462
463 /*
464  * Miscellaneous configurable options
465  */
466 #define CONFIG_SYS_LOAD_ADDR            0x2000000 /* default load address */
467
468 /*
469  * For booting Linux, the board info and command line data
470  * have to be in the first 256 MB of memory, since this is
471  * the maximum mapped by the Linux kernel during initialization.
472  */
473 #define CONFIG_SYS_BOOTMAPSZ    (256 << 20) /* Initial Memory map for Linux */
474 #define CONFIG_SYS_BOOTM_LEN    (64 << 20)      /* Increase max gunzip size */
475
476 /*
477  * Core HID Setup
478  */
479 #define CONFIG_SYS_HID0_INIT    0x000000000
480 #define CONFIG_SYS_HID0_FINAL   (HID0_ENABLE_MACHINE_CHECK | \
481                                  HID0_ENABLE_INSTRUCTION_CACHE)
482 #define CONFIG_SYS_HID2         HID2_HBE
483
484 /*
485  * MMU Setup
486  */
487 #define CONFIG_HIGH_BATS        1       /* High BATs supported */
488
489 /* DDR: cache cacheable */
490 #define CONFIG_SYS_SDRAM_LOWER          CONFIG_SYS_SDRAM_BASE
491 #define CONFIG_SYS_SDRAM_UPPER          (CONFIG_SYS_SDRAM_BASE + 0x10000000)
492
493 #define CONFIG_SYS_IBAT0L       (CONFIG_SYS_SDRAM_LOWER \
494                                 | BATL_PP_RW \
495                                 | BATL_MEMCOHERENCE)
496 #define CONFIG_SYS_IBAT0U       (CONFIG_SYS_SDRAM_LOWER \
497                                 | BATU_BL_256M \
498                                 | BATU_VS \
499                                 | BATU_VP)
500 #define CONFIG_SYS_DBAT0L       CONFIG_SYS_IBAT0L
501 #define CONFIG_SYS_DBAT0U       CONFIG_SYS_IBAT0U
502
503 #define CONFIG_SYS_IBAT1L       (CONFIG_SYS_SDRAM_UPPER \
504                                 | BATL_PP_RW \
505                                 | BATL_MEMCOHERENCE)
506 #define CONFIG_SYS_IBAT1U       (CONFIG_SYS_SDRAM_UPPER \
507                                 | BATU_BL_256M \
508                                 | BATU_VS \
509                                 | BATU_VP)
510 #define CONFIG_SYS_DBAT1L       CONFIG_SYS_IBAT1L
511 #define CONFIG_SYS_DBAT1U       CONFIG_SYS_IBAT1U
512
513 /* IMMRBAR, PCI IO and NAND: cache-inhibit and guarded */
514 #define CONFIG_SYS_IBAT2L       (CONFIG_SYS_IMMR \
515                                 | BATL_PP_RW \
516                                 | BATL_CACHEINHIBIT \
517                                 | BATL_GUARDEDSTORAGE)
518 #define CONFIG_SYS_IBAT2U       (CONFIG_SYS_IMMR \
519                                 | BATU_BL_8M \
520                                 | BATU_VS \
521                                 | BATU_VP)
522 #define CONFIG_SYS_DBAT2L       CONFIG_SYS_IBAT2L
523 #define CONFIG_SYS_DBAT2U       CONFIG_SYS_IBAT2U
524
525 /* BCSR: cache-inhibit and guarded */
526 #define CONFIG_SYS_IBAT3L       (CONFIG_SYS_BCSR \
527                                 | BATL_PP_RW \
528                                 | BATL_CACHEINHIBIT \
529                                 | BATL_GUARDEDSTORAGE)
530 #define CONFIG_SYS_IBAT3U       (CONFIG_SYS_BCSR \
531                                 | BATU_BL_128K \
532                                 | BATU_VS \
533                                 | BATU_VP)
534 #define CONFIG_SYS_DBAT3L       CONFIG_SYS_IBAT3L
535 #define CONFIG_SYS_DBAT3U       CONFIG_SYS_IBAT3U
536
537 /* FLASH: icache cacheable, but dcache-inhibit and guarded */
538 #define CONFIG_SYS_IBAT4L       (CONFIG_SYS_FLASH_BASE \
539                                 | BATL_PP_RW \
540                                 | BATL_MEMCOHERENCE)
541 #define CONFIG_SYS_IBAT4U       (CONFIG_SYS_FLASH_BASE \
542                                 | BATU_BL_32M \
543                                 | BATU_VS \
544                                 | BATU_VP)
545 #define CONFIG_SYS_DBAT4L       (CONFIG_SYS_FLASH_BASE \
546                                 | BATL_PP_RW \
547                                 | BATL_CACHEINHIBIT \
548                                 | BATL_GUARDEDSTORAGE)
549 #define CONFIG_SYS_DBAT4U       CONFIG_SYS_IBAT4U
550
551 /* Stack in dcache: cacheable, no memory coherence */
552 #define CONFIG_SYS_IBAT5L       (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW)
553 #define CONFIG_SYS_IBAT5U       (CONFIG_SYS_INIT_RAM_ADDR \
554                                 | BATU_BL_128K \
555                                 | BATU_VS \
556                                 | BATU_VP)
557 #define CONFIG_SYS_DBAT5L       CONFIG_SYS_IBAT5L
558 #define CONFIG_SYS_DBAT5U       CONFIG_SYS_IBAT5U
559
560 #ifdef CONFIG_PCI
561 /* PCI MEM space: cacheable */
562 #define CONFIG_SYS_IBAT6L       (CONFIG_SYS_PCI_MEM_PHYS \
563                                 | BATL_PP_RW \
564                                 | BATL_MEMCOHERENCE)
565 #define CONFIG_SYS_IBAT6U       (CONFIG_SYS_PCI_MEM_PHYS \
566                                 | BATU_BL_256M \
567                                 | BATU_VS \
568                                 | BATU_VP)
569 #define CONFIG_SYS_DBAT6L       CONFIG_SYS_IBAT6L
570 #define CONFIG_SYS_DBAT6U       CONFIG_SYS_IBAT6U
571 /* PCI MMIO space: cache-inhibit and guarded */
572 #define CONFIG_SYS_IBAT7L       (CONFIG_SYS_PCI_MMIO_PHYS \
573                                 | BATL_PP_RW \
574                                 | BATL_CACHEINHIBIT \
575                                 | BATL_GUARDEDSTORAGE)
576 #define CONFIG_SYS_IBAT7U       (CONFIG_SYS_PCI_MMIO_PHYS \
577                                 | BATU_BL_256M \
578                                 | BATU_VS \
579                                 | BATU_VP)
580 #define CONFIG_SYS_DBAT7L       CONFIG_SYS_IBAT7L
581 #define CONFIG_SYS_DBAT7U       CONFIG_SYS_IBAT7U
582 #else
583 #define CONFIG_SYS_IBAT6L       (0)
584 #define CONFIG_SYS_IBAT6U       (0)
585 #define CONFIG_SYS_IBAT7L       (0)
586 #define CONFIG_SYS_IBAT7U       (0)
587 #define CONFIG_SYS_DBAT6L       CONFIG_SYS_IBAT6L
588 #define CONFIG_SYS_DBAT6U       CONFIG_SYS_IBAT6U
589 #define CONFIG_SYS_DBAT7L       CONFIG_SYS_IBAT7L
590 #define CONFIG_SYS_DBAT7U       CONFIG_SYS_IBAT7U
591 #endif
592
593 #if defined(CONFIG_CMD_KGDB)
594 #define CONFIG_KGDB_BAUDRATE    230400  /* speed of kgdb serial port */
595 #endif
596
597 /*
598  * Environment Configuration
599  */
600
601 #define CONFIG_ENV_OVERWRITE
602
603 #if defined(CONFIG_TSEC_ENET)
604 #define CONFIG_HAS_ETH0
605 #define CONFIG_HAS_ETH1
606 #endif
607
608 #define CONFIG_LOADADDR 800000  /* default location for tftp and bootm */
609
610 #define CONFIG_EXTRA_ENV_SETTINGS                                       \
611         "netdev=eth0\0"                                                 \
612         "consoledev=ttyS0\0"                                            \
613         "ramdiskaddr=1000000\0"                                         \
614         "ramdiskfile=ramfs.83xx\0"                                      \
615         "fdtaddr=780000\0"                                              \
616         "fdtfile=mpc8379_mds.dtb\0"                                     \
617         ""
618
619 #define CONFIG_NFSBOOTCOMMAND                                           \
620         "setenv bootargs root=/dev/nfs rw "                             \
621                 "nfsroot=$serverip:$rootpath "                          \
622                 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:"   \
623                                                         "$netdev:off "  \
624                 "console=$consoledev,$baudrate $othbootargs;"           \
625         "tftp $loadaddr $bootfile;"                                     \
626         "tftp $fdtaddr $fdtfile;"                                       \
627         "bootm $loadaddr - $fdtaddr"
628
629 #define CONFIG_RAMBOOTCOMMAND                                           \
630         "setenv bootargs root=/dev/ram rw "                             \
631                 "console=$consoledev,$baudrate $othbootargs;"           \
632         "tftp $ramdiskaddr $ramdiskfile;"                               \
633         "tftp $loadaddr $bootfile;"                                     \
634         "tftp $fdtaddr $fdtfile;"                                       \
635         "bootm $loadaddr $ramdiskaddr $fdtaddr"
636
637 #define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND
638
639 #endif  /* __CONFIG_H */