2 * Copyright 2004, 2011 Freescale Semiconductor.
4 * SPDX-License-Identifier: GPL-2.0+
8 * mpc8541cds board configuration file
10 * Please refer to doc/README.mpc85xxcds for more info.
16 #define CONFIG_DISPLAY_BOARDINFO
18 /* High Level Configuration Options */
19 #define CONFIG_BOOKE 1 /* BOOKE */
20 #define CONFIG_E500 1 /* BOOKE e500 family */
21 #define CONFIG_CPM2 1 /* has CPM2 */
22 #define CONFIG_MPC8541 1 /* MPC8541 specific */
23 #define CONFIG_MPC8541CDS 1 /* MPC8541CDS board specific */
25 #define CONFIG_SYS_TEXT_BASE 0xfff80000
28 #define CONFIG_PCI_INDIRECT_BRIDGE
29 #define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */
30 #define CONFIG_TSEC_ENET /* tsec ethernet support */
31 #define CONFIG_ENV_OVERWRITE
33 #define CONFIG_FSL_LAW 1 /* Use common FSL init code */
35 #define CONFIG_FSL_VIA
38 extern unsigned long get_clock_freq(void);
40 #define CONFIG_SYS_CLK_FREQ get_clock_freq() /* sysclk for MPC85xx */
43 * These can be toggled for performance analysis, otherwise use default.
45 #define CONFIG_L2_CACHE /* toggle L2 cache */
46 #define CONFIG_BTB /* toggle branch predition */
48 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */
49 #define CONFIG_SYS_MEMTEST_END 0x00400000
51 #define CONFIG_SYS_CCSRBAR 0xe0000000
52 #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
55 #define CONFIG_SYS_FSL_DDR1
56 #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/
57 #define CONFIG_DDR_SPD
58 #undef CONFIG_FSL_DDR_INTERACTIVE
60 #define CONFIG_MEM_INIT_VALUE 0xDeadBeef
62 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/
63 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
65 #define CONFIG_NUM_DDR_CONTROLLERS 1
66 #define CONFIG_DIMM_SLOTS_PER_CTLR 1
67 #define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
69 /* I2C addresses of SPD EEPROMs */
70 #define SPD_EEPROM_ADDRESS 0x51 /* CTLR 0 DIMM 0 */
73 * Make sure required options are set
75 #ifndef CONFIG_SPD_EEPROM
76 #error ("CONFIG_SPD_EEPROM is required by MPC85555CDS")
79 #undef CONFIG_CLOCKS_IN_MHZ
82 * Local Bus Definitions
86 * FLASH on the Local Bus
87 * Two banks, 8M each, using the CFI driver.
88 * Boot from BR0/OR0 bank at 0xff00_0000
89 * Alternate BR1/OR1 bank at 0xff80_0000
92 * Base address 0 = 0xff00_0000 = BR0[0:16] = 1111 1111 0000 0000 0
93 * Base address 1 = 0xff80_0000 = BR1[0:16] = 1111 1111 1000 0000 0
94 * Port Size = 16 bits = BRx[19:20] = 10
95 * Use GPCM = BRx[24:26] = 000
98 * 0 4 8 12 16 20 24 28
99 * 1111 1111 1000 0000 0001 0000 0000 0001 = ff801001 BR0
100 * 1111 1111 0000 0000 0001 0000 0000 0001 = ff001001 BR1
103 * Addr Mask = 8M = ORx[0:16] = 1111 1111 1000 0000 0
104 * Reserved ORx[17:18] = 11, confusion here?
106 * ACS = half cycle delay = ORx[21:22] = 11
107 * SCY = 6 = ORx[24:27] = 0110
108 * TRLX = use relaxed timing = ORx[29] = 1
109 * EAD = use external address latch delay = OR[31] = 1
111 * 0 4 8 12 16 20 24 28
112 * 1111 1111 1000 0000 0110 1110 0110 0101 = ff806e65 ORx
115 #define CONFIG_SYS_FLASH_BASE 0xff000000 /* start of FLASH 8M */
117 #define CONFIG_SYS_BR0_PRELIM 0xff801001
118 #define CONFIG_SYS_BR1_PRELIM 0xff001001
120 #define CONFIG_SYS_OR0_PRELIM 0xff806e65
121 #define CONFIG_SYS_OR1_PRELIM 0xff806e65
123 #define CONFIG_SYS_FLASH_BANKS_LIST {0xff800000, CONFIG_SYS_FLASH_BASE}
124 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */
125 #define CONFIG_SYS_MAX_FLASH_SECT 128 /* sectors per device */
126 #undef CONFIG_SYS_FLASH_CHECKSUM
127 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
128 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
130 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
132 #define CONFIG_FLASH_CFI_DRIVER
133 #define CONFIG_SYS_FLASH_CFI
134 #define CONFIG_SYS_FLASH_EMPTY_INFO
137 * SDRAM on the Local Bus
139 #define CONFIG_SYS_LBC_SDRAM_BASE 0xf0000000 /* Localbus SDRAM */
140 #define CONFIG_SYS_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */
143 * Base Register 2 and Option Register 2 configure SDRAM.
144 * The SDRAM base address, CONFIG_SYS_LBC_SDRAM_BASE, is 0xf0000000.
147 * Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0
148 * port-size = 32-bits = BR2[19:20] = 11
149 * no parity checking = BR2[21:22] = 00
150 * SDRAM for MSEL = BR2[24:26] = 011
153 * 0 4 8 12 16 20 24 28
154 * 1111 0000 0000 0000 0001 1000 0110 0001 = f0001861
156 * FIXME: CONFIG_SYS_LBC_SDRAM_BASE should be masked and OR'ed into
157 * FIXME: the top 17 bits of BR2.
160 #define CONFIG_SYS_BR2_PRELIM 0xf0001861
163 * The SDRAM size in MB, CONFIG_SYS_LBC_SDRAM_SIZE, is 64.
166 * 64MB mask for AM, OR2[0:7] = 1111 1100
167 * XAM, OR2[17:18] = 11
168 * 9 columns OR2[19-21] = 010
169 * 13 rows OR2[23-25] = 100
170 * EAD set for extra time OR[31] = 1
172 * 0 4 8 12 16 20 24 28
173 * 1111 1100 0000 0000 0110 1001 0000 0001 = fc006901
176 #define CONFIG_SYS_OR2_PRELIM 0xfc006901
178 #define CONFIG_SYS_LBC_LCRR 0x00030004 /* LB clock ratio reg */
179 #define CONFIG_SYS_LBC_LBCR 0x00000000 /* LB config reg */
180 #define CONFIG_SYS_LBC_LSRT 0x20000000 /* LB sdram refresh timer */
181 #define CONFIG_SYS_LBC_MRTPR 0x00000000 /* LB refresh timer prescal*/
184 * Common settings for all Local Bus SDRAM commands.
185 * At run time, either BSMA1516 (for CPU 1.1)
186 * or BSMA1617 (for CPU 1.0) (old)
189 #define CONFIG_SYS_LBC_LSDMR_COMMON ( LSDMR_RFCR16 \
199 * The CADMUS registers are connected to CS3 on CDS.
200 * The new memory map places CADMUS at 0xf8000000.
203 * Base address of 0xf8000000 = BR[0:16] = 1111 1000 0000 0000 0
204 * port-size = 8-bits = BR[19:20] = 01
205 * no parity checking = BR[21:22] = 00
206 * GPMC for MSEL = BR[24:26] = 000
209 * 0 4 8 12 16 20 24 28
210 * 1111 1000 0000 0000 0000 1000 0000 0001 = f8000801
213 * 1 MB mask for AM, OR[0:16] = 1111 1111 1111 0000 0
214 * disable buffer ctrl OR[19] = 0
218 * SCY 15 wait states OR[24:27] = 1111 max is suboptimal but safe
222 * EAD extra time OR[31] = 1
224 * 0 4 8 12 16 20 24 28
225 * 1111 1111 1111 0000 0000 1111 1111 0111 = fff00ff7
228 #define CONFIG_FSL_CADMUS
230 #define CADMUS_BASE_ADDR 0xf8000000
231 #define CONFIG_SYS_BR3_PRELIM 0xf8000801
232 #define CONFIG_SYS_OR3_PRELIM 0xfff00ff7
234 #define CONFIG_SYS_INIT_RAM_LOCK 1
235 #define CONFIG_SYS_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */
236 #define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in RAM */
238 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
239 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
241 #define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */
242 #define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserved for malloc */
245 #define CONFIG_CONS_INDEX 2
246 #define CONFIG_SYS_NS16550_SERIAL
247 #define CONFIG_SYS_NS16550_REG_SIZE 1
248 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
250 #define CONFIG_SYS_BAUDRATE_TABLE \
251 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
253 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
254 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
259 #define CONFIG_SYS_I2C
260 #define CONFIG_SYS_I2C_FSL
261 #define CONFIG_SYS_FSL_I2C_SPEED 400000
262 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
263 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
264 #define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} }
267 #define CONFIG_ID_EEPROM
268 #define CONFIG_SYS_I2C_EEPROM_CCID
269 #define CONFIG_SYS_ID_EEPROM
270 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
271 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
275 * Memory space is mapped 1-1, but I/O space must start from 0.
277 #define CONFIG_SYS_PCI1_MEM_VIRT 0x80000000
278 #define CONFIG_SYS_PCI1_MEM_BUS 0x80000000
279 #define CONFIG_SYS_PCI1_MEM_PHYS 0x80000000
280 #define CONFIG_SYS_PCI1_MEM_SIZE 0x20000000 /* 512M */
281 #define CONFIG_SYS_PCI1_IO_VIRT 0xe2000000
282 #define CONFIG_SYS_PCI1_IO_BUS 0x00000000
283 #define CONFIG_SYS_PCI1_IO_PHYS 0xe2000000
284 #define CONFIG_SYS_PCI1_IO_SIZE 0x100000 /* 1M */
286 #define CONFIG_SYS_PCI2_MEM_VIRT 0xa0000000
287 #define CONFIG_SYS_PCI2_MEM_BUS 0xa0000000
288 #define CONFIG_SYS_PCI2_MEM_PHYS 0xa0000000
289 #define CONFIG_SYS_PCI2_MEM_SIZE 0x20000000 /* 512M */
290 #define CONFIG_SYS_PCI2_IO_VIRT 0xe2100000
291 #define CONFIG_SYS_PCI2_IO_BUS 0x00000000
292 #define CONFIG_SYS_PCI2_IO_PHYS 0xe2100000
293 #define CONFIG_SYS_PCI2_IO_SIZE 0x100000 /* 1M */
303 #if defined(CONFIG_PCI)
305 #define CONFIG_MPC85XX_PCI2
306 #define CONFIG_PCI_PNP /* do pci plug-and-play */
308 #undef CONFIG_EEPRO100
311 #undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
312 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */
314 #endif /* CONFIG_PCI */
316 #if defined(CONFIG_TSEC_ENET)
318 #define CONFIG_MII 1 /* MII PHY management */
319 #define CONFIG_TSEC1 1
320 #define CONFIG_TSEC1_NAME "TSEC0"
321 #define CONFIG_TSEC2 1
322 #define CONFIG_TSEC2_NAME "TSEC1"
323 #define TSEC1_PHY_ADDR 0
324 #define TSEC2_PHY_ADDR 1
325 #define TSEC1_PHYIDX 0
326 #define TSEC2_PHYIDX 0
327 #define TSEC1_FLAGS TSEC_GIGABIT
328 #define TSEC2_FLAGS TSEC_GIGABIT
330 /* Options are: TSEC[0-1] */
331 #define CONFIG_ETHPRIME "TSEC0"
333 #endif /* CONFIG_TSEC_ENET */
338 #define CONFIG_ENV_IS_IN_FLASH 1
339 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + 0x40000)
340 #define CONFIG_ENV_SECT_SIZE 0x40000 /* 256K(one sector) for env */
341 #define CONFIG_ENV_SIZE 0x2000
343 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
344 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
349 #define CONFIG_BOOTP_BOOTFILESIZE
350 #define CONFIG_BOOTP_BOOTPATH
351 #define CONFIG_BOOTP_GATEWAY
352 #define CONFIG_BOOTP_HOSTNAME
355 * Command line configuration.
357 #define CONFIG_CMD_IRQ
358 #define CONFIG_CMD_REGINFO
360 #if defined(CONFIG_PCI)
361 #define CONFIG_CMD_PCI
364 #undef CONFIG_WATCHDOG /* watchdog disabled */
367 * Miscellaneous configurable options
369 #define CONFIG_SYS_LONGHELP /* undef to save memory */
370 #define CONFIG_CMDLINE_EDITING /* Command-line editing */
371 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */
372 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
373 #if defined(CONFIG_CMD_KGDB)
374 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
376 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
378 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
379 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */
380 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
383 * For booting Linux, the board info and command line data
384 * have to be in the first 64 MB of memory, since this is
385 * the maximum mapped by the Linux kernel during initialization.
387 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux*/
388 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
390 #if defined(CONFIG_CMD_KGDB)
391 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
395 * Environment Configuration
398 /* The mac addresses for all ethernet interface */
399 #if defined(CONFIG_TSEC_ENET)
400 #define CONFIG_HAS_ETH0
401 #define CONFIG_HAS_ETH1
402 #define CONFIG_HAS_ETH2
405 #define CONFIG_IPADDR 192.168.1.253
407 #define CONFIG_HOSTNAME unknown
408 #define CONFIG_ROOTPATH "/nfsroot"
409 #define CONFIG_BOOTFILE "your.uImage"
411 #define CONFIG_SERVERIP 192.168.1.1
412 #define CONFIG_GATEWAYIP 192.168.1.1
413 #define CONFIG_NETMASK 255.255.255.0
415 #define CONFIG_LOADADDR 200000 /*default location for tftp and bootm*/
417 #undef CONFIG_BOOTARGS /* the boot command will set bootargs*/
419 #define CONFIG_BAUDRATE 115200
421 #define CONFIG_EXTRA_ENV_SETTINGS \
423 "consoledev=ttyS1\0" \
424 "ramdiskaddr=600000\0" \
425 "ramdiskfile=your.ramdisk.u-boot\0" \
427 "fdtfile=your.fdt.dtb\0"
429 #define CONFIG_NFSBOOTCOMMAND \
430 "setenv bootargs root=/dev/nfs rw " \
431 "nfsroot=$serverip:$rootpath " \
432 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
433 "console=$consoledev,$baudrate $othbootargs;" \
434 "tftp $loadaddr $bootfile;" \
435 "tftp $fdtaddr $fdtfile;" \
436 "bootm $loadaddr - $fdtaddr"
438 #define CONFIG_RAMBOOTCOMMAND \
439 "setenv bootargs root=/dev/ram rw " \
440 "console=$consoledev,$baudrate $othbootargs;" \
441 "tftp $ramdiskaddr $ramdiskfile;" \
442 "tftp $loadaddr $bootfile;" \
443 "bootm $loadaddr $ramdiskaddr"
445 #define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND
447 #endif /* __CONFIG_H */