2 * Copyright 2007, 2010-2011 Freescale Semiconductor, Inc.
4 * SPDX-License-Identifier: GPL-2.0+
8 * mpc8544ds board configuration file
14 /* High Level Configuration Options */
15 #define CONFIG_BOOKE 1 /* BOOKE */
16 #define CONFIG_E500 1 /* BOOKE e500 family */
18 #ifndef CONFIG_SYS_TEXT_BASE
19 #define CONFIG_SYS_TEXT_BASE 0xfff80000
22 #define CONFIG_PCI1 1 /* PCI controller 1 */
23 #define CONFIG_PCIE1 1 /* PCIE controller 1 (slot 1) */
24 #define CONFIG_PCIE2 1 /* PCIE controller 2 (slot 2) */
25 #define CONFIG_PCIE3 1 /* PCIE controller 3 (ULI bridge) */
26 #define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */
27 #define CONFIG_PCI_INDIRECT_BRIDGE 1 /* indirect PCI bridge support */
28 #define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */
29 #define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */
31 #define CONFIG_TSEC_ENET /* tsec ethernet support */
32 #define CONFIG_ENV_OVERWRITE
33 #define CONFIG_INTERRUPTS /* enable pci, srio, ddr interrupts */
36 extern unsigned long get_board_sys_clk(unsigned long dummy);
38 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk(0) /* sysclk for MPC85xx */
41 * These can be toggled for performance analysis, otherwise use default.
43 #define CONFIG_L2_CACHE /* toggle L2 cache */
44 #define CONFIG_BTB /* toggle branch predition */
47 * Only possible on E500 Version 2 or newer cores.
49 #define CONFIG_ENABLE_36BIT_PHYS 1
51 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */
52 #define CONFIG_SYS_MEMTEST_END 0x00400000
53 #define CONFIG_PANIC_HANG /* do not reset board on panic */
55 #define CONFIG_SYS_CCSRBAR 0xe0000000
56 #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
59 #define CONFIG_SYS_FSL_DDR2
60 #undef CONFIG_FSL_DDR_INTERACTIVE
61 #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */
62 #define CONFIG_DDR_SPD
64 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */
65 #define CONFIG_MEM_INIT_VALUE 0xDeadBeef
67 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
68 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
69 #define CONFIG_VERY_BIG_RAM
71 #define CONFIG_NUM_DDR_CONTROLLERS 1
72 #define CONFIG_DIMM_SLOTS_PER_CTLR 1
73 #define CONFIG_CHIP_SELECTS_PER_CTRL 2
75 /* I2C addresses of SPD EEPROMs */
76 #define SPD_EEPROM_ADDRESS 0x51 /* DDR DIMM */
78 /* Make sure required options are set */
79 #ifndef CONFIG_SPD_EEPROM
80 #error ("CONFIG_SPD_EEPROM is required")
83 #undef CONFIG_CLOCKS_IN_MHZ
88 * 0x0000_0000 0x7fff_ffff DDR 2G Cacheable
90 * 0x8000_0000 0xbfff_ffff PCI Express Mem 1G non-cacheable
92 * 0xc000_0000 0xdfff_ffff PCI 512M non-cacheable
94 * 0xe000_0000 0xe00f_ffff CCSR 1M non-cacheable
95 * 0xe100_0000 0xe3ff_ffff PCI IO range 4M non-cacheable
99 * 0xf000_0000 0xf3ff_ffff SDRAM 64M Cacheable
100 * 0xf401_0000 0xf401_3fff L1 for stack 4K Cacheable TLB0
102 * Localbus non-cacheable
104 * 0xf800_0000 0xf80f_ffff NVRAM/CADMUS (*) 1M non-cacheable
105 * 0xff00_0000 0xff7f_ffff FLASH (2nd bank) 8M non-cacheable
106 * 0xff80_0000 0xffff_ffff FLASH (boot bank) 8M non-cacheable
111 * Local Bus Definitions
113 #define CONFIG_SYS_BOOT_BLOCK 0xfc000000 /* boot TLB */
115 #define CONFIG_SYS_FLASH_BASE 0xff800000 /* start of FLASH 8M */
117 #define CONFIG_SYS_BR0_PRELIM 0xff801001
118 #define CONFIG_SYS_BR1_PRELIM 0xfe801001
120 #define CONFIG_SYS_OR0_PRELIM 0xff806e65
121 #define CONFIG_SYS_OR1_PRELIM 0xff806e65
123 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE}
125 #define CONFIG_SYS_FLASH_QUIET_TEST
126 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
127 #define CONFIG_SYS_MAX_FLASH_SECT 128 /* sectors per device */
128 #undef CONFIG_SYS_FLASH_CHECKSUM
129 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
130 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
131 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
133 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
135 #define CONFIG_FLASH_CFI_DRIVER
136 #define CONFIG_SYS_FLASH_CFI
137 #define CONFIG_SYS_FLASH_EMPTY_INFO
139 #define CONFIG_SYS_LBC_NONCACHE_BASE 0xf8000000
141 #define CONFIG_SYS_BR2_PRELIM 0xf8201001 /* port size 16bit */
142 #define CONFIG_SYS_OR2_PRELIM 0xfff06ff7 /* 1MB Compact Flash area*/
144 #define CONFIG_SYS_BR3_PRELIM 0xf8100801 /* port size 8bit */
145 #define CONFIG_SYS_OR3_PRELIM 0xfff06ff7 /* 1MB PIXIS area*/
147 #define CONFIG_FSL_PIXIS 1 /* use common PIXIS code */
148 #define PIXIS_BASE 0xf8100000 /* PIXIS registers */
149 #define PIXIS_ID 0x0 /* Board ID at offset 0 */
150 #define PIXIS_VER 0x1 /* Board version at offset 1 */
151 #define PIXIS_PVER 0x2 /* PIXIS FPGA version at offset 2 */
152 #define PIXIS_RST 0x4 /* PIXIS Reset Control register */
153 #define PIXIS_AUX 0x6 /* PIXIS Auxiliary register; Scratch
155 #define PIXIS_SPD 0x7 /* Register for SYSCLK speed */
156 #define PIXIS_VCTL 0x10 /* VELA Control Register */
157 #define PIXIS_VCFGEN0 0x12 /* VELA Config Enable 0 */
158 #define PIXIS_VCFGEN1 0x13 /* VELA Config Enable 1 */
159 #define PIXIS_VBOOT 0x16 /* VELA VBOOT Register */
160 #define PIXIS_VBOOT_FMAP 0x80 /* VBOOT - CFG_FLASHMAP */
161 #define PIXIS_VBOOT_FBANK 0x40 /* VBOOT - CFG_FLASHBANK */
162 #define PIXIS_VSPEED0 0x17 /* VELA VSpeed 0 */
163 #define PIXIS_VSPEED1 0x18 /* VELA VSpeed 1 */
164 #define PIXIS_VCLKH 0x19 /* VELA VCLKH register */
165 #define PIXIS_VCLKL 0x1A /* VELA VCLKL register */
166 #define PIXIS_VSPEED2 0x1d /* VELA VSpeed 2 */
167 #define CONFIG_SYS_PIXIS_VBOOT_MASK 0x40 /* Reset altbank mask*/
168 #define PIXIS_VSPEED2_TSEC1SER 0x2
169 #define PIXIS_VSPEED2_TSEC3SER 0x1
170 #define PIXIS_VCFGEN1_TSEC1SER 0x20
171 #define PIXIS_VCFGEN1_TSEC3SER 0x40
172 #define PIXIS_VSPEED2_MASK (PIXIS_VSPEED2_TSEC1SER|PIXIS_VSPEED2_TSEC3SER)
173 #define PIXIS_VCFGEN1_MASK (PIXIS_VCFGEN1_TSEC1SER|PIXIS_VCFGEN1_TSEC3SER)
175 #define CONFIG_SYS_INIT_RAM_LOCK 1
176 #define CONFIG_SYS_INIT_RAM_ADDR 0xf4010000 /* Initial L1 address */
177 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 /* Size of used area in RAM */
179 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
180 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
182 #define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */
183 #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */
185 /* Serial Port - controlled on board with jumper J8
189 #define CONFIG_CONS_INDEX 1
190 #define CONFIG_SYS_NS16550_SERIAL
191 #define CONFIG_SYS_NS16550_REG_SIZE 1
192 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
194 #define CONFIG_SYS_BAUDRATE_TABLE \
195 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
197 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
198 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
201 #define CONFIG_SYS_I2C
202 #define CONFIG_SYS_I2C_FSL
203 #define CONFIG_SYS_FSL_I2C_SPEED 400000
204 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
205 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3100
206 #define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} }
207 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
211 * Memory space is mapped 1-1, but I/O space must start from 0.
213 #define CONFIG_SYS_PCIE_VIRT 0x80000000 /* 1G PCIE TLB */
214 #define CONFIG_SYS_PCIE_PHYS 0x80000000 /* 1G PCIE TLB */
215 #define CONFIG_SYS_PCI_VIRT 0xc0000000 /* 512M PCI TLB */
216 #define CONFIG_SYS_PCI_PHYS 0xc0000000 /* 512M PCI TLB */
218 #define CONFIG_SYS_PCI1_MEM_VIRT 0xc0000000
219 #define CONFIG_SYS_PCI1_MEM_BUS 0xc0000000
220 #define CONFIG_SYS_PCI1_MEM_PHYS 0xc0000000
221 #define CONFIG_SYS_PCI1_MEM_SIZE 0x20000000 /* 512M */
222 #define CONFIG_SYS_PCI1_IO_VIRT 0xe1000000
223 #define CONFIG_SYS_PCI1_IO_BUS 0x00000000
224 #define CONFIG_SYS_PCI1_IO_PHYS 0xe1000000
225 #define CONFIG_SYS_PCI1_IO_SIZE 0x00010000 /* 64k */
227 /* controller 2, Slot 1, tgtid 1, Base address 9000 */
228 #define CONFIG_SYS_PCIE2_NAME "Slot 1"
229 #define CONFIG_SYS_PCIE2_MEM_VIRT 0x80000000
230 #define CONFIG_SYS_PCIE2_MEM_BUS 0x80000000
231 #define CONFIG_SYS_PCIE2_MEM_PHYS 0x80000000
232 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */
233 #define CONFIG_SYS_PCIE2_IO_VIRT 0xe1010000
234 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
235 #define CONFIG_SYS_PCIE2_IO_PHYS 0xe1010000
236 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */
238 /* controller 1, Slot 2,tgtid 2, Base address a000 */
239 #define CONFIG_SYS_PCIE1_NAME "Slot 2"
240 #define CONFIG_SYS_PCIE1_MEM_VIRT 0xa0000000
241 #define CONFIG_SYS_PCIE1_MEM_BUS 0xa0000000
242 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xa0000000
243 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000 /* 256M */
244 #define CONFIG_SYS_PCIE1_IO_VIRT 0xe1020000
245 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
246 #define CONFIG_SYS_PCIE1_IO_PHYS 0xe1020000
247 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
249 /* controller 3, direct to uli, tgtid 3, Base address b000 */
250 #define CONFIG_SYS_PCIE3_NAME "ULI"
251 #define CONFIG_SYS_PCIE3_MEM_VIRT 0xb0000000
252 #define CONFIG_SYS_PCIE3_MEM_BUS 0xb0000000
253 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xb0000000
254 #define CONFIG_SYS_PCIE3_MEM_SIZE 0x00100000 /* 1M */
255 #define CONFIG_SYS_PCIE3_IO_VIRT 0xb0100000 /* reuse mem LAW */
256 #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000
257 #define CONFIG_SYS_PCIE3_IO_PHYS 0xb0100000 /* reuse mem LAW */
258 #define CONFIG_SYS_PCIE3_IO_SIZE 0x00100000 /* 1M */
259 #define CONFIG_SYS_PCIE3_MEM_VIRT2 0xb0200000
260 #define CONFIG_SYS_PCIE3_MEM_BUS2 0xb0200000
261 #define CONFIG_SYS_PCIE3_MEM_PHYS2 0xb0200000
262 #define CONFIG_SYS_PCIE3_MEM_SIZE2 0x00200000 /* 1M */
264 #if defined(CONFIG_PCI)
266 /*PCIE video card used*/
267 #define VIDEO_IO_OFFSET CONFIG_SYS_PCIE2_IO_VIRT
269 /*PCI video card used*/
270 /*#define VIDEO_IO_OFFSET CONFIG_SYS_PCI1_IO_VIRT*/
274 #if defined(CONFIG_VIDEO)
275 #define CONFIG_BIOSEMU
276 #define CONFIG_ATI_RADEON_FB
277 #define CONFIG_VIDEO_LOGO
278 #define CONFIG_SYS_ISA_IO_BASE_ADDRESS VIDEO_IO_OFFSET
281 #undef CONFIG_EEPRO100
284 #ifndef CONFIG_PCI_PNP
285 #define PCI_ENET0_IOADDR CONFIG_SYS_PCI1_IO_BUS
286 #define PCI_ENET0_MEMADDR CONFIG_SYS_PCI1_IO_BUS
287 #define PCI_IDSEL_NUMBER 0x11 /* IDSEL = AD11 */
290 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
291 #define CONFIG_DOS_PARTITION
292 #define CONFIG_SCSI_AHCI
294 #ifdef CONFIG_SCSI_AHCI
295 #define CONFIG_LIBATA
296 #define CONFIG_SATA_ULI5288
297 #define CONFIG_SYS_SCSI_MAX_SCSI_ID 4
298 #define CONFIG_SYS_SCSI_MAX_LUN 1
299 #define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * CONFIG_SYS_SCSI_MAX_LUN)
300 #define CONFIG_SYS_SCSI_MAXDEVICE CONFIG_SYS_SCSI_MAX_DEVICE
303 #endif /* CONFIG_PCI */
305 #if defined(CONFIG_TSEC_ENET)
307 #define CONFIG_MII 1 /* MII PHY management */
308 #define CONFIG_MII_DEFAULT_TSEC 1 /* Allow unregistered phys */
309 #define CONFIG_TSEC1 1
310 #define CONFIG_TSEC1_NAME "eTSEC1"
311 #define CONFIG_TSEC3 1
312 #define CONFIG_TSEC3_NAME "eTSEC3"
314 #define CONFIG_PIXIS_SGMII_CMD
315 #define CONFIG_FSL_SGMII_RISER 1
316 #define SGMII_RISER_PHY_OFFSET 0x1c
318 #define TSEC1_PHY_ADDR 0
319 #define TSEC3_PHY_ADDR 1
321 #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
322 #define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
324 #define TSEC1_PHYIDX 0
325 #define TSEC3_PHYIDX 0
327 #define CONFIG_ETHPRIME "eTSEC1"
329 #define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */
330 #endif /* CONFIG_TSEC_ENET */
335 #define CONFIG_ENV_IS_IN_FLASH 1
336 #if CONFIG_SYS_MONITOR_BASE > 0xfff80000
337 #define CONFIG_ENV_ADDR 0xfff80000
339 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + 0x70000)
341 #define CONFIG_ENV_SIZE 0x2000
342 #define CONFIG_ENV_SECT_SIZE 0x10000 /* 64K (one sector) */
344 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
345 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
350 #define CONFIG_BOOTP_BOOTFILESIZE
351 #define CONFIG_BOOTP_BOOTPATH
352 #define CONFIG_BOOTP_GATEWAY
353 #define CONFIG_BOOTP_HOSTNAME
356 * Command line configuration.
358 #define CONFIG_CMD_IRQ
359 #define CONFIG_CMD_REGINFO
361 #if defined(CONFIG_PCI)
362 #define CONFIG_CMD_PCI
369 #define CONFIG_USB_EHCI
371 #ifdef CONFIG_USB_EHCI
372 #define CONFIG_USB_EHCI_PCI
373 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
374 #define CONFIG_PCI_EHCI_DEVICE 0
377 #undef CONFIG_WATCHDOG /* watchdog disabled */
380 * Miscellaneous configurable options
382 #define CONFIG_SYS_LONGHELP /* undef to save memory */
383 #define CONFIG_CMDLINE_EDITING /* Command-line editing */
384 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */
385 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
386 #if defined(CONFIG_CMD_KGDB)
387 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
389 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
391 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
392 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */
393 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
396 * For booting Linux, the board info and command line data
397 * have to be in the first 64 MB of memory, since this is
398 * the maximum mapped by the Linux kernel during initialization.
400 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux*/
401 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
403 #if defined(CONFIG_CMD_KGDB)
404 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
408 * Environment Configuration
411 /* The mac addresses for all ethernet interface */
412 #if defined(CONFIG_TSEC_ENET)
413 #define CONFIG_HAS_ETH0
414 #define CONFIG_HAS_ETH1
417 #define CONFIG_IPADDR 192.168.1.251
419 #define CONFIG_HOSTNAME 8544ds_unknown
420 #define CONFIG_ROOTPATH "/nfs/mpc85xx"
421 #define CONFIG_BOOTFILE "8544ds/uImage.uboot"
422 #define CONFIG_UBOOTPATH 8544ds/u-boot.bin /* TFTP server */
424 #define CONFIG_SERVERIP 192.168.1.1
425 #define CONFIG_GATEWAYIP 192.168.1.1
426 #define CONFIG_NETMASK 255.255.0.0
428 #define CONFIG_LOADADDR 1000000 /*default location for tftp and bootm*/
430 #undef CONFIG_BOOTARGS /* the boot command will set bootargs*/
432 #define CONFIG_BAUDRATE 115200
434 #define CONFIG_EXTRA_ENV_SETTINGS \
436 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
437 "tftpflash=tftpboot $loadaddr $uboot; " \
438 "protect off " __stringify(CONFIG_SYS_TEXT_BASE) \
440 "erase " __stringify(CONFIG_SYS_TEXT_BASE) \
442 "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \
444 "protect on " __stringify(CONFIG_SYS_TEXT_BASE) \
446 "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \
448 "consoledev=ttyS0\0" \
449 "ramdiskaddr=2000000\0" \
450 "ramdiskfile=8544ds/ramdisk.uboot\0" \
451 "fdtaddr=1e00000\0" \
452 "fdtfile=8544ds/mpc8544ds.dtb\0" \
455 #define CONFIG_NFSBOOTCOMMAND \
456 "setenv bootargs root=/dev/nfs rw " \
457 "nfsroot=$serverip:$rootpath " \
458 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
459 "console=$consoledev,$baudrate $othbootargs;" \
460 "tftp $loadaddr $bootfile;" \
461 "tftp $fdtaddr $fdtfile;" \
462 "bootm $loadaddr - $fdtaddr"
464 #define CONFIG_RAMBOOTCOMMAND \
465 "setenv bootargs root=/dev/ram rw " \
466 "console=$consoledev,$baudrate $othbootargs;" \
467 "tftp $ramdiskaddr $ramdiskfile;" \
468 "tftp $loadaddr $bootfile;" \
469 "tftp $fdtaddr $fdtfile;" \
470 "bootm $loadaddr $ramdiskaddr $fdtaddr"
472 #define CONFIG_BOOTCOMMAND \
473 "setenv bootargs root=/dev/$bdev rw " \
474 "console=$consoledev,$baudrate $othbootargs;" \
475 "tftp $loadaddr $bootfile;" \
476 "tftp $fdtaddr $fdtfile;" \
477 "bootm $loadaddr - $fdtaddr"
479 #endif /* __CONFIG_H */