2 * Copyright 2004, 2011 Freescale Semiconductor.
3 * (C) Copyright 2002,2003 Motorola,Inc.
4 * Xianghua Xiao <X.Xiao@motorola.com>
6 * SPDX-License-Identifier: GPL-2.0+
10 * mpc8560ads board configuration file
12 * Please refer to doc/README.mpc85xx for more info.
14 * Make sure you change the MAC address and other network params first,
15 * search for CONFIG_SERVERIP, etc. in this file.
21 /* High Level Configuration Options */
22 #define CONFIG_CPM2 1 /* has CPM2 */
25 * default CCARBAR is at 0xff700000
26 * assume U-Boot is less than 0.5MB
28 #define CONFIG_SYS_TEXT_BASE 0xfff80000
30 #define CONFIG_PCI_INDIRECT_BRIDGE
31 #define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */
32 #define CONFIG_TSEC_ENET /* tsec ethernet support */
33 #undef CONFIG_ETHER_ON_FCC /* cpm FCC ethernet support */
34 #define CONFIG_ENV_OVERWRITE
35 #define CONFIG_RESET_PHY_R 1 /* Call reset_phy() */
40 * Two valid values are:
44 * Most PCI cards are still 33Mhz, so in the presence of PCI, 33MHz
45 * is likely the desired value here, so that is now the default.
46 * The board, however, can run at 66MHz. In any event, this value
47 * must match the settings of some switches. Details can be found
48 * in the README.mpc85xxads.
51 #ifndef CONFIG_SYS_CLK_FREQ
52 #define CONFIG_SYS_CLK_FREQ 33000000
56 * These can be toggled for performance analysis, otherwise use default.
58 #define CONFIG_L2_CACHE /* toggle L2 cache */
59 #define CONFIG_BTB /* toggle branch predition */
61 #define CONFIG_SYS_INIT_DBCR DBCR_IDM /* Enable Debug Exceptions */
63 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest region */
64 #define CONFIG_SYS_MEMTEST_END 0x00400000
66 #define CONFIG_SYS_CCSRBAR 0xe0000000
67 #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
70 #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/
71 #define CONFIG_DDR_SPD
72 #undef CONFIG_FSL_DDR_INTERACTIVE
74 #define CONFIG_MEM_INIT_VALUE 0xDeadBeef
76 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/
77 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
79 #define CONFIG_NUM_DDR_CONTROLLERS 1
80 #define CONFIG_DIMM_SLOTS_PER_CTLR 1
81 #define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
83 /* I2C addresses of SPD EEPROMs */
84 #define SPD_EEPROM_ADDRESS 0x51 /* CTLR 0 DIMM 0 */
86 /* These are used when DDR doesn't use SPD. */
87 #define CONFIG_SYS_SDRAM_SIZE 128 /* DDR is 128MB */
88 #define CONFIG_SYS_DDR_CS0_BNDS 0x00000007 /* 0-128MB */
89 #define CONFIG_SYS_DDR_CS0_CONFIG 0x80000002
90 #define CONFIG_SYS_DDR_TIMING_1 0x37344321
91 #define CONFIG_SYS_DDR_TIMING_2 0x00000800 /* P9-45,may need tuning */
92 #define CONFIG_SYS_DDR_CONTROL 0xc2000000 /* unbuffered,no DYN_PWR */
93 #define CONFIG_SYS_DDR_MODE 0x00000062 /* DLL,normal,seq,4/2.5 */
94 #define CONFIG_SYS_DDR_INTERVAL 0x05200100 /* autocharge,no open page */
97 * SDRAM on the Local Bus
99 #define CONFIG_SYS_LBC_SDRAM_BASE 0xf0000000 /* Localbus SDRAM */
100 #define CONFIG_SYS_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */
102 #define CONFIG_SYS_FLASH_BASE 0xff000000 /* start of FLASH 16M */
103 #define CONFIG_SYS_BR0_PRELIM 0xff001801 /* port size 32bit */
105 #define CONFIG_SYS_OR0_PRELIM 0xff006ff7 /* 16MB Flash */
106 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
107 #define CONFIG_SYS_MAX_FLASH_SECT 64 /* sectors per device */
108 #undef CONFIG_SYS_FLASH_CHECKSUM
109 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
110 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
112 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
114 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
115 #define CONFIG_SYS_RAMBOOT
117 #undef CONFIG_SYS_RAMBOOT
120 #define CONFIG_FLASH_CFI_DRIVER
121 #define CONFIG_SYS_FLASH_CFI
122 #define CONFIG_SYS_FLASH_EMPTY_INFO
124 #undef CONFIG_CLOCKS_IN_MHZ
127 * Local Bus Definitions
131 * Base Register 2 and Option Register 2 configure SDRAM.
132 * The SDRAM base address, CONFIG_SYS_LBC_SDRAM_BASE, is 0xf0000000.
135 * Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0
136 * port-size = 32-bits = BR2[19:20] = 11
137 * no parity checking = BR2[21:22] = 00
138 * SDRAM for MSEL = BR2[24:26] = 011
141 * 0 4 8 12 16 20 24 28
142 * 1111 0000 0000 0000 0001 1000 0110 0001 = f0001861
144 * FIXME: CONFIG_SYS_LBC_SDRAM_BASE should be masked and OR'ed into
145 * FIXME: the top 17 bits of BR2.
148 #define CONFIG_SYS_BR2_PRELIM 0xf0001861
151 * The SDRAM size in MB, CONFIG_SYS_LBC_SDRAM_SIZE, is 64.
154 * 64MB mask for AM, OR2[0:7] = 1111 1100
155 * XAM, OR2[17:18] = 11
156 * 9 columns OR2[19-21] = 010
157 * 13 rows OR2[23-25] = 100
158 * EAD set for extra time OR[31] = 1
160 * 0 4 8 12 16 20 24 28
161 * 1111 1100 0000 0000 0110 1001 0000 0001 = fc006901
164 #define CONFIG_SYS_OR2_PRELIM 0xfc006901
166 #define CONFIG_SYS_LBC_LCRR 0x00030004 /* LB clock ratio reg */
167 #define CONFIG_SYS_LBC_LBCR 0x00000000 /* LB config reg */
168 #define CONFIG_SYS_LBC_LSRT 0x20000000 /* LB sdram refresh timer */
169 #define CONFIG_SYS_LBC_MRTPR 0x20000000 /* LB refresh timer prescal*/
171 #define CONFIG_SYS_LBC_LSDMR_COMMON ( LSDMR_BSMA1516 \
182 * SDRAM Controller configuration sequence.
184 #define CONFIG_SYS_LBC_LSDMR_1 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_PCHALL)
185 #define CONFIG_SYS_LBC_LSDMR_2 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_ARFRSH)
186 #define CONFIG_SYS_LBC_LSDMR_3 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_ARFRSH)
187 #define CONFIG_SYS_LBC_LSDMR_4 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_MRW)
188 #define CONFIG_SYS_LBC_LSDMR_5 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_NORMAL)
191 * 32KB, 8-bit wide for ADS config reg
193 #define CONFIG_SYS_BR4_PRELIM 0xf8000801
194 #define CONFIG_SYS_OR4_PRELIM 0xffffe1f1
195 #define CONFIG_SYS_BCSR (CONFIG_SYS_BR4_PRELIM & 0xffff8000)
197 #define CONFIG_SYS_INIT_RAM_LOCK 1
198 #define CONFIG_SYS_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */
199 #define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in RAM */
201 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
202 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
204 #define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */
205 #define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserved for malloc */
208 #define CONFIG_CONS_ON_SCC /* define if console on SCC */
209 #undef CONFIG_CONS_NONE /* define if console on something else */
210 #define CONFIG_CONS_INDEX 1 /* which serial channel for console */
212 #define CONFIG_BAUDRATE 115200
214 #define CONFIG_SYS_BAUDRATE_TABLE \
215 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
220 #define CONFIG_SYS_I2C
221 #define CONFIG_SYS_I2C_FSL
222 #define CONFIG_SYS_FSL_I2C_SPEED 400000
223 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
224 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
225 #define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} }
228 #define CONFIG_SYS_RIO_MEM_VIRT 0xc0000000 /* base address */
229 #define CONFIG_SYS_RIO_MEM_BUS 0xc0000000 /* base address */
230 #define CONFIG_SYS_RIO_MEM_PHYS 0xc0000000
231 #define CONFIG_SYS_RIO_MEM_SIZE 0x20000000 /* 128M */
235 * Memory space is mapped 1-1, but I/O space must start from 0.
237 #define CONFIG_SYS_PCI1_MEM_VIRT 0x80000000
238 #define CONFIG_SYS_PCI1_MEM_BUS 0x80000000
239 #define CONFIG_SYS_PCI1_MEM_PHYS 0x80000000
240 #define CONFIG_SYS_PCI1_MEM_SIZE 0x20000000 /* 512M */
241 #define CONFIG_SYS_PCI1_IO_VIRT 0xe2000000
242 #define CONFIG_SYS_PCI1_IO_BUS 0x00000000
243 #define CONFIG_SYS_PCI1_IO_PHYS 0xe2000000
244 #define CONFIG_SYS_PCI1_IO_SIZE 0x100000 /* 1M */
246 #if defined(CONFIG_PCI)
247 #undef CONFIG_EEPRO100
250 #if !defined(CONFIG_PCI_PNP)
251 #define PCI_ENET0_IOADDR 0xe0000000
252 #define PCI_ENET0_MEMADDR 0xe0000000
253 #define PCI_IDSEL_NUMBER 0x0c /* slot0->3(IDSEL)=12->15 */
256 #undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
257 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */
259 #endif /* CONFIG_PCI */
261 #ifdef CONFIG_TSEC_ENET
264 #define CONFIG_MII 1 /* MII PHY management */
266 #define CONFIG_TSEC1 1
267 #define CONFIG_TSEC1_NAME "TSEC0"
268 #define CONFIG_TSEC2 1
269 #define CONFIG_TSEC2_NAME "TSEC1"
270 #define TSEC1_PHY_ADDR 0
271 #define TSEC2_PHY_ADDR 1
272 #define TSEC1_PHYIDX 0
273 #define TSEC2_PHYIDX 0
274 #define TSEC1_FLAGS TSEC_GIGABIT
275 #define TSEC2_FLAGS TSEC_GIGABIT
277 /* Options are: TSEC[0-1] */
278 #define CONFIG_ETHPRIME "TSEC0"
280 #endif /* CONFIG_TSEC_ENET */
282 #ifdef CONFIG_ETHER_ON_FCC /* CPM FCC Ethernet */
284 #undef CONFIG_ETHER_NONE /* define if ether on something else */
285 #define CONFIG_ETHER_INDEX 2 /* which channel for ether */
287 #if (CONFIG_ETHER_INDEX == 2)
291 * - Select bus for bd/buffers
294 #define CONFIG_SYS_CMXFCR_MASK2 (CMXFCR_FC2 | CMXFCR_RF2CS_MSK | CMXFCR_TF2CS_MSK)
295 #define CONFIG_SYS_CMXFCR_VALUE2 (CMXFCR_RF2CS_CLK13 | CMXFCR_TF2CS_CLK14)
296 #define CONFIG_SYS_CPMFCR_RAMTYPE 0
297 #define CONFIG_SYS_FCC_PSMR (FCC_PSMR_FDE)
298 #define FETH2_RST 0x01
299 #elif (CONFIG_ETHER_INDEX == 3)
300 /* need more definitions here for FE3 */
301 #define FETH3_RST 0x80
302 #endif /* CONFIG_ETHER_INDEX */
305 #define CONFIG_MII 1 /* MII PHY management */
308 #define CONFIG_BITBANGMII /* bit-bang MII PHY management */
311 * GPIO pins used for bit-banged MII communications
313 #define MDIO_PORT 2 /* Port C */
314 #define MDIO_DECLARE volatile ioport_t *iop = ioport_addr ( \
315 (immap_t *) CONFIG_SYS_IMMR, MDIO_PORT )
316 #define MDC_DECLARE MDIO_DECLARE
318 #define MDIO_ACTIVE (iop->pdir |= 0x00400000)
319 #define MDIO_TRISTATE (iop->pdir &= ~0x00400000)
320 #define MDIO_READ ((iop->pdat & 0x00400000) != 0)
322 #define MDIO(bit) if(bit) iop->pdat |= 0x00400000; \
323 else iop->pdat &= ~0x00400000
325 #define MDC(bit) if(bit) iop->pdat |= 0x00200000; \
326 else iop->pdat &= ~0x00200000
328 #define MIIDELAY udelay(1)
335 #ifndef CONFIG_SYS_RAMBOOT
336 #define CONFIG_ENV_IS_IN_FLASH 1
337 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + 0x40000)
338 #define CONFIG_ENV_SECT_SIZE 0x40000 /* 256K(one sector) for env */
339 #define CONFIG_ENV_SIZE 0x2000
341 #define CONFIG_SYS_NO_FLASH 1 /* Flash is not usable now */
342 #define CONFIG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */
343 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
344 #define CONFIG_ENV_SIZE 0x2000
347 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
348 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
353 #define CONFIG_BOOTP_BOOTFILESIZE
354 #define CONFIG_BOOTP_BOOTPATH
355 #define CONFIG_BOOTP_GATEWAY
356 #define CONFIG_BOOTP_HOSTNAME
359 * Command line configuration.
361 #define CONFIG_CMD_IRQ
362 #define CONFIG_CMD_REGINFO
364 #if defined(CONFIG_PCI)
365 #define CONFIG_CMD_PCI
368 #if defined(CONFIG_ETHER_ON_FCC)
371 #undef CONFIG_WATCHDOG /* watchdog disabled */
374 * Miscellaneous configurable options
376 #define CONFIG_SYS_LONGHELP /* undef to save memory */
377 #define CONFIG_CMDLINE_EDITING /* Command-line editing */
378 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */
379 #define CONFIG_SYS_LOAD_ADDR 0x1000000 /* default load address */
381 #if defined(CONFIG_CMD_KGDB)
382 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
384 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
387 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
388 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */
389 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
392 * For booting Linux, the board info and command line data
393 * have to be in the first 64 MB of memory, since this is
394 * the maximum mapped by the Linux kernel during initialization.
396 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux*/
397 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
399 #if defined(CONFIG_CMD_KGDB)
400 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
404 * Environment Configuration
406 #if defined(CONFIG_TSEC_ENET) || defined(CONFIG_ETHER_ON_FCC)
407 #define CONFIG_HAS_ETH0
408 #define CONFIG_HAS_ETH1
409 #define CONFIG_HAS_ETH2
410 #define CONFIG_HAS_ETH3
413 #define CONFIG_IPADDR 192.168.1.253
415 #define CONFIG_HOSTNAME unknown
416 #define CONFIG_ROOTPATH "/nfsroot"
417 #define CONFIG_BOOTFILE "your.uImage"
419 #define CONFIG_SERVERIP 192.168.1.1
420 #define CONFIG_GATEWAYIP 192.168.1.1
421 #define CONFIG_NETMASK 255.255.255.0
423 #define CONFIG_LOADADDR 200000 /* default location for tftp and bootm */
425 #undef CONFIG_BOOTARGS /* the boot command will set bootargs */
427 #define CONFIG_BAUDRATE 115200
429 #define CONFIG_EXTRA_ENV_SETTINGS \
431 "consoledev=ttyCPM\0" \
432 "ramdiskaddr=1000000\0" \
433 "ramdiskfile=your.ramdisk.u-boot\0" \
435 "fdtfile=mpc8560ads.dtb\0"
437 #define CONFIG_NFSBOOTCOMMAND \
438 "setenv bootargs root=/dev/nfs rw " \
439 "nfsroot=$serverip:$rootpath " \
440 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
441 "console=$consoledev,$baudrate $othbootargs;" \
442 "tftp $loadaddr $bootfile;" \
443 "tftp $fdtaddr $fdtfile;" \
444 "bootm $loadaddr - $fdtaddr"
446 #define CONFIG_RAMBOOTCOMMAND \
447 "setenv bootargs root=/dev/ram rw " \
448 "console=$consoledev,$baudrate $othbootargs;" \
449 "tftp $ramdiskaddr $ramdiskfile;" \
450 "tftp $loadaddr $bootfile;" \
451 "tftp $fdtaddr $fdtfile;" \
452 "bootm $loadaddr $ramdiskaddr $fdtaddr"
454 #define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND
456 #endif /* __CONFIG_H */