2 * Copyright 2007-2008,2010-2011 Freescale Semiconductor, Inc.
4 * See file CREDITS for list of people who contributed to this
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of
10 * the License, or (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
24 * mpc8572ds board configuration file
30 #include "../board/freescale/common/ics307_clk.h"
33 #define CONFIG_PHYS_64BIT
37 #define CONFIG_NAND_U_BOOT
38 #define CONFIG_RAMBOOT_NAND
39 #ifdef CONFIG_NAND_SPL
40 #define CONFIG_SYS_TEXT_BASE_SPL 0xfff00000
41 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE_SPL /* start of monitor */
43 #define CONFIG_SYS_TEXT_BASE 0xf8f82000
44 #endif /* CONFIG_NAND_SPL */
47 #ifndef CONFIG_SYS_TEXT_BASE
48 #define CONFIG_SYS_TEXT_BASE 0xeff80000
51 #ifndef CONFIG_RESET_VECTOR_ADDRESS
52 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
55 #ifndef CONFIG_SYS_MONITOR_BASE
56 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
59 /* High Level Configuration Options */
60 #define CONFIG_BOOKE 1 /* BOOKE */
61 #define CONFIG_E500 1 /* BOOKE e500 family */
62 #define CONFIG_MPC85xx 1 /* MPC8540/60/55/41/48 */
63 #define CONFIG_MPC8572 1
64 #define CONFIG_MPC8572DS 1
65 #define CONFIG_MP 1 /* support multiple processors */
67 #define CONFIG_FSL_ELBC 1 /* Has Enhanced localbus controller */
68 #define CONFIG_PCI 1 /* Enable PCI/PCIE */
69 #define CONFIG_PCIE1 1 /* PCIE controler 1 (slot 1) */
70 #define CONFIG_PCIE2 1 /* PCIE controler 2 (slot 2) */
71 #define CONFIG_PCIE3 1 /* PCIE controler 3 (ULI bridge) */
72 #define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */
73 #define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */
74 #define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */
76 #define CONFIG_FSL_LAW 1 /* Use common FSL init code */
78 #define CONFIG_TSEC_ENET /* tsec ethernet support */
79 #define CONFIG_ENV_OVERWRITE
81 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk() /* sysclk for MPC85xx */
82 #define CONFIG_DDR_CLK_FREQ get_board_ddr_clk() /* ddrclk for MPC85xx */
83 #define CONFIG_ICS307_REFCLK_HZ 33333000 /* ICS307 clock chip ref freq */
86 * These can be toggled for performance analysis, otherwise use default.
88 #define CONFIG_L2_CACHE /* toggle L2 cache */
89 #define CONFIG_BTB /* toggle branch predition */
91 #define CONFIG_ENABLE_36BIT_PHYS 1
93 #ifdef CONFIG_PHYS_64BIT
94 #define CONFIG_ADDR_MAP 1
95 #define CONFIG_SYS_NUM_ADDR_MAP 16 /* number of TLB1 entries */
98 #define CONFIG_SYS_MEMTEST_START 0x00000000 /* memtest works on */
99 #define CONFIG_SYS_MEMTEST_END 0x7fffffff
100 #define CONFIG_PANIC_HANG /* do not reset board on panic */
103 * Config the L2 Cache as L2 SRAM
105 #define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000
106 #ifdef CONFIG_PHYS_64BIT
107 #define CONFIG_SYS_INIT_L2_ADDR_PHYS 0xff8f80000ull
109 #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR
111 #define CONFIG_SYS_L2_SIZE (512 << 10)
112 #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
115 * Base addresses -- Note these are effective addresses where the
116 * actual resources get mapped (not physical addresses)
118 #define CONFIG_SYS_CCSRBAR 0xffe00000 /* relocated CCSRBAR */
119 #ifdef CONFIG_PHYS_64BIT
120 #define CONFIG_SYS_CCSRBAR_PHYS 0xfffe00000ull /* physical addr of CCSRBAR */
122 #define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR /* physical addr of CCSRBAR */
124 #define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR /* PQII uses CONFIG_SYS_IMMR */
126 #if defined(CONFIG_RAMBOOT_NAND) && !defined(CONFIG_NAND_SPL)
127 #define CONFIG_SYS_CCSRBAR_DEFAULT CONFIG_SYS_CCSRBAR
129 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */
133 #define CONFIG_VERY_BIG_RAM
134 #define CONFIG_FSL_DDR2
135 #undef CONFIG_FSL_DDR_INTERACTIVE
136 #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */
137 #define CONFIG_DDR_SPD
139 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
140 #define CONFIG_MEM_INIT_VALUE 0xDeadBeef
142 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
143 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
145 #define CONFIG_NUM_DDR_CONTROLLERS 2
146 #define CONFIG_DIMM_SLOTS_PER_CTLR 1
147 #define CONFIG_CHIP_SELECTS_PER_CTRL 2
149 /* I2C addresses of SPD EEPROMs */
150 #define CONFIG_SYS_SPD_BUS_NUM 1 /* SPD EEPROMS locate on I2C bus 1 */
151 #define SPD_EEPROM_ADDRESS1 0x51 /* CTLR 0 DIMM 0 */
152 #define SPD_EEPROM_ADDRESS2 0x52 /* CTLR 1 DIMM 0 */
154 /* These are used when DDR doesn't use SPD. */
155 #define CONFIG_SYS_SDRAM_SIZE 512 /* DDR is 512MB */
156 #define CONFIG_SYS_DDR_CS0_BNDS 0x0000001F
157 #define CONFIG_SYS_DDR_CS0_CONFIG 0x80010202 /* Enable, no interleaving */
158 #define CONFIG_SYS_DDR_TIMING_3 0x00020000
159 #define CONFIG_SYS_DDR_TIMING_0 0x00260802
160 #define CONFIG_SYS_DDR_TIMING_1 0x626b2634
161 #define CONFIG_SYS_DDR_TIMING_2 0x062874cf
162 #define CONFIG_SYS_DDR_MODE_1 0x00440462
163 #define CONFIG_SYS_DDR_MODE_2 0x00000000
164 #define CONFIG_SYS_DDR_INTERVAL 0x0c300100
165 #define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef
166 #define CONFIG_SYS_DDR_CLK_CTRL 0x00800000
167 #define CONFIG_SYS_DDR_OCD_CTRL 0x00000000
168 #define CONFIG_SYS_DDR_OCD_STATUS 0x00000000
169 #define CONFIG_SYS_DDR_CONTROL 0xc3000008 /* Type = DDR2 */
170 #define CONFIG_SYS_DDR_CONTROL2 0x24400000
172 #define CONFIG_SYS_DDR_ERR_INT_EN 0x0000000d
173 #define CONFIG_SYS_DDR_ERR_DIS 0x00000000
174 #define CONFIG_SYS_DDR_SBE 0x00010000
177 * Make sure required options are set
179 #ifndef CONFIG_SPD_EEPROM
180 #error ("CONFIG_SPD_EEPROM is required")
183 #undef CONFIG_CLOCKS_IN_MHZ
188 * 0x0000_0000 0x7fff_ffff DDR 2G Cacheable
189 * 0x8000_0000 0xbfff_ffff PCI Express Mem 1G non-cacheable
190 * 0xc000_0000 0xdfff_ffff PCI 512M non-cacheable
191 * 0xe100_0000 0xe3ff_ffff PCI IO range 4M non-cacheable
193 * Localbus cacheable (TBD)
194 * 0xXXXX_XXXX 0xXXXX_XXXX SRAM YZ M Cacheable
196 * Localbus non-cacheable
197 * 0xe000_0000 0xe80f_ffff Promjet/free 128M non-cacheable
198 * 0xe800_0000 0xefff_ffff FLASH 128M non-cacheable
199 * 0xffa0_0000 0xffaf_ffff NAND 1M non-cacheable
200 * 0xffdf_0000 0xffdf_7fff PIXIS 32K non-cacheable TLB0
201 * 0xffd0_0000 0xffd0_3fff L1 for stack 16K Cacheable TLB0
202 * 0xffe0_0000 0xffef_ffff CCSR 1M non-cacheable
206 * Local Bus Definitions
208 #define CONFIG_SYS_FLASH_BASE 0xe0000000 /* start of FLASH 128M */
209 #ifdef CONFIG_PHYS_64BIT
210 #define CONFIG_SYS_FLASH_BASE_PHYS 0xfe0000000ull
212 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
216 #define CONFIG_FLASH_BR_PRELIM \
217 (BR_PHYS_ADDR((CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000)) \
219 #define CONFIG_FLASH_OR_PRELIM 0xf8000ff7
221 #define CONFIG_SYS_BR1_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | BR_PS_16 | BR_V)
222 #define CONFIG_SYS_OR1_PRELIM 0xf8000ff7
224 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS}
225 #define CONFIG_SYS_FLASH_QUIET_TEST
226 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
228 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */
229 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
230 #undef CONFIG_SYS_FLASH_CHECKSUM
231 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
232 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
234 #if defined(CONFIG_RAMBOOT_NAND)
235 #define CONFIG_SYS_RAMBOOT
236 #define CONFIG_SYS_EXTRA_ENV_RELOC
238 #undef CONFIG_SYS_RAMBOOT
241 #define CONFIG_FLASH_CFI_DRIVER
242 #define CONFIG_SYS_FLASH_CFI
243 #define CONFIG_SYS_FLASH_EMPTY_INFO
244 #define CONFIG_SYS_FLASH_AMD_CHECK_DQ7
246 #define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */
248 #define CONFIG_HWCONFIG /* enable hwconfig */
249 #define CONFIG_FSL_PIXIS 1 /* use common PIXIS code */
250 #define PIXIS_BASE 0xffdf0000 /* PIXIS registers */
251 #ifdef CONFIG_PHYS_64BIT
252 #define PIXIS_BASE_PHYS 0xfffdf0000ull
254 #define PIXIS_BASE_PHYS PIXIS_BASE
257 #define CONFIG_SYS_BR3_PRELIM (BR_PHYS_ADDR(PIXIS_BASE_PHYS) | BR_PS_8 | BR_V)
258 #define CONFIG_SYS_OR3_PRELIM 0xffffeff7 /* 32KB but only 4k mapped */
260 #define PIXIS_ID 0x0 /* Board ID at offset 0 */
261 #define PIXIS_VER 0x1 /* Board version at offset 1 */
262 #define PIXIS_PVER 0x2 /* PIXIS FPGA version at offset 2 */
263 #define PIXIS_CSR 0x3 /* PIXIS General control/status register */
264 #define PIXIS_RST 0x4 /* PIXIS Reset Control register */
265 #define PIXIS_PWR 0x5 /* PIXIS Power status register */
266 #define PIXIS_AUX 0x6 /* Auxiliary 1 register */
267 #define PIXIS_SPD 0x7 /* Register for SYSCLK speed */
268 #define PIXIS_AUX2 0x8 /* Auxiliary 2 register */
269 #define PIXIS_VCTL 0x10 /* VELA Control Register */
270 #define PIXIS_VSTAT 0x11 /* VELA Status Register */
271 #define PIXIS_VCFGEN0 0x12 /* VELA Config Enable 0 */
272 #define PIXIS_VCFGEN1 0x13 /* VELA Config Enable 1 */
273 #define PIXIS_VCORE0 0x14 /* VELA VCORE0 Register */
274 #define PIXIS_VBOOT 0x16 /* VELA VBOOT Register */
275 #define PIXIS_VBOOT_LBMAP 0xc0 /* VBOOT - CFG_LBMAP */
276 #define PIXIS_VBOOT_LBMAP_NOR0 0x00 /* cfg_lbmap - boot from NOR 0 */
277 #define PIXIS_VBOOT_LBMAP_PJET 0x01 /* cfg_lbmap - boot from projet */
278 #define PIXIS_VBOOT_LBMAP_NAND 0x02 /* cfg_lbmap - boot from NAND */
279 #define PIXIS_VBOOT_LBMAP_NOR1 0x03 /* cfg_lbmap - boot from NOR 1 */
280 #define PIXIS_VSPEED0 0x17 /* VELA VSpeed 0 */
281 #define PIXIS_VSPEED1 0x18 /* VELA VSpeed 1 */
282 #define PIXIS_VSPEED2 0x19 /* VELA VSpeed 2 */
283 #define PIXIS_VSYSCLK0 0x1C /* VELA SYSCLK0 Register */
284 #define PIXIS_VSYSCLK1 0x1D /* VELA SYSCLK1 Register */
285 #define PIXIS_VSYSCLK2 0x1E /* VELA SYSCLK2 Register */
286 #define PIXIS_VDDRCLK0 0x1F /* VELA DDRCLK0 Register */
287 #define PIXIS_VDDRCLK1 0x20 /* VELA DDRCLK1 Register */
288 #define PIXIS_VDDRCLK2 0x21 /* VELA DDRCLK2 Register */
289 #define PIXIS_VWATCH 0x24 /* Watchdog Register */
290 #define PIXIS_LED 0x25 /* LED Register */
292 #define PIXIS_SPD_SYSCLK_MASK 0x7 /* SYSCLK option */
294 /* old pixis referenced names */
295 #define PIXIS_VCLKH 0x19 /* VELA VCLKH register */
296 #define PIXIS_VCLKL 0x1A /* VELA VCLKL register */
297 #define CONFIG_SYS_PIXIS_VBOOT_MASK 0xc0
298 #define PIXIS_VSPEED2_TSEC1SER 0x8
299 #define PIXIS_VSPEED2_TSEC2SER 0x4
300 #define PIXIS_VSPEED2_TSEC3SER 0x2
301 #define PIXIS_VSPEED2_TSEC4SER 0x1
302 #define PIXIS_VCFGEN1_TSEC1SER 0x20
303 #define PIXIS_VCFGEN1_TSEC2SER 0x20
304 #define PIXIS_VCFGEN1_TSEC3SER 0x20
305 #define PIXIS_VCFGEN1_TSEC4SER 0x20
306 #define PIXIS_VSPEED2_MASK (PIXIS_VSPEED2_TSEC1SER \
307 | PIXIS_VSPEED2_TSEC2SER \
308 | PIXIS_VSPEED2_TSEC3SER \
309 | PIXIS_VSPEED2_TSEC4SER)
310 #define PIXIS_VCFGEN1_MASK (PIXIS_VCFGEN1_TSEC1SER \
311 | PIXIS_VCFGEN1_TSEC2SER \
312 | PIXIS_VCFGEN1_TSEC3SER \
313 | PIXIS_VCFGEN1_TSEC4SER)
315 #define CONFIG_SYS_INIT_RAM_LOCK 1
316 #define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* Initial L1 address */
317 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 /* Size of used area in RAM */
319 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
320 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
322 #define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */
323 #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */
325 #ifndef CONFIG_NAND_SPL
326 #define CONFIG_SYS_NAND_BASE 0xffa00000
327 #ifdef CONFIG_PHYS_64BIT
328 #define CONFIG_SYS_NAND_BASE_PHYS 0xfffa00000ull
330 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
333 #define CONFIG_SYS_NAND_BASE 0xfff00000
334 #ifdef CONFIG_PHYS_64BIT
335 #define CONFIG_SYS_NAND_BASE_PHYS 0xffff00000ull
337 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
341 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE,\
342 CONFIG_SYS_NAND_BASE + 0x40000, \
343 CONFIG_SYS_NAND_BASE + 0x80000,\
344 CONFIG_SYS_NAND_BASE + 0xC0000}
345 #define CONFIG_SYS_MAX_NAND_DEVICE 4
346 #define CONFIG_MTD_NAND_VERIFY_WRITE
347 #define CONFIG_CMD_NAND 1
348 #define CONFIG_NAND_FSL_ELBC 1
349 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
351 /* NAND boot: 4K NAND loader config */
352 #define CONFIG_SYS_NAND_SPL_SIZE 0x1000
353 #define CONFIG_SYS_NAND_U_BOOT_SIZE ((512 << 10) - 0x2000)
354 #define CONFIG_SYS_NAND_U_BOOT_DST (CONFIG_SYS_INIT_L2_ADDR)
355 #define CONFIG_SYS_NAND_U_BOOT_START \
356 (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_NAND_SPL_SIZE)
357 #define CONFIG_SYS_NAND_U_BOOT_OFFS (0)
358 #define CONFIG_SYS_NAND_U_BOOT_RELOC (CONFIG_SYS_INIT_L2_END - 0x2000)
359 #define CONFIG_SYS_NAND_U_BOOT_RELOC_SP ((CONFIG_SYS_INIT_L2_END - 1) & ~0xF)
362 /* NAND flash config */
363 #define CONFIG_NAND_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
364 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
365 | BR_PS_8 /* Port Size = 8 bit */ \
366 | BR_MS_FCM /* MSEL = FCM */ \
368 #define CONFIG_NAND_OR_PRELIM (0xFFFC0000 /* length 256K */ \
369 | OR_FCM_PGS /* Large Page*/ \
377 #ifdef CONFIG_RAMBOOT_NAND
378 #define CONFIG_SYS_BR0_PRELIM CONFIG_NAND_BR_PRELIM /* NAND Base Address */
379 #define CONFIG_SYS_OR0_PRELIM CONFIG_NAND_OR_PRELIM /* NAND Options */
380 #define CONFIG_SYS_BR2_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */
381 #define CONFIG_SYS_OR2_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */
383 #define CONFIG_SYS_BR0_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */
384 #define CONFIG_SYS_OR0_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */
385 #define CONFIG_SYS_BR2_PRELIM CONFIG_NAND_BR_PRELIM /* NAND Base Address */
386 #define CONFIG_SYS_OR2_PRELIM CONFIG_NAND_OR_PRELIM /* NAND Options */
388 #define CONFIG_SYS_BR4_PRELIM (BR_PHYS_ADDR((CONFIG_SYS_NAND_BASE_PHYS + 0x40000))\
389 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
390 | BR_PS_8 /* Port Size = 8 bit */ \
391 | BR_MS_FCM /* MSEL = FCM */ \
393 #define CONFIG_SYS_OR4_PRELIM CONFIG_NAND_OR_PRELIM /* NAND Options */
394 #define CONFIG_SYS_BR5_PRELIM (BR_PHYS_ADDR((CONFIG_SYS_NAND_BASE_PHYS + 0x80000))\
395 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
396 | BR_PS_8 /* Port Size = 8 bit */ \
397 | BR_MS_FCM /* MSEL = FCM */ \
399 #define CONFIG_SYS_OR5_PRELIM CONFIG_NAND_OR_PRELIM /* NAND Options */
401 #define CONFIG_SYS_BR6_PRELIM (BR_PHYS_ADDR((CONFIG_SYS_NAND_BASE_PHYS + 0xc0000))\
402 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
403 | BR_PS_8 /* Port Size = 8 bit */ \
404 | BR_MS_FCM /* MSEL = FCM */ \
406 #define CONFIG_SYS_OR6_PRELIM CONFIG_NAND_OR_PRELIM /* NAND Options */
409 /* Serial Port - controlled on board with jumper J8
413 #define CONFIG_CONS_INDEX 1
414 #define CONFIG_SYS_NS16550
415 #define CONFIG_SYS_NS16550_SERIAL
416 #define CONFIG_SYS_NS16550_REG_SIZE 1
417 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
418 #ifdef CONFIG_NAND_SPL
419 #define CONFIG_NS16550_MIN_FUNCTIONS
422 #define CONFIG_SYS_BAUDRATE_TABLE \
423 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
425 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
426 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
428 /* Use the HUSH parser */
429 #define CONFIG_SYS_HUSH_PARSER
430 #ifdef CONFIG_SYS_HUSH_PARSER
431 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
435 * Pass open firmware flat tree
437 #define CONFIG_OF_LIBFDT 1
438 #define CONFIG_OF_BOARD_SETUP 1
439 #define CONFIG_OF_STDOUT_VIA_ALIAS 1
441 /* new uImage format support */
443 #define CONFIG_FIT_VERBOSE 1 /* enable fit_format_{error,warning}() */
446 #define CONFIG_FSL_I2C /* Use FSL common I2C driver */
447 #define CONFIG_HARD_I2C /* I2C with hardware support */
448 #undef CONFIG_SOFT_I2C /* I2C bit-banged */
449 #define CONFIG_I2C_MULTI_BUS
450 #define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */
451 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
452 #define CONFIG_SYS_I2C_SLAVE 0x7F
453 #define CONFIG_SYS_I2C_NOPROBES {{0,0x29}}/* Don't probe these addrs */
454 #define CONFIG_SYS_I2C_OFFSET 0x3000
455 #define CONFIG_SYS_I2C2_OFFSET 0x3100
460 #define CONFIG_ID_EEPROM
461 #ifdef CONFIG_ID_EEPROM
462 #define CONFIG_SYS_I2C_EEPROM_NXID
464 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
465 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
466 #define CONFIG_SYS_EEPROM_BUS_NUM 1
470 * Memory space is mapped 1-1, but I/O space must start from 0.
473 /* controller 3, direct to uli, tgtid 3, Base address 8000 */
474 #define CONFIG_SYS_PCIE3_NAME "ULI"
475 #define CONFIG_SYS_PCIE3_MEM_VIRT 0x80000000
476 #ifdef CONFIG_PHYS_64BIT
477 #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000
478 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc00000000ull
480 #define CONFIG_SYS_PCIE3_MEM_BUS 0x80000000
481 #define CONFIG_SYS_PCIE3_MEM_PHYS 0x80000000
483 #define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */
484 #define CONFIG_SYS_PCIE3_IO_VIRT 0xffc00000
485 #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000
486 #ifdef CONFIG_PHYS_64BIT
487 #define CONFIG_SYS_PCIE3_IO_PHYS 0xfffc00000ull
489 #define CONFIG_SYS_PCIE3_IO_PHYS 0xffc00000
491 #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */
493 /* controller 2, Slot 2, tgtid 2, Base address 9000 */
494 #define CONFIG_SYS_PCIE2_NAME "Slot 1"
495 #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000
496 #ifdef CONFIG_PHYS_64BIT
497 #define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000
498 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull
500 #define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000
501 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000
503 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */
504 #define CONFIG_SYS_PCIE2_IO_VIRT 0xffc10000
505 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
506 #ifdef CONFIG_PHYS_64BIT
507 #define CONFIG_SYS_PCIE2_IO_PHYS 0xfffc10000ull
509 #define CONFIG_SYS_PCIE2_IO_PHYS 0xffc10000
511 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */
513 /* controller 1, Slot 1, tgtid 1, Base address a000 */
514 #define CONFIG_SYS_PCIE1_NAME "Slot 2"
515 #define CONFIG_SYS_PCIE1_MEM_VIRT 0xc0000000
516 #ifdef CONFIG_PHYS_64BIT
517 #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000
518 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc40000000ull
520 #define CONFIG_SYS_PCIE1_MEM_BUS 0xc0000000
521 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc0000000
523 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */
524 #define CONFIG_SYS_PCIE1_IO_VIRT 0xffc20000
525 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
526 #ifdef CONFIG_PHYS_64BIT
527 #define CONFIG_SYS_PCIE1_IO_PHYS 0xfffc20000ull
529 #define CONFIG_SYS_PCIE1_IO_PHYS 0xffc20000
531 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
533 #if defined(CONFIG_PCI)
535 /*PCIE video card used*/
536 #define VIDEO_IO_OFFSET CONFIG_SYS_PCIE1_IO_VIRT
541 #if defined(CONFIG_VIDEO)
542 #define CONFIG_BIOSEMU
543 #define CONFIG_CFB_CONSOLE
544 #define CONFIG_VIDEO_SW_CURSOR
545 #define CONFIG_VGA_AS_SINGLE_DEVICE
546 #define CONFIG_ATI_RADEON_FB
547 #define CONFIG_VIDEO_LOGO
548 /*#define CONFIG_CONSOLE_CURSOR*/
549 #define CONFIG_SYS_ISA_IO_BASE_ADDRESS VIDEO_IO_OFFSET
552 #define CONFIG_NET_MULTI
553 #define CONFIG_PCI_PNP /* do pci plug-and-play */
555 #undef CONFIG_EEPRO100
557 #undef CONFIG_RTL8139
558 #define CONFIG_E1000 /* Define e1000 pci Ethernet card */
560 #ifndef CONFIG_PCI_PNP
561 #define PCI_ENET0_IOADDR CONFIG_SYS_PCIE3_IO_BUS
562 #define PCI_ENET0_MEMADDR CONFIG_SYS_PCIE3_IO_BUS
563 #define PCI_IDSEL_NUMBER 0x11 /* IDSEL = AD11 */
566 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
567 #define CONFIG_DOS_PARTITION
568 #define CONFIG_SCSI_AHCI
570 #ifdef CONFIG_SCSI_AHCI
571 #define CONFIG_SATA_ULI5288
572 #define CONFIG_SYS_SCSI_MAX_SCSI_ID 4
573 #define CONFIG_SYS_SCSI_MAX_LUN 1
574 #define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * CONFIG_SYS_SCSI_MAX_LUN)
575 #define CONFIG_SYS_SCSI_MAXDEVICE CONFIG_SYS_SCSI_MAX_DEVICE
578 #endif /* CONFIG_PCI */
581 #if defined(CONFIG_TSEC_ENET)
583 #ifndef CONFIG_NET_MULTI
584 #define CONFIG_NET_MULTI 1
587 #define CONFIG_MII 1 /* MII PHY management */
588 #define CONFIG_MII_DEFAULT_TSEC 1 /* Allow unregistered phys */
589 #define CONFIG_TSEC1 1
590 #define CONFIG_TSEC1_NAME "eTSEC1"
591 #define CONFIG_TSEC2 1
592 #define CONFIG_TSEC2_NAME "eTSEC2"
593 #define CONFIG_TSEC3 1
594 #define CONFIG_TSEC3_NAME "eTSEC3"
595 #define CONFIG_TSEC4 1
596 #define CONFIG_TSEC4_NAME "eTSEC4"
598 #define CONFIG_PIXIS_SGMII_CMD
599 #define CONFIG_FSL_SGMII_RISER 1
600 #define SGMII_RISER_PHY_OFFSET 0x1c
602 #ifdef CONFIG_FSL_SGMII_RISER
603 #define CONFIG_SYS_TBIPA_VALUE 0x10 /* avoid conflict with eTSEC4 paddr */
606 #define TSEC1_PHY_ADDR 0
607 #define TSEC2_PHY_ADDR 1
608 #define TSEC3_PHY_ADDR 2
609 #define TSEC4_PHY_ADDR 3
611 #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
612 #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
613 #define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
614 #define TSEC4_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
616 #define TSEC1_PHYIDX 0
617 #define TSEC2_PHYIDX 0
618 #define TSEC3_PHYIDX 0
619 #define TSEC4_PHYIDX 0
621 #define CONFIG_ETHPRIME "eTSEC1"
623 #define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */
624 #endif /* CONFIG_TSEC_ENET */
630 #if defined(CONFIG_SYS_RAMBOOT)
631 #if defined(CONFIG_RAMBOOT_NAND)
632 #define CONFIG_ENV_IS_IN_NAND 1
633 #define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE
634 #define CONFIG_ENV_OFFSET ((512 * 1024)\
635 + CONFIG_SYS_NAND_BLOCK_SIZE)
639 #define CONFIG_ENV_IS_IN_FLASH 1
640 #if CONFIG_SYS_MONITOR_BASE > 0xfff80000
641 #define CONFIG_ENV_ADDR 0xfff80000
643 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
645 #define CONFIG_ENV_SIZE 0x2000
646 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */
649 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
650 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
653 * Command line configuration.
655 #include <config_cmd_default.h>
657 #define CONFIG_CMD_IRQ
658 #define CONFIG_CMD_PING
659 #define CONFIG_CMD_I2C
660 #define CONFIG_CMD_MII
661 #define CONFIG_CMD_ELF
662 #define CONFIG_CMD_IRQ
663 #define CONFIG_CMD_SETEXPR
664 #define CONFIG_CMD_REGINFO
666 #if defined(CONFIG_PCI)
667 #define CONFIG_CMD_PCI
668 #define CONFIG_CMD_NET
669 #define CONFIG_CMD_SCSI
670 #define CONFIG_CMD_EXT2
673 #undef CONFIG_WATCHDOG /* watchdog disabled */
676 * Miscellaneous configurable options
678 #define CONFIG_SYS_LONGHELP /* undef to save memory */
679 #define CONFIG_CMDLINE_EDITING /* Command-line editing */
680 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */
681 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
682 #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
683 #if defined(CONFIG_CMD_KGDB)
684 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
686 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
688 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
689 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */
690 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
691 #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */
694 * For booting Linux, the board info and command line data
695 * have to be in the first 16 MB of memory, since this is
696 * the maximum mapped by the Linux kernel during initialization.
698 #define CONFIG_SYS_BOOTMAPSZ (16 << 20) /* Initial Memory map for Linux*/
699 #define CONFIG_SYS_BOOTM_LEN (16 << 20) /* Increase max gunzip size */
701 #if defined(CONFIG_CMD_KGDB)
702 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
703 #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
707 * Environment Configuration
710 /* The mac addresses for all ethernet interface */
711 #if defined(CONFIG_TSEC_ENET)
712 #define CONFIG_HAS_ETH0
713 #define CONFIG_ETHADDR 00:E0:0C:02:00:FD
714 #define CONFIG_HAS_ETH1
715 #define CONFIG_ETH1ADDR 00:E0:0C:02:01:FD
716 #define CONFIG_HAS_ETH2
717 #define CONFIG_ETH2ADDR 00:E0:0C:02:02:FD
718 #define CONFIG_HAS_ETH3
719 #define CONFIG_ETH3ADDR 00:E0:0C:02:03:FD
722 #define CONFIG_IPADDR 192.168.1.254
724 #define CONFIG_HOSTNAME unknown
725 #define CONFIG_ROOTPATH /opt/nfsroot
726 #define CONFIG_BOOTFILE uImage
727 #define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */
729 #define CONFIG_SERVERIP 192.168.1.1
730 #define CONFIG_GATEWAYIP 192.168.1.1
731 #define CONFIG_NETMASK 255.255.255.0
733 /* default location for tftp and bootm */
734 #define CONFIG_LOADADDR 1000000
736 #define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */
737 #undef CONFIG_BOOTARGS /* the boot command will set bootargs */
739 #define CONFIG_BAUDRATE 115200
741 #define CONFIG_EXTRA_ENV_SETTINGS \
742 "memctl_intlv_ctl=2\0" \
744 "uboot=" MK_STR(CONFIG_UBOOTPATH) "\0" \
745 "tftpflash=tftpboot $loadaddr $uboot; " \
746 "protect off " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
747 "erase " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
748 "cp.b $loadaddr " MK_STR(CONFIG_SYS_TEXT_BASE) " $filesize; " \
749 "protect on " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
750 "cmp.b $loadaddr " MK_STR(CONFIG_SYS_TEXT_BASE) " $filesize\0" \
751 "consoledev=ttyS0\0" \
752 "ramdiskaddr=2000000\0" \
753 "ramdiskfile=8572ds/ramdisk.uboot\0" \
755 "fdtfile=8572ds/mpc8572ds.dtb\0" \
758 #define CONFIG_HDBOOT \
759 "setenv bootargs root=/dev/$bdev rw " \
760 "console=$consoledev,$baudrate $othbootargs;" \
761 "tftp $loadaddr $bootfile;" \
762 "tftp $fdtaddr $fdtfile;" \
763 "bootm $loadaddr - $fdtaddr"
765 #define CONFIG_NFSBOOTCOMMAND \
766 "setenv bootargs root=/dev/nfs rw " \
767 "nfsroot=$serverip:$rootpath " \
768 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
769 "console=$consoledev,$baudrate $othbootargs;" \
770 "tftp $loadaddr $bootfile;" \
771 "tftp $fdtaddr $fdtfile;" \
772 "bootm $loadaddr - $fdtaddr"
774 #define CONFIG_RAMBOOTCOMMAND \
775 "setenv bootargs root=/dev/ram rw " \
776 "console=$consoledev,$baudrate $othbootargs;" \
777 "tftp $ramdiskaddr $ramdiskfile;" \
778 "tftp $loadaddr $bootfile;" \
779 "tftp $fdtaddr $fdtfile;" \
780 "bootm $loadaddr $ramdiskaddr $fdtaddr"
782 #define CONFIG_BOOTCOMMAND CONFIG_HDBOOT
784 #endif /* __CONFIG_H */