2 * Copyright 2007-2008 Freescale Semiconductor, Inc.
4 * See file CREDITS for list of people who contributed to this
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of
10 * the License, or (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
24 * mpc8572ds board configuration file
30 /* High Level Configuration Options */
31 #define CONFIG_BOOKE 1 /* BOOKE */
32 #define CONFIG_E500 1 /* BOOKE e500 family */
33 #define CONFIG_MPC85xx 1 /* MPC8540/60/55/41/48 */
34 #define CONFIG_MPC8572 1
35 #define CONFIG_MPC8572DS 1
36 #define CONFIG_MP 1 /* support multiple processors */
37 #define CONFIG_NUM_CPUS 2 /* Number of CPUs in the system */
39 #define CONFIG_PCI 1 /* Enable PCI/PCIE */
40 #define CONFIG_PCIE1 1 /* PCIE controler 1 (slot 1) */
41 #define CONFIG_PCIE2 1 /* PCIE controler 2 (slot 2) */
42 #define CONFIG_PCIE3 1 /* PCIE controler 3 (ULI bridge) */
43 #define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */
44 #define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */
46 #define CONFIG_FSL_LAW 1 /* Use common FSL init code */
48 #define CONFIG_TSEC_ENET /* tsec ethernet support */
49 #define CONFIG_ENV_OVERWRITE
52 * When initializing flash, if we cannot find the manufacturer ID,
53 * assume this is the AMD flash associated with the CDS board.
54 * This allows booting from a promjet.
56 #define CONFIG_ASSUME_AMD_FLASH
59 extern unsigned long get_board_sys_clk(unsigned long dummy);
60 extern unsigned long get_board_ddr_clk(unsigned long dummy);
62 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk(0) /* sysclk for MPC85xx */
63 #define CONFIG_DDR_CLK_FREQ get_board_ddr_clk(0) /* ddrclk for MPC85xx */
64 #define CONFIG_ICS307_REFCLK_HZ 33333000 /* ICS307 clock chip ref freq */
65 #define CONFIG_GET_CLK_FROM_ICS307 /* decode sysclk and ddrclk freq
66 from ICS307 instead of switches */
69 * These can be toggled for performance analysis, otherwise use default.
71 #define CONFIG_L2_CACHE /* toggle L2 cache */
72 #define CONFIG_BTB /* toggle branch predition */
73 #define CONFIG_ADDR_STREAMING /* toggle addr streaming */
75 #define CONFIG_ENABLE_36BIT_PHYS 1
77 #define CONFIG_SYS_MEMTEST_START 0x00000000 /* memtest works on */
78 #define CONFIG_SYS_MEMTEST_END 0x7fffffff
79 #define CONFIG_PANIC_HANG /* do not reset board on panic */
82 * Base addresses -- Note these are effective addresses where the
83 * actual resources get mapped (not physical addresses)
85 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */
86 #define CONFIG_SYS_CCSRBAR 0xffe00000 /* relocated CCSRBAR */
87 #define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR /* physical addr of CCSRBAR */
88 #define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR /* PQII uses CONFIG_SYS_IMMR */
90 #define CONFIG_SYS_PCIE3_ADDR (CONFIG_SYS_CCSRBAR+0x8000)
91 #define CONFIG_SYS_PCIE2_ADDR (CONFIG_SYS_CCSRBAR+0x9000)
92 #define CONFIG_SYS_PCIE1_ADDR (CONFIG_SYS_CCSRBAR+0xa000)
95 #define CONFIG_FSL_DDR2
96 #undef CONFIG_FSL_DDR_INTERACTIVE
97 #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */
98 #define CONFIG_DDR_SPD
101 #define CONFIG_MEM_INIT_VALUE 0xDeadBeef
103 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
104 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
106 #define CONFIG_NUM_DDR_CONTROLLERS 2
107 #define CONFIG_DIMM_SLOTS_PER_CTLR 1
108 #define CONFIG_CHIP_SELECTS_PER_CTRL 2
110 /* I2C addresses of SPD EEPROMs */
111 #define CONFIG_SYS_SPD_BUS_NUM 1 /* SPD EEPROMS locate on I2C bus 1 */
112 #define SPD_EEPROM_ADDRESS1 0x51 /* CTLR 0 DIMM 0 */
113 #define SPD_EEPROM_ADDRESS2 0x52 /* CTLR 1 DIMM 0 */
115 /* These are used when DDR doesn't use SPD. */
116 #define CONFIG_SYS_SDRAM_SIZE 256 /* DDR is 256MB */
117 #define CONFIG_SYS_DDR_CS0_BNDS 0x0000001F
118 #define CONFIG_SYS_DDR_CS0_CONFIG 0x80010102 /* Enable, no interleaving */
119 #define CONFIG_SYS_DDR_TIMING_3 0x00000000
120 #define CONFIG_SYS_DDR_TIMING_0 0x00260802
121 #define CONFIG_SYS_DDR_TIMING_1 0x3935d322
122 #define CONFIG_SYS_DDR_TIMING_2 0x14904cc8
123 #define CONFIG_SYS_DDR_MODE_1 0x00480432
124 #define CONFIG_SYS_DDR_MODE_2 0x00000000
125 #define CONFIG_SYS_DDR_INTERVAL 0x06180100
126 #define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef
127 #define CONFIG_SYS_DDR_CLK_CTRL 0x03800000
128 #define CONFIG_SYS_DDR_OCD_CTRL 0x00000000
129 #define CONFIG_SYS_DDR_OCD_STATUS 0x00000000
130 #define CONFIG_SYS_DDR_CONTROL 0xC3008000 /* Type = DDR2 */
131 #define CONFIG_SYS_DDR_CONTROL2 0x04400010
133 #define CONFIG_SYS_DDR_ERR_INT_EN 0x0000000d
134 #define CONFIG_SYS_DDR_ERR_DIS 0x00000000
135 #define CONFIG_SYS_DDR_SBE 0x00010000
138 * Make sure required options are set
140 #ifndef CONFIG_SPD_EEPROM
141 #error ("CONFIG_SPD_EEPROM is required")
144 #undef CONFIG_CLOCKS_IN_MHZ
149 * 0x0000_0000 0x7fff_ffff DDR 2G Cacheable
150 * 0x8000_0000 0xbfff_ffff PCI Express Mem 1G non-cacheable
151 * 0xc000_0000 0xdfff_ffff PCI 512M non-cacheable
152 * 0xe100_0000 0xe3ff_ffff PCI IO range 4M non-cacheable
154 * Localbus cacheable (TBD)
155 * 0xXXXX_XXXX 0xXXXX_XXXX SRAM YZ M Cacheable
157 * Localbus non-cacheable
158 * 0xe000_0000 0xe80f_ffff Promjet/free 128M non-cacheable
159 * 0xe800_0000 0xefff_ffff FLASH 128M non-cacheable
160 * 0xffdf_0000 0xffdf_7fff PIXIS 32K non-cacheable TLB0
161 * 0xffd0_0000 0xffd0_3fff L1 for stack 16K Cacheable TLB0
162 * 0xffe0_0000 0xffef_ffff CCSR 1M non-cacheable
166 * Local Bus Definitions
168 #define CONFIG_SYS_FLASH_BASE 0xe0000000 /* start of FLASH 128M */
170 #define CONFIG_SYS_BR0_PRELIM 0xe8001001
171 #define CONFIG_SYS_OR0_PRELIM 0xf8000ff7
173 #define CONFIG_SYS_BR1_PRELIM 0xe0001001
174 #define CONFIG_SYS_OR1_PRELIM 0xf8000ff7
176 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE + 0x8000000, CONFIG_SYS_FLASH_BASE}
177 #define CONFIG_SYS_FLASH_QUIET_TEST
178 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
180 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */
181 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
182 #undef CONFIG_SYS_FLASH_CHECKSUM
183 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
184 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
186 #define CONFIG_SYS_MONITOR_BASE TEXT_BASE /* start of monitor */
188 #define CONFIG_FLASH_CFI_DRIVER
189 #define CONFIG_SYS_FLASH_CFI
190 #define CONFIG_SYS_FLASH_EMPTY_INFO
191 #define CONFIG_SYS_FLASH_AMD_CHECK_DQ7
193 #define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */
195 #define CONFIG_FSL_PIXIS 1 /* use common PIXIS code */
196 #define PIXIS_BASE 0xffdf0000 /* PIXIS registers */
198 #define CONFIG_SYS_BR3_PRELIM (PIXIS_BASE | 0x0801) /* port size 8bit */
199 #define CONFIG_SYS_OR3_PRELIM 0xffffeff7 /* 32KB but only 4k mapped */
201 #define PIXIS_ID 0x0 /* Board ID at offset 0 */
202 #define PIXIS_VER 0x1 /* Board version at offset 1 */
203 #define PIXIS_PVER 0x2 /* PIXIS FPGA version at offset 2 */
204 #define PIXIS_CSR 0x3 /* PIXIS General control/status register */
205 #define PIXIS_RST 0x4 /* PIXIS Reset Control register */
206 #define PIXIS_PWR 0x5 /* PIXIS Power status register */
207 #define PIXIS_AUX 0x6 /* Auxiliary 1 register */
208 #define PIXIS_SPD 0x7 /* Register for SYSCLK speed */
209 #define PIXIS_AUX2 0x8 /* Auxiliary 2 register */
210 #define PIXIS_VCTL 0x10 /* VELA Control Register */
211 #define PIXIS_VSTAT 0x11 /* VELA Status Register */
212 #define PIXIS_VCFGEN0 0x12 /* VELA Config Enable 0 */
213 #define PIXIS_VCFGEN1 0x13 /* VELA Config Enable 1 */
214 #define PIXIS_VCORE0 0x14 /* VELA VCORE0 Register */
215 #define PIXIS_VBOOT 0x16 /* VELA VBOOT Register */
216 #define PIXIS_VSPEED0 0x17 /* VELA VSpeed 0 */
217 #define PIXIS_VSPEED1 0x18 /* VELA VSpeed 1 */
218 #define PIXIS_VSPEED2 0x19 /* VELA VSpeed 2 */
219 #define PIXIS_VSYSCLK0 0x1C /* VELA SYSCLK0 Register */
220 #define PIXIS_VSYSCLK1 0x1D /* VELA SYSCLK1 Register */
221 #define PIXIS_VSYSCLK2 0x1E /* VELA SYSCLK2 Register */
222 #define PIXIS_VDDRCLK0 0x1F /* VELA DDRCLK0 Register */
223 #define PIXIS_VDDRCLK1 0x20 /* VELA DDRCLK1 Register */
224 #define PIXIS_VDDRCLK2 0x21 /* VELA DDRCLK2 Register */
225 #define PIXIS_VWATCH 0x24 /* Watchdog Register */
226 #define PIXIS_LED 0x25 /* LED Register */
228 /* old pixis referenced names */
229 #define PIXIS_VCLKH 0x19 /* VELA VCLKH register */
230 #define PIXIS_VCLKL 0x1A /* VELA VCLKL register */
231 #define CONFIG_SYS_PIXIS_VBOOT_MASK 0xc0
232 #define PIXIS_VSPEED2_TSEC1SER 0x8
233 #define PIXIS_VSPEED2_TSEC2SER 0x4
234 #define PIXIS_VSPEED2_TSEC3SER 0x2
235 #define PIXIS_VSPEED2_TSEC4SER 0x1
236 #define PIXIS_VCFGEN1_TSEC1SER 0x20
237 #define PIXIS_VCFGEN1_TSEC2SER 0x20
238 #define PIXIS_VCFGEN1_TSEC3SER 0x20
239 #define PIXIS_VCFGEN1_TSEC4SER 0x20
240 #define PIXIS_VSPEED2_MASK (PIXIS_VSPEED2_TSEC1SER \
241 | PIXIS_VSPEED2_TSEC2SER \
242 | PIXIS_VSPEED2_TSEC3SER \
243 | PIXIS_VSPEED2_TSEC4SER)
244 #define PIXIS_VCFGEN1_MASK (PIXIS_VCFGEN1_TSEC1SER \
245 | PIXIS_VCFGEN1_TSEC2SER \
246 | PIXIS_VCFGEN1_TSEC3SER \
247 | PIXIS_VCFGEN1_TSEC4SER)
249 /* define to use L1 as initial stack */
250 #define CONFIG_L1_INIT_RAM
251 #define CONFIG_SYS_INIT_RAM_LOCK 1
252 #define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* Initial L1 address */
253 #define CONFIG_SYS_INIT_RAM_END 0x00004000 /* End of used area in RAM */
255 #define CONFIG_SYS_GBL_DATA_SIZE 128 /* num bytes initial data */
256 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
257 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
259 #define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */
260 #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */
262 /* Serial Port - controlled on board with jumper J8
266 #define CONFIG_CONS_INDEX 1
267 #undef CONFIG_SERIAL_SOFTWARE_FIFO
268 #define CONFIG_SYS_NS16550
269 #define CONFIG_SYS_NS16550_SERIAL
270 #define CONFIG_SYS_NS16550_REG_SIZE 1
271 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
273 #define CONFIG_SYS_BAUDRATE_TABLE \
274 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
276 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
277 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
279 /* Use the HUSH parser */
280 #define CONFIG_SYS_HUSH_PARSER
281 #ifdef CONFIG_SYS_HUSH_PARSER
282 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
286 * Pass open firmware flat tree
288 #define CONFIG_OF_LIBFDT 1
289 #define CONFIG_OF_BOARD_SETUP 1
290 #define CONFIG_OF_STDOUT_VIA_ALIAS 1
292 #define CONFIG_SYS_64BIT_VSPRINTF 1
293 #define CONFIG_SYS_64BIT_STRTOUL 1
295 /* new uImage format support */
297 #define CONFIG_FIT_VERBOSE 1 /* enable fit_format_{error,warning}() */
300 #define CONFIG_FSL_I2C /* Use FSL common I2C driver */
301 #define CONFIG_HARD_I2C /* I2C with hardware support */
302 #undef CONFIG_SOFT_I2C /* I2C bit-banged */
303 #define CONFIG_I2C_MULTI_BUS
304 #define CONFIG_I2C_CMD_TREE
305 #define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */
306 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
307 #define CONFIG_SYS_I2C_SLAVE 0x7F
308 #define CONFIG_SYS_I2C_NOPROBES {{0,0x29}}/* Don't probe these addrs */
309 #define CONFIG_SYS_I2C_OFFSET 0x3000
310 #define CONFIG_SYS_I2C2_OFFSET 0x3100
315 #define CONFIG_ID_EEPROM
316 #ifdef CONFIG_ID_EEPROM
317 #define CONFIG_SYS_I2C_EEPROM_NXID
319 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
320 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
321 #define CONFIG_SYS_EEPROM_BUS_NUM 1
325 * Memory space is mapped 1-1, but I/O space must start from 0.
328 /* PCI view of System Memory */
329 #define CONFIG_SYS_PCI_MEMORY_BUS 0x00000000
330 #define CONFIG_SYS_PCI_MEMORY_PHYS 0x00000000
331 #define CONFIG_SYS_PCI_MEMORY_SIZE 0x80000000
333 /* controller 3, direct to uli, tgtid 3, Base address 8000 */
334 #define CONFIG_SYS_PCIE3_MEM_BASE 0x80000000
335 #define CONFIG_SYS_PCIE3_MEM_PHYS CONFIG_SYS_PCIE3_MEM_BASE
336 #define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */
337 #define CONFIG_SYS_PCIE3_IO_BASE 0x00000000
338 #define CONFIG_SYS_PCIE3_IO_PHYS 0xffc00000
339 #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */
341 /* controller 2, Slot 2, tgtid 2, Base address 9000 */
342 #define CONFIG_SYS_PCIE2_MEM_BASE 0xa0000000
343 #define CONFIG_SYS_PCIE2_MEM_PHYS CONFIG_SYS_PCIE2_MEM_BASE
344 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */
345 #define CONFIG_SYS_PCIE2_IO_BASE 0x00000000
346 #define CONFIG_SYS_PCIE2_IO_PHYS 0xffc10000
347 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */
349 /* controller 1, Slot 1, tgtid 1, Base address a000 */
350 #define CONFIG_SYS_PCIE1_MEM_BASE 0xc0000000
351 #define CONFIG_SYS_PCIE1_MEM_PHYS CONFIG_SYS_PCIE1_MEM_BASE
352 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */
353 #define CONFIG_SYS_PCIE1_IO_BASE 0x00000000
354 #define CONFIG_SYS_PCIE1_IO_PHYS 0xffc20000
355 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
357 #if defined(CONFIG_PCI)
359 /*PCIE video card used*/
360 #define VIDEO_IO_OFFSET CONFIG_SYS_PCIE1_IO_PHYS
365 #if defined(CONFIG_VIDEO)
366 #define CONFIG_BIOSEMU
367 #define CONFIG_CFB_CONSOLE
368 #define CONFIG_VIDEO_SW_CURSOR
369 #define CONFIG_VGA_AS_SINGLE_DEVICE
370 #define CONFIG_ATI_RADEON_FB
371 #define CONFIG_VIDEO_LOGO
372 /*#define CONFIG_CONSOLE_CURSOR*/
373 #define CONFIG_SYS_ISA_IO_BASE_ADDRESS VIDEO_IO_OFFSET
376 #define CONFIG_NET_MULTI
377 #define CONFIG_PCI_PNP /* do pci plug-and-play */
379 #undef CONFIG_EEPRO100
381 #undef CONFIG_RTL8139
383 #ifdef CONFIG_RTL8139
384 /* This macro is used by RTL8139 but not defined in PPC architecture */
385 #define KSEG1ADDR(x) (x)
386 #define _IO_BASE 0x00000000
389 #ifndef CONFIG_PCI_PNP
390 #define PCI_ENET0_IOADDR CONFIG_SYS_PCIE3_IO_BASE
391 #define PCI_ENET0_MEMADDR CONFIG_SYS_PCIE3_IO_BASE
392 #define PCI_IDSEL_NUMBER 0x11 /* IDSEL = AD11 */
395 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
396 #define CONFIG_DOS_PARTITION
397 #define CONFIG_SCSI_AHCI
399 #ifdef CONFIG_SCSI_AHCI
400 #define CONFIG_SATA_ULI5288
401 #define CONFIG_SYS_SCSI_MAX_SCSI_ID 4
402 #define CONFIG_SYS_SCSI_MAX_LUN 1
403 #define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * CONFIG_SYS_SCSI_MAX_LUN)
404 #define CONFIG_SYS_SCSI_MAXDEVICE CONFIG_SYS_SCSI_MAX_DEVICE
407 #endif /* CONFIG_PCI */
410 #if defined(CONFIG_TSEC_ENET)
412 #ifndef CONFIG_NET_MULTI
413 #define CONFIG_NET_MULTI 1
416 #define CONFIG_MII 1 /* MII PHY management */
417 #define CONFIG_MII_DEFAULT_TSEC 1 /* Allow unregistered phys */
418 #define CONFIG_TSEC1 1
419 #define CONFIG_TSEC1_NAME "eTSEC1"
420 #define CONFIG_TSEC2 1
421 #define CONFIG_TSEC2_NAME "eTSEC2"
422 #define CONFIG_TSEC3 1
423 #define CONFIG_TSEC3_NAME "eTSEC3"
424 #define CONFIG_TSEC4 1
425 #define CONFIG_TSEC4_NAME "eTSEC4"
427 #define CONFIG_PIXIS_SGMII_CMD
428 #define CONFIG_FSL_SGMII_RISER 1
429 #define SGMII_RISER_PHY_OFFSET 0x1c
431 #ifdef CONFIG_FSL_SGMII_RISER
432 #define CONFIG_SYS_TBIPA_VALUE 0x10 /* avoid conflict with eTSEC4 paddr */
435 #define TSEC1_PHY_ADDR 0
436 #define TSEC2_PHY_ADDR 1
437 #define TSEC3_PHY_ADDR 2
438 #define TSEC4_PHY_ADDR 3
440 #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
441 #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
442 #define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
443 #define TSEC4_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
445 #define TSEC1_PHYIDX 0
446 #define TSEC2_PHYIDX 0
447 #define TSEC3_PHYIDX 0
448 #define TSEC4_PHYIDX 0
450 #define CONFIG_ETHPRIME "eTSEC1"
452 #define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */
453 #endif /* CONFIG_TSEC_ENET */
458 #define CONFIG_ENV_IS_IN_FLASH 1
459 #if CONFIG_SYS_MONITOR_BASE > 0xfff80000
460 #define CONFIG_ENV_ADDR 0xfff80000
462 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + 0x70000)
464 #define CONFIG_ENV_SIZE 0x2000
465 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */
467 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
468 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
471 * Command line configuration.
473 #include <config_cmd_default.h>
475 #define CONFIG_CMD_IRQ
476 #define CONFIG_CMD_PING
477 #define CONFIG_CMD_I2C
478 #define CONFIG_CMD_MII
479 #define CONFIG_CMD_ELF
480 #define CONFIG_CMD_IRQ
481 #define CONFIG_CMD_SETEXPR
483 #if defined(CONFIG_PCI)
484 #define CONFIG_CMD_PCI
485 #define CONFIG_CMD_BEDBUG
486 #define CONFIG_CMD_NET
487 #define CONFIG_CMD_SCSI
488 #define CONFIG_CMD_EXT2
491 #undef CONFIG_WATCHDOG /* watchdog disabled */
494 * Miscellaneous configurable options
496 #define CONFIG_SYS_LONGHELP /* undef to save memory */
497 #define CONFIG_CMDLINE_EDITING /* Command-line editing */
498 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
499 #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
500 #if defined(CONFIG_CMD_KGDB)
501 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
503 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
505 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
506 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */
507 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
508 #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */
511 * For booting Linux, the board info and command line data
512 * have to be in the first 8 MB of memory, since this is
513 * the maximum mapped by the Linux kernel during initialization.
515 #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/
518 * Internal Definitions
522 #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
523 #define BOOTFLAG_WARM 0x02 /* Software reboot */
525 #if defined(CONFIG_CMD_KGDB)
526 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
527 #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
531 * Environment Configuration
534 /* The mac addresses for all ethernet interface */
535 #if defined(CONFIG_TSEC_ENET)
536 #define CONFIG_HAS_ETH0
537 #define CONFIG_ETHADDR 00:E0:0C:02:00:FD
538 #define CONFIG_HAS_ETH1
539 #define CONFIG_ETH1ADDR 00:E0:0C:02:01:FD
540 #define CONFIG_HAS_ETH2
541 #define CONFIG_ETH2ADDR 00:E0:0C:02:02:FD
542 #define CONFIG_HAS_ETH3
543 #define CONFIG_ETH3ADDR 00:E0:0C:02:03:FD
546 #define CONFIG_IPADDR 192.168.1.254
548 #define CONFIG_HOSTNAME unknown
549 #define CONFIG_ROOTPATH /opt/nfsroot
550 #define CONFIG_BOOTFILE uImage
551 #define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */
553 #define CONFIG_SERVERIP 192.168.1.1
554 #define CONFIG_GATEWAYIP 192.168.1.1
555 #define CONFIG_NETMASK 255.255.255.0
557 /* default location for tftp and bootm */
558 #define CONFIG_LOADADDR 1000000
560 #define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */
561 #undef CONFIG_BOOTARGS /* the boot command will set bootargs */
563 #define CONFIG_BAUDRATE 115200
565 #define CONFIG_EXTRA_ENV_SETTINGS \
566 "memctl_intlv_ctl=2\0" \
568 "uboot=" MK_STR(CONFIG_UBOOTPATH) "\0" \
569 "tftpflash=tftpboot $loadaddr $uboot; " \
570 "protect off " MK_STR(TEXT_BASE) " +$filesize; " \
571 "erase " MK_STR(TEXT_BASE) " +$filesize; " \
572 "cp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize; " \
573 "protect on " MK_STR(TEXT_BASE) " +$filesize; " \
574 "cmp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize\0" \
575 "consoledev=ttyS0\0" \
576 "ramdiskaddr=2000000\0" \
577 "ramdiskfile=8572ds/ramdisk.uboot\0" \
579 "fdtfile=8572ds/mpc8572ds.dtb\0" \
582 #define CONFIG_HDBOOT \
583 "setenv bootargs root=/dev/$bdev rw " \
584 "console=$consoledev,$baudrate $othbootargs;" \
585 "tftp $loadaddr $bootfile;" \
586 "tftp $fdtaddr $fdtfile;" \
587 "bootm $loadaddr - $fdtaddr"
589 #define CONFIG_NFSBOOTCOMMAND \
590 "setenv bootargs root=/dev/nfs rw " \
591 "nfsroot=$serverip:$rootpath " \
592 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
593 "console=$consoledev,$baudrate $othbootargs;" \
594 "tftp $loadaddr $bootfile;" \
595 "tftp $fdtaddr $fdtfile;" \
596 "bootm $loadaddr - $fdtaddr"
598 #define CONFIG_RAMBOOTCOMMAND \
599 "setenv bootargs root=/dev/ram rw " \
600 "console=$consoledev,$baudrate $othbootargs;" \
601 "tftp $ramdiskaddr $ramdiskfile;" \
602 "tftp $loadaddr $bootfile;" \
603 "tftp $fdtaddr $fdtfile;" \
604 "bootm $loadaddr $ramdiskaddr $fdtaddr"
606 #define CONFIG_BOOTCOMMAND CONFIG_HDBOOT
608 #endif /* __CONFIG_H */