2 * Copyright 2007 Freescale Semiconductor, Inc.
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * Version 2 as published by the Free Software Foundation.
10 * MPC8610HPCD board configuration file
16 /* High Level Configuration Options */
17 #define CONFIG_MPC86xx 1 /* MPC86xx */
18 #define CONFIG_MPC8610 1 /* MPC8610 specific */
19 #define CONFIG_MPC8610HPCD 1 /* MPC8610HPCD board specific */
20 #define CONFIG_NUM_CPUS 1 /* Number of CPUs in the system */
21 #define CONFIG_LINUX_RESET_VEC 0x100 /* Reset vector used by Linux */
23 #define CONFIG_FSL_DIU_FB 1 /* FSL DIU */
28 #if defined(CONFIG_VIDEO)
29 #define CONFIG_CFB_CONSOLE
30 #define CONFIG_VGA_AS_SINGLE_DEVICE
34 #define CFG_DIAG_ADDR 0xff800000
37 #define CFG_RESET_ADDRESS 0xfff00100
39 #define CONFIG_PCI 1 /* Enable PCI/PCIE*/
40 #define CONFIG_PCI1 1 /* PCI controler 1 */
41 #define CONFIG_PCIE1 1 /* PCIe 1 connected to ULI bridge */
42 #define CONFIG_PCIE2 1 /* PCIe 2 connected to slot */
43 #define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */
44 #define CONFIG_FSL_LAW 1 /* Use common FSL init code */
46 #define CONFIG_ENV_OVERWRITE
47 #define CONFIG_INTERRUPTS /* enable pci, srio, ddr interrupts */
49 #define CONFIG_HIGH_BATS 1 /* High BATs supported & enabled */
50 #define CONFIG_ALTIVEC 1
53 * L2CR setup -- make sure this is right for your board!
57 #define L2_ENABLE (L2CR_L2E |0x00100000 )
59 #ifndef CONFIG_SYS_CLK_FREQ
60 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk(0)
63 #define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */
64 #define CONFIG_MISC_INIT_R 1
66 #define CFG_MEMTEST_START 0x00200000 /* memtest region */
67 #define CFG_MEMTEST_END 0x00400000
70 * Base addresses -- Note these are effective addresses where the
71 * actual resources get mapped (not physical addresses)
73 #define CFG_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */
74 #define CFG_CCSRBAR 0xe0000000 /* relocated CCSRBAR */
75 #define CFG_IMMR CFG_CCSRBAR /* PQII uses CFG_IMMR */
77 #define CFG_PCI1_ADDR (CFG_CCSRBAR+0x8000)
78 #define CFG_PCIE1_ADDR (CFG_CCSRBAR+0xa000)
79 #define CFG_PCIE2_ADDR (CFG_CCSRBAR+0x9000)
81 #define CFG_DIU_ADDR (CFG_CCSRBAR+0x2c000)
84 #define CONFIG_FSL_DDR2
85 #undef CONFIG_FSL_DDR_INTERACTIVE
86 #define CONFIG_SPD_EEPROM /* Use SPD for DDR */
87 #define CONFIG_DDR_SPD
89 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */
90 #define CONFIG_MEM_INIT_VALUE 0xDeadBeef
92 #define CFG_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/
93 #define CFG_SDRAM_BASE CFG_DDR_SDRAM_BASE
94 #define CONFIG_VERY_BIG_RAM
96 #define MPC86xx_DDR_SDRAM_CLK_CNTL
98 #define CONFIG_NUM_DDR_CONTROLLERS 1
99 #define CONFIG_DIMM_SLOTS_PER_CTLR 1
100 #define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
102 #define SPD_EEPROM_ADDRESS1 0x51 /* CTLR 0 DIMM 0 */
104 /* These are used when DDR doesn't use SPD. */
105 #define CFG_SDRAM_SIZE 256 /* DDR is 256MB */
108 #define CFG_DDR_CS0_BNDS 0x0000000F
109 #define CFG_DDR_CS0_CONFIG 0x80010202 /* Enable, no interleaving */
110 #define CFG_DDR_TIMING_3 0x00000000
111 #define CFG_DDR_TIMING_0 0x00260802
112 #define CFG_DDR_TIMING_1 0x3935d322
113 #define CFG_DDR_TIMING_2 0x14904cc8
114 #define CFG_DDR_MODE_1 0x00480432
115 #define CFG_DDR_MODE_2 0x00000000
116 #define CFG_DDR_INTERVAL 0x06180100
117 #define CFG_DDR_DATA_INIT 0xdeadbeef
118 #define CFG_DDR_CLK_CTRL 0x03800000
119 #define CFG_DDR_OCD_CTRL 0x00000000
120 #define CFG_DDR_OCD_STATUS 0x00000000
121 #define CFG_DDR_CONTROL 0xe3008000 /* Type = DDR2 */
122 #define CFG_DDR_CONTROL2 0x04400010
124 #define CFG_DDR_ERR_INT_EN 0x00000000
125 #define CFG_DDR_ERR_DIS 0x00000000
126 #define CFG_DDR_SBE 0x000f0000
129 * FIXME: Not used in fixed_sdram function
131 #define CFG_DDR_MODE 0x00000022
132 #define CFG_DDR_CS1_BNDS 0x00000000
133 #define CFG_DDR_CS2_BNDS 0x00000FFF /* Not done */
134 #define CFG_DDR_CS3_BNDS 0x00000FFF /* Not done */
135 #define CFG_DDR_CS4_BNDS 0x00000FFF /* Not done */
136 #define CFG_DDR_CS5_BNDS 0x00000FFF /* Not done */
140 #define CONFIG_ID_EEPROM
141 #define CFG_I2C_EEPROM_NXID
142 #define CFG_ID_EEPROM
143 #define CFG_I2C_EEPROM_ADDR 0x57
144 #define CFG_I2C_EEPROM_ADDR_LEN 1
147 #define CFG_FLASH_BASE 0xf0000000 /* start of FLASH 128M */
148 #define CFG_FLASH_BASE2 0xf8000000
150 #define CFG_FLASH_BANKS_LIST {CFG_FLASH_BASE, CFG_FLASH_BASE2}
152 #define CFG_BR0_PRELIM 0xf8001001 /* port size 16bit */
153 #define CFG_OR0_PRELIM 0xf8006e65 /* 128MB NOR Flash*/
155 #define CFG_BR1_PRELIM 0xf0001001 /* port size 16bit */
156 #define CFG_OR1_PRELIM 0xf8006e65 /* 128MB Promjet */
158 #define CFG_BR2_PRELIM 0xf0000000
159 #define CFG_OR2_PRELIM 0xf0000000 /* 256MB NAND Flash - bank 1 */
161 #define CFG_BR3_PRELIM 0xe8000801 /* port size 8bit */
162 #define CFG_OR3_PRELIM 0xfff06ff7 /* 1MB PIXIS area*/
165 #define CONFIG_FSL_PIXIS 1 /* use common PIXIS code */
166 #define PIXIS_BASE 0xe8000000 /* PIXIS registers */
167 #define PIXIS_ID 0x0 /* Board ID at offset 0 */
168 #define PIXIS_VER 0x1 /* Board version at offset 1 */
169 #define PIXIS_PVER 0x2 /* PIXIS FPGA version at offset 2 */
170 #define PIXIS_RST 0x4 /* PIXIS Reset Control register */
171 #define PIXIS_AUX 0x6 /* PIXIS Auxiliary register; Scratch */
172 #define PIXIS_SPD 0x7 /* Register for SYSCLK speed */
173 #define PIXIS_BRDCFG0 0x8 /* PIXIS Board Configuration Register0*/
174 #define PIXIS_VCTL 0x10 /* VELA Control Register */
175 #define PIXIS_VCFGEN0 0x12 /* VELA Config Enable 0 */
176 #define PIXIS_VCFGEN1 0x13 /* VELA Config Enable 1 */
177 #define PIXIS_VBOOT 0x16 /* VELA VBOOT Register */
178 #define PIXIS_VSPEED0 0x17 /* VELA VSpeed 0 */
179 #define PIXIS_VSPEED1 0x18 /* VELA VSpeed 1 */
180 #define PIXIS_VCLKH 0x19 /* VELA VCLKH register */
181 #define PIXIS_VCLKL 0x1A /* VELA VCLKL register */
182 #define CFG_PIXIS_VBOOT_MASK 0x0C /* Reset altbank mask*/
184 #define CFG_MAX_FLASH_BANKS 2 /* number of banks */
185 #define CFG_MAX_FLASH_SECT 1024 /* sectors per device */
187 #undef CFG_FLASH_CHECKSUM
188 #define CFG_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
189 #define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
190 #define CFG_MONITOR_BASE TEXT_BASE /* start of monitor */
192 #define CONFIG_FLASH_CFI_DRIVER
193 #define CFG_FLASH_CFI
194 #define CFG_FLASH_EMPTY_INFO
196 #if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
202 #if defined(CFG_RAMBOOT)
203 #undef CONFIG_SPD_EEPROM
204 #define CFG_SDRAM_SIZE 256
207 #undef CONFIG_CLOCKS_IN_MHZ
209 #define CONFIG_L1_INIT_RAM
210 #define CFG_INIT_RAM_LOCK 1
211 #ifndef CFG_INIT_RAM_LOCK
212 #define CFG_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */
214 #define CFG_INIT_RAM_ADDR 0xe4000000 /* Initial RAM address */
216 #define CFG_INIT_RAM_END 0x4000 /* End of used area in RAM */
218 #define CFG_GBL_DATA_SIZE 128 /* num bytes initial data */
219 #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
220 #define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
222 #define CFG_MONITOR_LEN (512 * 1024) /* Reserve 512 KB for Mon */
223 #define CFG_MALLOC_LEN (6 * 1024 * 1024) /* Reserved for malloc */
226 #define CONFIG_CONS_INDEX 1
227 #undef CONFIG_SERIAL_SOFTWARE_FIFO
229 #define CFG_NS16550_SERIAL
230 #define CFG_NS16550_REG_SIZE 1
231 #define CFG_NS16550_CLK get_bus_freq(0)
233 #define CFG_BAUDRATE_TABLE \
234 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
236 #define CFG_NS16550_COM1 (CFG_CCSRBAR+0x4500)
237 #define CFG_NS16550_COM2 (CFG_CCSRBAR+0x4600)
239 /* Use the HUSH parser */
240 #define CFG_HUSH_PARSER
241 #ifdef CFG_HUSH_PARSER
242 #define CFG_PROMPT_HUSH_PS2 "> "
246 * Pass open firmware flat tree to kernel
248 #define CONFIG_OF_LIBFDT 1
249 #define CONFIG_OF_BOARD_SETUP 1
250 #define CONFIG_OF_STDOUT_VIA_ALIAS 1
253 /* maximum size of the flat tree (8K) */
254 #define OF_FLAT_TREE_MAX_SIZE 8192
256 #define CFG_64BIT_VSPRINTF 1
257 #define CFG_64BIT_STRTOUL 1
262 #define CONFIG_FSL_I2C /* Use FSL common I2C driver */
263 #define CONFIG_HARD_I2C /* I2C with hardware support*/
264 #undef CONFIG_SOFT_I2C /* I2C bit-banged */
265 #define CFG_I2C_SPEED 400000 /* I2C speed and slave address */
266 #define CFG_I2C_SLAVE 0x7F
267 #define CFG_I2C_NOPROBES {0x69} /* Don't probe these addrs */
268 #define CFG_I2C_OFFSET 0x3000
272 * Addresses are mapped 1-1.
274 #define CFG_PCI1_MEM_BASE 0x80000000
275 #define CFG_PCI1_MEM_PHYS CFG_PCI1_MEM_BASE
276 #define CFG_PCI1_MEM_SIZE 0x10000000 /* 256M */
277 #define CFG_PCI1_IO_BASE 0x00000000
278 #define CFG_PCI1_IO_PHYS 0xe1000000
279 #define CFG_PCI1_IO_SIZE 0x00100000 /* 1M */
281 /* PCI view of System Memory */
282 #define CFG_PCI_MEMORY_BUS 0x00000000
283 #define CFG_PCI_MEMORY_PHYS 0x00000000
284 #define CFG_PCI_MEMORY_SIZE 0x80000000
287 #define KSEG1ADDR(x) ({u32 _x = le32_to_cpu(*(u32 *)(x)); (&_x); })
288 #define _IO_BASE 0x00000000
290 /* controller 1, Base address 0xa000 */
291 #define CFG_PCIE1_MEM_BASE 0xa0000000
292 #define CFG_PCIE1_MEM_PHYS CFG_PCIE1_MEM_BASE
293 #define CFG_PCIE1_MEM_SIZE 0x10000000 /* 256M */
294 #define CFG_PCIE1_IO_BASE 0x00000000
295 #define CFG_PCIE1_IO_PHYS 0xe3000000
296 #define CFG_PCIE1_IO_SIZE 0x00100000 /* 1M */
298 /* controller 2, Base Address 0x9000 */
299 #define CFG_PCIE2_MEM_BASE 0x90000000
300 #define CFG_PCIE2_MEM_PHYS CFG_PCIE2_MEM_BASE
301 #define CFG_PCIE2_MEM_SIZE 0x10000000 /* 256M */
302 #define CFG_PCIE2_IO_BASE 0x00000000 /* reuse mem LAW */
303 #define CFG_PCIE2_IO_PHYS 0xe2000000
304 #define CFG_PCIE2_IO_SIZE 0x00100000 /* 1M */
307 #if defined(CONFIG_PCI)
309 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
311 #define CONFIG_NET_MULTI
312 #define CONFIG_CMD_NET
313 #define CONFIG_PCI_PNP /* do pci plug-and-play */
314 #define CONFIG_CMD_REGINFO
316 #define CONFIG_ULI526X
317 #ifdef CONFIG_ULI526X
318 #define CONFIG_ETHADDR 00:E0:0C:00:00:01
321 /************************************************************
323 ************************************************************/
324 #define CONFIG_PCI_OHCI 1
325 #define CONFIG_USB_OHCI_NEW 1
326 #define CONFIG_USB_KEYBOARD 1
327 #define CFG_DEVICE_DEREGISTER
328 #define CFG_USB_EVENT_POLL 1
329 #define CFG_USB_OHCI_SLOT_NAME "ohci_pci"
330 #define CFG_USB_OHCI_MAX_ROOT_PORTS 15
331 #define CFG_OHCI_SWAP_REG_ACCESS 1
333 #if !defined(CONFIG_PCI_PNP)
334 #define PCI_ENET0_IOADDR 0xe0000000
335 #define PCI_ENET0_MEMADDR 0xe0000000
336 #define PCI_IDSEL_NUMBER 0x0c /* slot0->3(IDSEL)=12->15 */
339 #define CONFIG_DOS_PARTITION
340 #define CONFIG_SCSI_AHCI
342 #ifdef CONFIG_SCSI_AHCI
343 #define CONFIG_SATA_ULI5288
344 #define CFG_SCSI_MAX_SCSI_ID 4
345 #define CFG_SCSI_MAX_LUN 1
346 #define CFG_SCSI_MAX_DEVICE (CFG_SCSI_MAX_SCSI_ID * CFG_SCSI_MAX_LUN)
347 #define CFG_SCSI_MAXDEVICE CFG_SCSI_MAX_DEVICE
350 #endif /* CONFIG_PCI */
353 * BAT0 2G Cacheable, non-guarded
356 #define CFG_DBAT0L (BATL_PP_RW | BATL_MEMCOHERENCE)
357 #define CFG_DBAT0U (BATU_BL_2G | BATU_VS | BATU_VP)
358 #define CFG_IBAT0L (BATL_PP_RW | BATL_MEMCOHERENCE )
359 #define CFG_IBAT0U CFG_DBAT0U
362 * BAT1 1G Cache-inhibited, guarded
363 * 0x8000_0000 256M PCI-1 Memory
364 * 0xa000_0000 256M PCI-Express 1 Memory
365 * 0x9000_0000 256M PCI-Express 2 Memory
368 #define CFG_DBAT1L (CFG_PCI1_MEM_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT \
369 | BATL_GUARDEDSTORAGE)
370 #define CFG_DBAT1U (CFG_PCI1_MEM_PHYS | BATU_BL_1G | BATU_VS | BATU_VP)
371 #define CFG_IBAT1L (CFG_PCI1_MEM_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT)
372 #define CFG_IBAT1U CFG_DBAT1U
375 * BAT2 16M Cache-inhibited, guarded
376 * 0xe100_0000 1M PCI-1 I/O
379 #define CFG_DBAT2L (CFG_PCI1_IO_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT \
380 | BATL_GUARDEDSTORAGE)
381 #define CFG_DBAT2U (CFG_PCI1_IO_PHYS | BATU_BL_16M | BATU_VS | BATU_VP)
382 #define CFG_IBAT2L (CFG_PCI1_IO_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT)
383 #define CFG_IBAT2U CFG_DBAT2U
386 * BAT3 32M Cache-inhibited, guarded
387 * 0xe200_0000 1M PCI-Express 2 I/O
388 * 0xe300_0000 1M PCI-Express 1 I/O
391 #define CFG_DBAT3L (CFG_PCIE2_IO_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT \
392 | BATL_GUARDEDSTORAGE)
393 #define CFG_DBAT3U (CFG_PCIE2_IO_PHYS | BATU_BL_32M | BATU_VS | BATU_VP)
394 #define CFG_IBAT3L (CFG_PCIE2_IO_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT)
395 #define CFG_IBAT3U CFG_DBAT3U
398 * BAT4 4M Cache-inhibited, guarded
399 * 0xe000_0000 4M CCSR
401 #define CFG_DBAT4L (CFG_CCSRBAR | BATL_PP_RW | BATL_CACHEINHIBIT \
402 | BATL_GUARDEDSTORAGE)
403 #define CFG_DBAT4U (CFG_CCSRBAR | BATU_BL_1M | BATU_VS | BATU_VP)
404 #define CFG_IBAT4L (CFG_CCSRBAR | BATL_PP_RW | BATL_CACHEINHIBIT)
405 #define CFG_IBAT4U CFG_DBAT4U
408 * BAT5 128K Cacheable, non-guarded
409 * 0xe400_0000 128K Init RAM for stack in the CPU DCache (no backing memory)
411 #define CFG_DBAT5L (CFG_INIT_RAM_ADDR | BATL_PP_RW | BATL_MEMCOHERENCE)
412 #define CFG_DBAT5U (CFG_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP)
413 #define CFG_IBAT5L CFG_DBAT5L
414 #define CFG_IBAT5U CFG_DBAT5U
417 * BAT6 256M Cache-inhibited, guarded
418 * 0xf000_0000 256M FLASH
420 #define CFG_DBAT6L (CFG_FLASH_BASE | BATL_PP_RW | BATL_CACHEINHIBIT \
421 | BATL_GUARDEDSTORAGE)
422 #define CFG_DBAT6U (CFG_FLASH_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
423 #define CFG_IBAT6L (CFG_FLASH_BASE | BATL_PP_RW | BATL_MEMCOHERENCE)
424 #define CFG_IBAT6U CFG_DBAT6U
427 * BAT7 4M Cache-inhibited, guarded
428 * 0xe800_0000 4M PIXIS
430 #define CFG_DBAT7L (PIXIS_BASE | BATL_PP_RW | BATL_CACHEINHIBIT \
431 | BATL_GUARDEDSTORAGE)
432 #define CFG_DBAT7U (PIXIS_BASE | BATU_BL_1M | BATU_VS | BATU_VP)
433 #define CFG_IBAT7L (PIXIS_BASE | BATL_PP_RW | BATL_CACHEINHIBIT)
434 #define CFG_IBAT7U CFG_DBAT7U
441 #define CFG_ENV_IS_IN_FLASH 1
442 #define CFG_ENV_ADDR (CFG_MONITOR_BASE + CFG_MONITOR_LEN)
443 #define CFG_ENV_SECT_SIZE 0x20000 /* 126k (one sector) for env */
444 #define CFG_ENV_SIZE 0x2000
446 #define CFG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */
447 #define CFG_ENV_ADDR (CFG_MONITOR_BASE - 0x1000)
448 #define CFG_ENV_SIZE 0x2000
451 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
452 #define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
458 #define CONFIG_BOOTP_BOOTFILESIZE
459 #define CONFIG_BOOTP_BOOTPATH
460 #define CONFIG_BOOTP_GATEWAY
461 #define CONFIG_BOOTP_HOSTNAME
465 * Command line configuration.
467 #include <config_cmd_default.h>
469 #define CONFIG_CMD_PING
470 #define CONFIG_CMD_I2C
471 #define CONFIG_CMD_MII
473 #if defined(CFG_RAMBOOT)
474 #undef CONFIG_CMD_ENV
477 #if defined(CONFIG_PCI)
478 #define CONFIG_CMD_PCI
479 #define CONFIG_CMD_SCSI
480 #define CONFIG_CMD_EXT2
481 #define CONFIG_CMD_USB
485 #define CONFIG_WATCHDOG /* watchdog enabled */
486 #define CFG_WATCHDOG_FREQ 5000 /* Feed interval, 5s */
488 /*DIU Configuration*/
489 #define DIU_CONNECT_TO_DVI /* DIU controller connects to DVI encoder*/
492 * Miscellaneous configurable options
494 #define CFG_LONGHELP /* undef to save memory */
495 #define CONFIG_CMDLINE_EDITING /* Command-line editing */
496 #define CFG_LOAD_ADDR 0x2000000 /* default load address */
497 #define CFG_PROMPT "=> " /* Monitor Command Prompt */
499 #if defined(CONFIG_CMD_KGDB)
500 #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
502 #define CFG_CBSIZE 256 /* Console I/O Buffer Size */
505 #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
506 #define CFG_MAXARGS 16 /* max number of command args */
507 #define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
508 #define CFG_HZ 1000 /* decrementer freq: 1ms ticks */
511 * For booting Linux, the board info and command line data
512 * have to be in the first 8 MB of memory, since this is
513 * the maximum mapped by the Linux kernel during initialization.
515 #define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/
518 * Internal Definitions
522 #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
523 #define BOOTFLAG_WARM 0x02 /* Software reboot */
525 #if defined(CONFIG_CMD_KGDB)
526 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
527 #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
531 * Environment Configuration
533 #define CONFIG_IPADDR 192.168.1.100
535 #define CONFIG_HOSTNAME unknown
536 #define CONFIG_ROOTPATH /opt/nfsroot
537 #define CONFIG_BOOTFILE uImage
538 #define CONFIG_UBOOTPATH 8610hpcd/u-boot.bin
540 #define CONFIG_SERVERIP 192.168.1.1
541 #define CONFIG_GATEWAYIP 192.168.1.1
542 #define CONFIG_NETMASK 255.255.255.0
544 /* default location for tftp and bootm */
545 #define CONFIG_LOADADDR 1000000
547 #define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */
548 #undef CONFIG_BOOTARGS /* the boot command will set bootargs */
550 #define CONFIG_BAUDRATE 115200
552 #if defined(CONFIG_PCI1)
554 "pcireg=md ${a}000 3; echo o;md ${a}c00 25; echo i; md ${a}da0 15;" \
555 "echo e;md ${a}e00 9\0" \
556 "pci1regs=setenv a e0008; run pcireg\0" \
557 "pcierr=md ${a}e00 8; pci d.b $b.0 7 1; pci d.w $b.0 1e 1;" \
558 "pci d.w $b.0 56 1\0" \
559 "pcierrc=mw ${a}e00 ffffffff; pci w.b $b.0 7 ff; pci w.w $b.0 1e ffff;" \
560 "pci w.w $b.0 56 ffff\0" \
561 "pci1err=setenv a e0008; run pcierr\0" \
562 "pci1errc=setenv a e0008; run pcierrc\0"
567 #if defined(CONFIG_PCIE1) || defined(CONFIG_PCIE2)
569 "pciereg=md ${a}000 6; md ${a}020 4; md ${a}bf8 2; echo o;md ${a}c00 25;" \
570 "echo i; md ${a}da0 15; echo e;md ${a}e00 e; echo d; md ${a}f00 c\0" \
571 "pcie1regs=setenv a e000a; run pciereg\0" \
572 "pcie2regs=setenv a e0009; run pciereg\0" \
573 "pcieerr=md ${a}020 1; md ${a}e00; pci d.b $b.0 7 1; pci d.w $b.0 1e 1;"\
574 "pci d.w $b.0 56 1; pci d $b.0 104 1; pci d $b.0 110 1;" \
575 "pci d $b.0 130 1\0" \
576 "pcieerrc=mw ${a}020 ffffffff; mw ${a}e00 ffffffff; pci w.b $b.0 7 ff;"\
577 "pci w.w $b.0 1e ffff; pci w.w $b.0 56 ffff; pci w $b.0 104 ffffffff;" \
578 "pci w $b.0 110 ffffffff; pci w $b.0 130 ffffffff\0" \
579 "pciecfg=pci d $b.0 0 20; pci d $b.0 100 e; pci d $b.0 400 69\0" \
580 "pcie1err=setenv a e000a; run pcieerr\0" \
581 "pcie2err=setenv a e0009; run pcieerr\0" \
582 "pcie1errc=setenv a e000a; run pcieerrc\0" \
583 "pcie2errc=setenv a e0009; run pcieerrc\0"
589 "dma0=mw ${d}104 ffffffff;mw ${d}110 50000;mw ${d}114 $sad0;mw ${d}118 50000;"\
590 "mw ${d}120 $bc0;mw ${d}100 f03c404; mw ${d}11c $dad0; md ${d}100 9\0" \
591 "dma1=mw ${d}184 ffffffff;mw ${d}190 50000;mw ${d}194 $sad1;mw ${d}198 50000;"\
592 "mw ${d}1a0 $bc1;mw ${d}180 f03c404; mw ${d}19c $dad1; md ${d}180 9\0" \
593 "dma2=mw ${d}204 ffffffff;mw ${d}210 50000;mw ${d}214 $sad2;mw ${d}218 50000;"\
594 "mw ${d}220 $bc2;mw ${d}200 f03c404; mw ${d}21c $dad2; md ${d}200 9\0" \
595 "dma3=mw ${d}284 ffffffff;mw ${d}290 50000;mw ${d}294 $sad3;mw ${d}298 50000;"\
596 "mw ${d}2a0 $bc3;mw ${d}280 f03c404; mw ${d}29c $dad3; md ${d}280 9\0"
599 #define CONFIG_EXTRA_ENV_SETTINGS \
601 "uboot=" MK_STR(CONFIG_UBOOTPATH) "\0" \
602 "tftpflash=tftpboot $loadaddr $uboot; " \
603 "protect off " MK_STR(TEXT_BASE) " +$filesize; " \
604 "erase " MK_STR(TEXT_BASE) " +$filesize; " \
605 "cp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize; " \
606 "protect on " MK_STR(TEXT_BASE) " +$filesize; " \
607 "cmp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize\0" \
608 "consoledev=ttyS0\0" \
609 "ramdiskaddr=2000000\0" \
610 "ramdiskfile=8610hpcd/ramdisk.uboot\0" \
612 "fdtfile=8610hpcd/mpc8610_hpcd.dtb\0" \
614 "en-wd=mw.b f8100010 0x08; echo -expect:- 08; md.b f8100010 1\0" \
615 "dis-wd=mw.b f8100010 0x00; echo -expect:- 00; md.b f8100010 1\0" \
617 "eoi=mw e00400b0 0\0" \
618 "iack=md e00400a0 1\0" \
619 "ddrreg=md ${a}000 8; md ${a}080 8;md ${a}100 d; md ${a}140 4;" \
620 "md ${a}bf0 4; md ${a}e00 3; md ${a}e20 3; md ${a}e40 7;" \
622 "ddr1regs=setenv a e0002; run ddrreg\0" \
623 "gureg=md ${a}000 2c; md ${a}0b0 1; md ${a}0c0 1; md ${a}800 1;" \
624 "md ${a}900 6; md ${a}a00 1; md ${a}b20 3; md ${a}e00 1;" \
625 "md ${a}e60 1; md ${a}ef0 1d\0" \
626 "guregs=setenv a e00e0; run gureg\0" \
627 "mcmreg=md ${a}000 1b; md ${a}bf8 2; md ${a}e00 5\0" \
628 "mcmregs=setenv a e0001; run mcmreg\0" \
629 "diuregs=md e002c000 1d\0" \
630 "dium=mw e002c01c\0" \
631 "diuerr=md e002c014 1\0" \
632 "othbootargs=diufb=15M video=fslfb:1280x1024-32@60,monitor=0 debug\0" \
634 "pmregs=md e00e1000 2b\0" \
635 "lawregs=md e0000c08 4b\0" \
636 "lbcregs=md e0005000 36\0" \
637 "dma0regs=md e0021100 12\0" \
638 "dma1regs=md e0021180 12\0" \
639 "dma2regs=md e0021200 12\0" \
640 "dma3regs=md e0021280 12\0" \
645 #define CONFIG_EXTRA_ENV_SETTINGS \
647 "uboot=" MK_STR(CONFIG_UBOOTPATH) "\0" \
648 "consoledev=ttyS0\0" \
649 "ramdiskaddr=2000000\0" \
650 "ramdiskfile=8610hpcd/ramdisk.uboot\0" \
652 "fdtfile=8610hpcd/mpc8610_hpcd.dtb\0" \
654 "othbootargs=diufb=15M video=fslfb:1280x1024-32@60,monitor=0\0"\
658 #define CONFIG_NFSBOOTCOMMAND \
659 "setenv bootargs root=/dev/nfs rw " \
660 "nfsroot=$serverip:$rootpath " \
661 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
662 "console=$consoledev,$baudrate $othbootargs;" \
663 "tftp $loadaddr $bootfile;" \
664 "tftp $fdtaddr $fdtfile;" \
665 "bootm $loadaddr - $fdtaddr"
667 #define CONFIG_RAMBOOTCOMMAND \
668 "setenv bootargs root=/dev/ram rw " \
669 "console=$consoledev,$baudrate $othbootargs;" \
670 "tftp $ramdiskaddr $ramdiskfile;" \
671 "tftp $loadaddr $bootfile;" \
672 "tftp $fdtaddr $fdtfile;" \
673 "bootm $loadaddr $ramdiskaddr $fdtaddr"
675 #define CONFIG_BOOTCOMMAND \
676 "setenv bootargs root=/dev/$bdev rw " \
677 "console=$consoledev,$baudrate $othbootargs;" \
678 "tftp $loadaddr $bootfile;" \
679 "tftp $fdtaddr $fdtfile;" \
680 "bootm $loadaddr - $fdtaddr"
682 #endif /* __CONFIG_H */
projects / u-boot / blob