2 * Copyright 2006 Freescale Semiconductor.
4 * Srikanth Srinivasan (srikanth.srinivasan@freescale.com)
6 * See file CREDITS for list of people who contributed to this
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of
12 * the License, or (at your option) any later version.
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
26 * MPC8641HPCN board configuration file
28 * Make sure you change the MAC address and other network params first,
29 * search for CONFIG_ETHADDR, CONFIG_SERVERIP, etc in this file.
35 /* High Level Configuration Options */
36 #define CONFIG_MPC86xx 1 /* MPC86xx */
37 #define CONFIG_MPC8641 1 /* MPC8641 specific */
38 #define CONFIG_MPC8641HPCN 1 /* MPC8641HPCN board specific */
39 #define CONFIG_NUM_CPUS 2 /* Number of CPUs in the system */
40 #define CONFIG_LINUX_RESET_VEC 0x100 /* Reset vector used by Linux */
44 #define CFG_DIAG_ADDR 0xff800000
47 #define CFG_RESET_ADDRESS 0xfff00100
51 #define CONFIG_TSEC_ENET /* tsec ethernet support */
52 #define CONFIG_ENV_OVERWRITE
54 #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/
55 #undef CONFIG_DDR_DLL /* possible DLL fix needed */
56 #define CONFIG_DDR_2T_TIMING /* Sets the 2T timing bit */
57 #define CONFIG_DDR_ECC /* only for ECC DDR module */
58 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */
59 #define CONFIG_MEM_INIT_VALUE 0xDeadBeef
61 #define CONFIG_ALTIVEC 1
64 * L2CR setup -- make sure this is right for your board!
68 #define L2_ENABLE (L2CR_L2E)
70 #ifndef CONFIG_SYS_CLK_FREQ
71 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk(0)
74 #define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */
76 #undef CFG_DRAM_TEST /* memory test, takes time */
77 #define CFG_MEMTEST_START 0x00200000 /* memtest region */
78 #define CFG_MEMTEST_END 0x00400000
82 * Base addresses -- Note these are effective addresses where the
83 * actual resources get mapped (not physical addresses)
85 #define CFG_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */
86 #define CFG_CCSRBAR 0xf8000000 /* relocated CCSRBAR */
87 #define CFG_IMMR CFG_CCSRBAR /* PQII uses CFG_IMMR */
93 #define CFG_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/
94 #define CFG_SDRAM_BASE CFG_DDR_SDRAM_BASE
96 #define MPC86xx_DDR_SDRAM_CLK_CNTL
98 #if defined(CONFIG_SPD_EEPROM)
100 * Determine DDR configuration from I2C interface.
102 #define SPD_EEPROM_ADDRESS 0x51 /* DDR DIMM */
106 * Manually set up DDR1 parameters
109 #define CFG_SDRAM_SIZE 256 /* DDR is 256MB */
111 #define CFG_DDR_CS0_BNDS 0x0000000F
112 #define CFG_DDR_CS0_CONFIG 0x80010102 /* Enable, no interleaving */
113 #define CFG_DDR_EXT_REFRESH 0x00000000
114 #define CFG_DDR_TIMING_0 0x00260802
115 #define CFG_DDR_TIMING_1 0x39357322
116 #define CFG_DDR_TIMING_2 0x14904cc8
117 #define CFG_DDR_MODE_1 0x00480432
118 #define CFG_DDR_MODE_2 0x00000000
119 #define CFG_DDR_INTERVAL 0x06090100
120 #define CFG_DDR_DATA_INIT 0xdeadbeef
121 #define CFG_DDR_CLK_CTRL 0x03800000
122 #define CFG_DDR_OCD_CTRL 0x00000000
123 #define CFG_DDR_OCD_STATUS 0x00000000
124 #define CFG_DDR_CONTROL 0xe3008000 /* Type = DDR2 */
125 #define CFG_DDR_CONTROL2 0x04400000
127 /* Not used in fixed_sdram function */
129 #define CFG_DDR_MODE 0x00000022
130 #define CFG_DDR_CS1_BNDS 0x00000000
131 #define CFG_DDR_CS2_BNDS 0x00000FFF /* Not done */
132 #define CFG_DDR_CS3_BNDS 0x00000FFF /* Not done */
133 #define CFG_DDR_CS4_BNDS 0x00000FFF /* Not done */
134 #define CFG_DDR_CS5_BNDS 0x00000FFF /* Not done */
139 * In MPC8641HPCN, allocate 16MB flash spaces at fe000000 and ff000000.
140 * There is an 8MB flash. In effect, the addresses from fe000000 to fe7fffff
141 * map to fe800000 to ffffffff, and ff000000 to ff7fffff map to ffffffff.
142 * However, when u-boot comes up, the flash_init needs hard start addresses
143 * to build its info table. For user convenience, the flash addresses is
144 * fe800000 and ff800000. That way, u-boot knows where the flash is
145 * and the user can download u-boot code from promjet to fef00000, a
146 * more intuitive location than fe700000.
148 * Note that, on switching the boot location, fef00000 becomes fff00000.
150 #define CFG_FLASH_BASE 0xfe800000 /* start of FLASH 32M */
151 #define CFG_FLASH_BASE2 0xff800000
153 #define CFG_FLASH_BANKS_LIST {CFG_FLASH_BASE, CFG_FLASH_BASE2}
155 #define CFG_BR0_PRELIM 0xff001001 /* port size 16bit */
156 #define CFG_OR0_PRELIM 0xff006ff7 /* 16MB Boot Flash area*/
158 #define CFG_BR1_PRELIM 0xfe001001 /* port size 16bit */
159 #define CFG_OR1_PRELIM 0xff006ff7 /* 16MB Alternate Boot Flash area*/
161 #define CFG_BR2_PRELIM 0xf8201001 /* port size 16bit */
162 #define CFG_OR2_PRELIM 0xfff06ff7 /* 1MB Compact Flash area*/
164 #define CFG_BR3_PRELIM 0xf8100801 /* port size 8bit */
165 #define CFG_OR3_PRELIM 0xfff06ff7 /* 1MB PIXIS area*/
168 #define PIXIS_BASE 0xf8100000 /* PIXIS registers */
169 #define PIXIS_ID 0x0 /* Board ID at offset 0 */
170 #define PIXIS_VER 0x1 /* Board version at offset 1 */
171 #define PIXIS_PVER 0x2 /* PIXIS FPGA version at offset 2 */
172 #define PIXIS_RST 0x4 /* PIXIS Reset Control register */
173 #define PIXIS_AUX 0x6 /* PIXIS Auxiliary register; Scratch register */
174 #define PIXIS_SPD 0x7 /* Register for SYSCLK speed */
175 #define PIXIS_VCTL 0x10 /* VELA Control Register */
176 #define PIXIS_VCFGEN0 0x12 /* VELA Config Enable 0 */
177 #define PIXIS_VCFGEN1 0x13 /* VELA Config Enable 1 */
178 #define PIXIS_VBOOT 0x16 /* VELA VBOOT Register */
179 #define PIXIS_VSPEED0 0x17 /* VELA VSpeed 0 */
180 #define PIXIS_VSPEED1 0x18 /* VELA VSpeed 1 */
181 #define PIXIS_VCLKH 0x19 /* VELA VCLKH register */
182 #define PIXIS_VCLKL 0x1A /* VELA VCLKL register */
184 #define CFG_MAX_FLASH_BANKS 2 /* number of banks */
185 #define CFG_MAX_FLASH_SECT 128 /* sectors per device */
187 #undef CFG_FLASH_CHECKSUM
188 #define CFG_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
189 #define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
190 #define CFG_MONITOR_BASE TEXT_BASE /* start of monitor */
192 #define CFG_FLASH_CFI_DRIVER
193 #define CFG_FLASH_CFI
194 #define CFG_FLASH_EMPTY_INFO
196 #if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
202 #if !defined(CONFIG_SPD_EEPROM) && !defined(CFG_RAMBOOT)
203 #undef CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/
206 #undef CONFIG_CLOCKS_IN_MHZ
208 #define CONFIG_L1_INIT_RAM
209 #define CFG_INIT_RAM_LOCK 1
210 #ifndef CFG_INIT_RAM_LOCK
211 #define CFG_INIT_RAM_ADDR 0x0fd00000 /* Initial RAM address */
213 #define CFG_INIT_RAM_ADDR 0xf8400000 /* Initial RAM address */
215 #define CFG_INIT_RAM_END 0x4000 /* End of used area in RAM */
217 #define CFG_GBL_DATA_SIZE 128 /* num bytes initial data */
218 #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
219 #define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
221 #define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */
222 #define CFG_MALLOC_LEN (128 * 1024) /* Reserved for malloc */
225 #define CONFIG_CONS_INDEX 1
226 #undef CONFIG_SERIAL_SOFTWARE_FIFO
228 #define CFG_NS16550_SERIAL
229 #define CFG_NS16550_REG_SIZE 1
230 #define CFG_NS16550_CLK get_bus_freq(0)
232 #define CFG_BAUDRATE_TABLE \
233 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
235 #define CFG_NS16550_COM1 (CFG_CCSRBAR+0x4500)
236 #define CFG_NS16550_COM2 (CFG_CCSRBAR+0x4600)
238 /* Use the HUSH parser */
239 #define CFG_HUSH_PARSER
240 #ifdef CFG_HUSH_PARSER
241 #define CFG_PROMPT_HUSH_PS2 "> "
245 * Pass open firmware flat tree to kernel
247 #define CONFIG_OF_FLAT_TREE 1
248 #define CONFIG_OF_BOARD_SETUP 1
250 /* maximum size of the flat tree (8K) */
251 #define OF_FLAT_TREE_MAX_SIZE 8192
253 #define OF_CPU "PowerPC,8641@0"
254 #define OF_SOC "soc8641@f8000000"
255 #define OF_TBCLK (bd->bi_busfreq / 8)
256 #define OF_STDOUT_PATH "/soc8641@f8000000/serial@4500"
258 #define CFG_64BIT_VSPRINTF 1
259 #define CFG_64BIT_STRTOUL 1
264 #define CONFIG_HARD_I2C /* I2C with hardware support*/
265 #undef CONFIG_SOFT_I2C /* I2C bit-banged */
266 #define CFG_I2C_SPEED 400000 /* I2C speed and slave address */
267 #define CFG_I2C_SLAVE 0x7F
268 #define CFG_I2C_NOPROBES {0x69} /* Don't probe these addrs */
273 #define CFG_RIO_MEM_BASE 0xc0000000 /* base address */
274 #define CFG_RIO_MEM_PHYS CFG_RIO_MEM_BASE
275 #define CFG_RIO_MEM_SIZE 0x20000000 /* 128M */
279 * Addresses are mapped 1-1.
281 #define CFG_PCI1_MEM_BASE 0x80000000
282 #define CFG_PCI1_MEM_PHYS CFG_PCI1_MEM_BASE
283 #define CFG_PCI1_MEM_SIZE 0x20000000 /* 512M */
284 #define CFG_PCI1_IO_BASE 0xe2000000
285 #define CFG_PCI1_IO_PHYS CFG_PCI1_IO_BASE
286 #define CFG_PCI1_IO_SIZE 0x1000000 /* 16M */
289 #define _IO_BASE 0x00000000
291 #define CFG_PCI2_MEM_BASE 0xa0000000
292 #define CFG_PCI2_MEM_PHYS CFG_PCI2_MEM_BASE
293 #define CFG_PCI2_MEM_SIZE 0x10000000 /* 256M */
294 #define CFG_PCI2_IO_BASE 0xe3000000
295 #define CFG_PCI2_IO_PHYS CFG_PCI2_IO_BASE
296 #define CFG_PCI2_IO_SIZE 0x1000000 /* 16M */
299 #if defined(CONFIG_PCI)
301 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
303 #undef CFG_SCSI_SCAN_BUS_REVERSE
305 #define CONFIG_NET_MULTI
306 #define CONFIG_PCI_PNP /* do pci plug-and-play */
308 #define CONFIG_RTL8139
310 #undef CONFIG_EEPRO100
313 #if !defined(CONFIG_PCI_PNP)
314 #define PCI_ENET0_IOADDR 0xe0000000
315 #define PCI_ENET0_MEMADDR 0xe0000000
316 #define PCI_IDSEL_NUMBER 0x0c /* slot0->3(IDSEL)=12->15 */
319 #undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
321 #endif /* CONFIG_PCI */
324 #if defined(CONFIG_TSEC_ENET)
326 #ifndef CONFIG_NET_MULTI
327 #define CONFIG_NET_MULTI 1
330 #define CONFIG_MII 1 /* MII PHY management */
332 #define CONFIG_MPC86XX_TSEC1 1
333 #define CONFIG_MPC86XX_TSEC1_NAME "eTSEC1"
334 #define CONFIG_MPC86XX_TSEC2 1
335 #define CONFIG_MPC86XX_TSEC2_NAME "eTSEC2"
336 #define CONFIG_MPC86XX_TSEC3 1
337 #define CONFIG_MPC86XX_TSEC3_NAME "eTSEC3"
338 #define CONFIG_MPC86XX_TSEC4 1
339 #define CONFIG_MPC86XX_TSEC4_NAME "eTSEC4"
341 #define TSEC1_PHY_ADDR 0
342 #define TSEC2_PHY_ADDR 1
343 #define TSEC3_PHY_ADDR 2
344 #define TSEC4_PHY_ADDR 3
345 #define TSEC1_PHYIDX 0
346 #define TSEC2_PHYIDX 0
347 #define TSEC3_PHYIDX 0
348 #define TSEC4_PHYIDX 0
350 #define CONFIG_ETHPRIME "eTSEC1"
352 #endif /* CONFIG_TSEC_ENET */
356 * BAT0 2G Cacheable, non-guarded
359 #define CFG_DBAT0L ( BATL_PP_RW | BATL_CACHEINHIBIT \
360 | BATL_GUARDEDSTORAGE | BATL_MEMCOHERENCE )
361 #define CFG_DBAT0U ( BATU_BL_2G | BATU_VS | BATU_VP )
362 #define CFG_IBAT0L ( BATL_PP_RW | BATL_CACHEINHIBIT | BATL_MEMCOHERENCE)
363 #define CFG_IBAT0U CFG_DBAT0U
366 * BAT1 1G Cache-inhibited, guarded
367 * 0x8000_0000 512M PCI-Express 1 Memory
368 * 0xa000_0000 512M PCI-Express 2 Memory
369 * Changed it for operating from 0xd0000000
371 #define CFG_DBAT1L ( CFG_PCI1_MEM_BASE | BATL_PP_RW \
372 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
373 #define CFG_DBAT1U (CFG_PCI1_MEM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
374 #define CFG_IBAT1L (CFG_PCI1_MEM_BASE | BATL_PP_RW | BATL_CACHEINHIBIT)
375 #define CFG_IBAT1U CFG_DBAT1U
378 * BAT2 512M Cache-inhibited, guarded
379 * 0xc000_0000 512M RapidIO Memory
381 #define CFG_DBAT2L (CFG_RIO_MEM_BASE | BATL_PP_RW \
382 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
383 #define CFG_DBAT2U (CFG_RIO_MEM_BASE | BATU_BL_512M | BATU_VS | BATU_VP)
384 #define CFG_IBAT2L (CFG_RIO_MEM_BASE | BATL_PP_RW | BATL_CACHEINHIBIT)
385 #define CFG_IBAT2U CFG_DBAT2U
388 * BAT3 4M Cache-inhibited, guarded
389 * 0xf800_0000 4M CCSR
391 #define CFG_DBAT3L ( CFG_CCSRBAR | BATL_PP_RW \
392 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
393 #define CFG_DBAT3U (CFG_CCSRBAR | BATU_BL_4M | BATU_VS | BATU_VP)
394 #define CFG_IBAT3L (CFG_CCSRBAR | BATL_PP_RW | BATL_CACHEINHIBIT)
395 #define CFG_IBAT3U CFG_DBAT3U
398 * BAT4 32M Cache-inhibited, guarded
399 * 0xe200_0000 16M PCI-Express 1 I/O
400 * 0xe300_0000 16M PCI-Express 2 I/0
401 * Note that this is at 0xe0000000
403 #define CFG_DBAT4L ( CFG_PCI1_IO_BASE | BATL_PP_RW \
404 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
405 #define CFG_DBAT4U (CFG_PCI1_IO_BASE | BATU_BL_32M | BATU_VS | BATU_VP)
406 #define CFG_IBAT4L (CFG_PCI1_IO_BASE | BATL_PP_RW | BATL_CACHEINHIBIT)
407 #define CFG_IBAT4U CFG_DBAT4U
410 * BAT5 128K Cacheable, non-guarded
411 * 0xe401_0000 128K Init RAM for stack in the CPU DCache (no backing memory)
413 #define CFG_DBAT5L (CFG_INIT_RAM_ADDR | BATL_PP_RW | BATL_MEMCOHERENCE)
414 #define CFG_DBAT5U (CFG_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP)
415 #define CFG_IBAT5L CFG_DBAT5L
416 #define CFG_IBAT5U CFG_DBAT5U
419 * BAT6 32M Cache-inhibited, guarded
420 * 0xfe00_0000 32M FLASH
422 #define CFG_DBAT6L ( CFG_FLASH_BASE | BATL_PP_RW \
423 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
424 #define CFG_DBAT6U (CFG_FLASH_BASE | BATU_BL_32M | BATU_VS | BATU_VP)
425 #define CFG_IBAT6L (CFG_FLASH_BASE | BATL_PP_RW | BATL_MEMCOHERENCE)
426 #define CFG_IBAT6U CFG_DBAT6U
428 #define CFG_DBAT7L 0x00000000
429 #define CFG_DBAT7U 0x00000000
430 #define CFG_IBAT7L 0x00000000
431 #define CFG_IBAT7U 0x00000000
440 #define CFG_ENV_IS_IN_FLASH 1
441 #define CFG_ENV_ADDR (CFG_MONITOR_BASE + 0x40000)
442 #define CFG_ENV_SECT_SIZE 0x40000 /* 256K(one sector) for env */
443 #define CFG_ENV_SIZE 0x2000
445 #define CFG_NO_FLASH 1 /* Flash is not usable now */
446 #define CFG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */
447 #define CFG_ENV_ADDR (CFG_MONITOR_BASE - 0x1000)
448 #define CFG_ENV_SIZE 0x2000
451 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
452 #define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
454 #if defined(CFG_RAMBOOT)
455 #if defined(CONFIG_PCI)
456 #define CONFIG_COMMANDS ((CONFIG_CMD_DFL \
466 #define CONFIG_COMMANDS ((CONFIG_CMD_DFL \
476 #if defined(CONFIG_PCI)
477 #define CONFIG_COMMANDS (CONFIG_CMD_DFL \
482 #define CONFIG_COMMANDS (CONFIG_CMD_DFL \
488 #include <cmd_confdefs.h>
490 #undef CONFIG_WATCHDOG /* watchdog disabled */
493 * Miscellaneous configurable options
495 #define CFG_LONGHELP /* undef to save memory */
496 #define CFG_LOAD_ADDR 0x2000000 /* default load address */
497 #define CFG_PROMPT "=> " /* Monitor Command Prompt */
499 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
500 #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
502 #define CFG_CBSIZE 256 /* Console I/O Buffer Size */
505 #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
506 #define CFG_MAXARGS 16 /* max number of command args */
507 #define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
508 #define CFG_HZ 1000 /* decrementer freq: 1ms ticks */
511 * For booting Linux, the board info and command line data
512 * have to be in the first 8 MB of memory, since this is
513 * the maximum mapped by the Linux kernel during initialization.
515 #define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/
517 /* Cache Configuration */
518 #define CFG_DCACHE_SIZE 32768
519 #define CFG_CACHELINE_SIZE 32
520 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
521 #define CFG_CACHELINE_SHIFT 5 /*log base 2 of the above value*/
525 * Internal Definitions
529 #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
530 #define BOOTFLAG_WARM 0x02 /* Software reboot */
532 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
533 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
534 #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
539 * Environment Configuration
542 /* The mac addresses for all ethernet interface */
543 #if defined(CONFIG_TSEC_ENET)
544 #define CONFIG_ETHADDR 00:E0:0C:00:00:01
545 #define CONFIG_ETH1ADDR 00:E0:0C:00:01:FD
546 #define CONFIG_ETH2ADDR 00:E0:0C:00:02:FD
547 #define CONFIG_ETH3ADDR 00:E0:0C:00:03:FD
550 #define CONFIG_HAS_ETH1 1
551 #define CONFIG_HAS_ETH2 1
552 #define CONFIG_HAS_ETH3 1
554 #define CONFIG_IPADDR 192.168.1.100
556 #define CONFIG_HOSTNAME unknown
557 #define CONFIG_ROOTPATH /opt/nfsroot
558 #define CONFIG_BOOTFILE uImage
560 #define CONFIG_SERVERIP 192.168.1.1
561 #define CONFIG_GATEWAYIP 192.168.1.1
562 #define CONFIG_NETMASK 255.255.255.0
564 /* default location for tftp and bootm */
565 #define CONFIG_LOADADDR 1000000
567 #define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */
568 #undef CONFIG_BOOTARGS /* the boot command will set bootargs */
570 #define CONFIG_BAUDRATE 115200
572 #define CONFIG_EXTRA_ENV_SETTINGS \
574 "consoledev=ttyS0\0" \
575 "ramdiskaddr=400000\0" \
576 "ramdiskfile=your.ramdisk.u-boot\0" \
577 "pex0=echo ---------------------------; echo --------- PCI EXPRESS -----\0"\
578 "pexstat=mw f8008000 84000004; echo -expect:- 16000000; md f8008004 1\0" \
579 "pex1=pci write 1.0.0 4 146; pci write 1.0.0 10 80000000\0" \
580 "pexd=echo -expect:- xxx01002 00100146; pci display 1.0.0 0 2\0" \
581 "pex=run pexstat; run pex1; run pexd\0" \
582 "en-wd=mw.b f8100010 0x08; echo -expect:- 08; md.b f8100010 1\0" \
583 "dis-wd=mw.b f8100010 0x00; echo -expect:- 00; md.b f8100010 1\0" \
587 #define CONFIG_NFSBOOTCOMMAND \
588 "setenv bootargs root=/dev/nfs rw " \
589 "nfsroot=$serverip:$rootpath " \
590 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
591 "console=$consoledev,$baudrate $othbootargs;" \
592 "tftp $loadaddr $bootfile;" \
595 #define CONFIG_RAMBOOTCOMMAND \
596 "setenv bootargs root=/dev/ram rw " \
597 "console=$consoledev,$baudrate $othbootargs;" \
598 "tftp $ramdiskaddr $ramdiskfile;" \
599 "tftp $loadaddr $bootfile;" \
600 "bootm $loadaddr $ramdiskaddr"
602 #define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND
604 #endif /* __CONFIG_H */