2 * (C) Copyright 2006, 2007 Detlev Zundel, dzu@denx.de
4 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
6 * See file CREDITS for list of people who contributed to this
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of
12 * the License, or (at your option) any later version.
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
26 * board/config.h - configuration options, board specific
33 * High Level Configuration Options
36 #define CONFIG_MPC852T 1
37 #define CONFIG_NC650 1
39 #define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */
40 #undef CONFIG_8xx_CONS_SMC2
41 #undef CONFIG_8xx_CONS_NONE
42 #define CONFIG_BAUDRATE 115200
43 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
46 * 10 MHz - PLL input clock
48 #define CONFIG_8xx_OSCLK 10000000
51 * 50 MHz - default CPU clock
53 #define CONFIG_8xx_CPUCLK_DEFAULT 50000000
56 * 15 MHz - CPU minimum clock
58 #define CFG_8xx_CPUCLK_MIN 15000000
61 * 133 MHz - CPU maximum clock
63 #define CFG_8xx_CPUCLK_MAX 133000000
65 #define CFG_MEASURE_CPUCLK
66 #define CFG_8XX_XIN CONFIG_8xx_OSCLK
68 #define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
69 #define CONFIG_AUTOBOOT_KEYED
70 #define CONFIG_AUTOBOOT_PROMPT "\nEnter password - autoboot in %d seconds...\n"
71 #define CONFIG_AUTOBOOT_DELAY_STR "ids"
72 #define CONFIG_BOOT_RETRY_TIME 900
73 #define CONFIG_BOOT_RETRY_MIN 30
75 #define CONFIG_PREBOOT "echo;echo Type \"run flash_nfs\" to mount root filesystem over NFS;echo"
77 #undef CONFIG_BOOTARGS
78 #define CONFIG_BOOTCOMMAND \
80 "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \
81 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off;" \
84 #define CONFIG_WATCHDOG /* watchdog enabled */
86 #undef CONFIG_STATUS_LED /* Status LED disabled */
88 #define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE)
90 #define CONFIG_FEC_ENET 1 /* use FEC ethernet */
93 #define CFG_DISCOVER_PHY 1
96 /* enable I2C and select the hardware/software driver */
97 #undef CONFIG_HARD_I2C /* I2C with hardware support */
98 #define CONFIG_SOFT_I2C 1 /* I2C bit-banged */
99 #define CFG_I2C_SPEED 100000 /* 100 kHz */
100 #define CFG_I2C_SLAVE 0x7f
103 * Software (bit-bang) I2C driver configuration
105 #if defined(CONFIG_IDS852_REV1)
107 #define SCL 0x1000 /* PA 3 */
108 #define SDA 0x2000 /* PA 2 */
110 #define __I2C_DIR immr->im_ioport.iop_padir
111 #define __I2C_DAT immr->im_ioport.iop_padat
112 #define __I2C_PAR immr->im_ioport.iop_papar
114 #elif defined(CONFIG_IDS852_REV2)
116 #define SCL 0x0002 /* PB 30 */
117 #define SDA 0x0001 /* PB 31 */
119 #define __I2C_PAR immr->im_cpm.cp_pbpar
120 #define __I2C_DIR immr->im_cpm.cp_pbdir
121 #define __I2C_DAT immr->im_cpm.cp_pbdat
125 #define I2C_INIT { __I2C_PAR &= ~(SDA|SCL); \
126 __I2C_DIR |= (SDA|SCL); }
127 #define I2C_READ ((__I2C_DAT & SDA) ? 1 : 0)
128 #define I2C_SDA(x) { if (x) __I2C_DAT |= SDA; else __I2C_DAT &= ~SDA; }
129 #define I2C_SCL(x) { if (x) __I2C_DAT |= SCL; else __I2C_DAT &= ~SCL; }
130 #define I2C_DELAY { udelay(5); }
131 #define I2C_ACTIVE { __I2C_DIR |= SDA; }
132 #define I2C_TRISTATE { __I2C_DIR &= ~SDA; }
134 #define CONFIG_RTC_PCF8563
135 #define CFG_I2C_RTC_ADDR 0x51
139 * Command line configuration.
141 #include <config_cmd_default.h>
143 #define CONFIG_CMD_ASKENV
144 #define CONFIG_CMD_DATE
145 #define CONFIG_CMD_DHCP
146 #define CONFIG_CMD_I2C
147 #define CONFIG_CMD_NAND
148 #define CONFIG_CMD_JFFS2
149 #define CONFIG_CMD_NFS
150 #define CONFIG_CMD_SNTP
154 * Miscellaneous configurable options
156 #define CFG_LONGHELP /* undef to save memory */
157 #define CFG_PROMPT "=> " /* Monitor Command Prompt */
158 #if defined(CONFIG_CMD_KGDB)
159 #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
161 #define CFG_CBSIZE 256 /* Console I/O Buffer Size */
163 #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
164 #define CFG_MAXARGS 16 /* max number of command args */
165 #define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
167 #define CFG_MEMTEST_START 0x0100000 /* memtest works on */
168 #define CFG_MEMTEST_END 0x0400000 /* 1 ... 4 MB in DRAM */
170 #define CFG_LOAD_ADDR 0x00100000
172 #define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
174 #define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
177 * Low Level Configuration Settings
178 * (address mappings, register initial values, etc.)
179 * You should know what you are doing if you make changes here.
181 /*-----------------------------------------------------------------------
182 * Internal Memory Mapped Register
184 #define CFG_IMMR 0xF0000000
185 #define CFG_IMMR_SIZE ((uint)(64 * 1024))
187 /*-----------------------------------------------------------------------
188 * Definitions for initial stack pointer and data area (in DPRAM)
190 #define CFG_INIT_RAM_ADDR CFG_IMMR
191 #define CFG_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */
192 #define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */
193 #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
194 #define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
196 /*-----------------------------------------------------------------------
197 * Start addresses for the final memory configuration
198 * (Set up by the startup code)
199 * Please note that CFG_SDRAM_BASE _must_ start at 0
201 #define CFG_SDRAM_BASE 0x00000000
202 #define CFG_FLASH_BASE 0x40000000
204 #define CFG_RESET_ADDRESS 0xFFF00100
206 #define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
207 #define CFG_MONITOR_BASE TEXT_BASE
208 #define CFG_MALLOC_LEN (256 << 10) /* Reserve 256 kB for malloc() */
211 * For booting Linux, the board info and command line data
212 * have to be in the first 8 MB of memory, since this is
213 * the maximum mapped by the Linux kernel during initialization.
215 #define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
216 /*-----------------------------------------------------------------------
219 #define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
220 #define CFG_MAX_FLASH_SECT 64 /* max number of sectors on one chip */
222 #define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
223 #define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
226 #define CFG_ENV_IS_IN_FLASH 1
227 #define CFG_ENV_OFFSET 0x00740000
229 #define CFG_ENV_SECT_SIZE 0x20000 /* Total Size of Environment sector */
230 #define CFG_ENV_SIZE 0x4000 /* Used Size of Environment Sector */
232 /*-----------------------------------------------------------------------
233 * Cache Configuration
235 #define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
236 #if defined(CONFIG_CMD_KGDB)
237 #define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */
243 #define CFG_MAX_NAND_DEVICE 1
244 #define NAND_MAX_CHIPS 1
246 /*-----------------------------------------------------------------------
247 * SYPCR - System Protection Control 11-9
248 * SYPCR can only be written once after reset!
249 *-----------------------------------------------------------------------
250 * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
252 #if defined(CONFIG_WATCHDOG)
253 #define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
254 SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP)
256 #define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
259 /*-----------------------------------------------------------------------
260 * SIUMCR - SIU Module Configuration 11-6
261 *-----------------------------------------------------------------------
263 #define CFG_SIUMCR (SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
265 /*-----------------------------------------------------------------------
266 * TBSCR - Time Base Status and Control 11-26
267 *-----------------------------------------------------------------------
268 * Clear Reference Interrupt Status, Timebase freezing enabled
270 #define CFG_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBE)
272 /*-----------------------------------------------------------------------
273 * PISCR - Periodic Interrupt Status and Control 11-31
274 *-----------------------------------------------------------------------
275 * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
277 #define CFG_PISCR (PISCR_PS | PISCR_PITF)
279 /*-----------------------------------------------------------------------
280 * SCCR - System Clock and reset Control Register 15-27
281 *-----------------------------------------------------------------------
282 * Set clock output, timebase and RTC source and divider,
283 * power management and some other internal clocks
285 #define SCCR_MASK SCCR_EBDF11
286 #define CFG_SCCR (SCCR_COM00 | SCCR_DFSYNC00 | \
287 SCCR_DFBRG00 | SCCR_DFNL000 | SCCR_DFNH000 | \
288 SCCR_DFLCD000 | SCCR_DFALCD00)
290 /*-----------------------------------------------------------------------
292 *-----------------------------------------------------------------------
298 * Init Memory Controller:
300 * BR0 and OR0 (FLASH)
303 #define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */
305 #define CFG_REMAP_OR_AM 0x80000000 /* OR addr mask */
306 #define CFG_PRELIM_OR_AM 0xE0000000 /* OR addr mask */
308 /* FLASH timing: Default value of OR0 after reset */
309 #define CFG_OR_TIMING_FLASH (OR_CSNT_SAM | OR_ACS_MSK | OR_BI | \
310 OR_SCY_15_CLK | OR_TRLX)
312 #define CFG_OR0_REMAP (CFG_REMAP_OR_AM | CFG_OR_TIMING_FLASH)
313 #define CFG_OR0_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH)
314 #define CFG_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_PS_8 | BR_V)
317 * BR2 and OR2 (NAND Flash) - addressed through UPMB on rev 1
318 * rev2 only uses the chipselect
320 #define CFG_NAND_BASE 0x50000000
321 #define CFG_NAND_SIZE 0x04000000
323 #define CFG_OR_TIMING_NAND (OR_CSNT_SAM | OR_ACS_DIV1 | OR_BI | \
324 OR_SCY_15_CLK | OR_EHTR | OR_TRLX)
326 #define CFG_BR2_PRELIM ((CFG_NAND_BASE & BR_BA_MSK) | BR_PS_8 | BR_MS_UPMB | BR_V )
327 #define CFG_OR2_PRELIM (((-CFG_NAND_SIZE) & OR_AM_MSK) | OR_BI )
330 * BR3 and OR3 (SDRAM)
332 #define SDRAM_BASE3_PRELIM 0x00000000 /* SDRAM bank */
333 #define SDRAM_MAX_SIZE 0x04000000 /* max 64 MB per bank */
336 * SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care)
338 #define CFG_OR_TIMING_SDRAM 0x00000A00
340 #define CFG_OR3_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_SDRAM)
341 #define CFG_BR3_PRELIM ((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V)
346 #define CFG_CPLD_BASE 0x80000000 /* CPLD */
347 #define CFG_CPLD_SIZE 0x10000 /* only 16 used */
349 #define CFG_OR_TIMING_CPLD (OR_CSNT_SAM | OR_ACS_DIV1 | OR_BI | \
352 #define CFG_BR4_PRELIM ((CFG_CPLD_BASE & BR_BA_MSK) | BR_PS_8 | BR_V )
353 #define CFG_OR4_PRELIM (((-CFG_CPLD_SIZE) & OR_AM_MSK) | CFG_OR_TIMING_CPLD)
358 #define CFG_SRAM_BASE 0x60000000
359 #define CFG_SRAM_SIZE 0x00080000
361 #define CFG_OR_TIMING_SRAM (OR_CSNT_SAM | OR_ACS_DIV1 | OR_BI | \
362 OR_SCY_15_CLK | OR_EHTR | OR_TRLX)
364 #define CFG_BR5_PRELIM ((CFG_SRAM_BASE & BR_BA_MSK) | BR_PS_8 | BR_V )
365 #define CFG_OR5_PRELIM (((-CFG_SRAM_SIZE) & OR_AM_MSK) | CFG_OR_TIMING_SRAM)
367 #if defined(CONFIG_CP850)
369 * BR6 and OR6 (DPRAM) - only on CP850
371 #define CFG_OR6_PRELIM 0xffff8170
372 #define CFG_BR6_PRELIM 0xa0000401
373 #define DPRAM_BASE_ADDR 0xa0000000
375 #define CONFIG_MISC_INIT_R 1
379 * 4096 Rows from SDRAM example configuration
380 * 1000 factor s -> ms
381 * 64 PTP (pre-divider from MPTPR) from SDRAM example configuration
382 * 4 Number of refresh cycles per period
383 * 64 Refresh cycle in ms per number of rows
385 #define CFG_PTA_PER_CLK ((4096 * 64 * 1000) / (4 * 64))
388 * Memory Periodic Timer Prescaler
391 /* periodic timer for refresh */
392 #define CFG_MAMR_PTA 39
394 /* refresh rate 15.6 us (= 64 ms / 4K = 62.4 / quad bursts) for <= 128 MBit */
395 #define CFG_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */
396 #define CFG_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */
398 /* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */
399 #define CFG_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */
400 #define CFG_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */
403 * MAMR settings for SDRAM
406 #define CFG_MAMR_8COL ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
407 MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \
408 MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
409 #define CFG_MAMR_9COL ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
410 MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \
411 MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
414 * MBMR settings for NAND flash
417 #define CFG_MBMR_NAND ( MBMR_WLFB_5X )
420 * Internal Definitions
424 #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
425 #define BOOTFLAG_WARM 0x02 /* Software reboot */
427 #define CONFIG_JFFS2_NAND 1 /* jffs2 on nand support */
428 #define NAND_CACHE_PAGES 16 /* size of nand cache in 512 bytes pages */
434 /* No command line, one static partition */
435 #undef CONFIG_JFFS2_CMDLINE
436 #define CONFIG_JFFS2_DEV "nand0"
437 #define CONFIG_JFFS2_PART_SIZE 0x00400000
438 #define CONFIG_JFFS2_PART_OFFSET 0x00000000
440 /* mtdparts command line support */
441 #define CONFIG_JFFS2_CMDLINE
442 #define MTDIDS_DEFAULT "nor0=nc650-0,nand0=nc650-nand"
444 #define MTDPARTS_DEFAULT "mtdparts=nc650-0:1m(kernel1),1m(kernel2)," \
445 "4m(cramfs1),1m(cramfs2)," \
446 "256k(u-boot),128k(env);" \
447 "nc650-nand:4m(jffs1),28m(jffs2)"
449 #endif /* __CONFIG_H */