2 * (C) Copyright 2000-2004
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
25 * Pantelis Antoniou, Intracom S.A., panto@intracom.gr
26 * U-Boot port on NetTA4 board
32 #if !defined(CONFIG_NETPHONE_VERSION) || CONFIG_NETPHONE_VERSION > 2
33 #error Unsupported CONFIG_NETPHONE version
37 * High Level Configuration Options
41 #define CONFIG_MPC870 1 /* This is a MPC885 CPU */
42 #define CONFIG_NETPHONE 1 /* ...on a NetPhone board */
44 #define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */
45 #undef CONFIG_8xx_CONS_SMC2
46 #undef CONFIG_8xx_CONS_NONE
48 #define CONFIG_BAUDRATE 115200 /* console baudrate = 115kbps */
50 /* #define CONFIG_XIN 10000000 */
51 #define CONFIG_XIN 50000000
52 /* #define MPC8XX_HZ 120000000 */
53 #define MPC8XX_HZ 66666666
55 #define CONFIG_8xx_GCLK_FREQ MPC8XX_HZ
58 #define CONFIG_BOOTDELAY -1 /* autoboot disabled */
60 #define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
63 #undef CONFIG_CLOCKS_IN_MHZ /* clocks NOT passsed to Linux in MHz */
65 #define CONFIG_PREBOOT "echo;"
67 #undef CONFIG_BOOTARGS
68 #define CONFIG_BOOTCOMMAND \
70 "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \
71 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off;" \
74 #define CONFIG_AUTOSCRIPT
75 #define CONFIG_LOADS_ECHO 0 /* echo off for serial download */
76 #undef CFG_LOADS_BAUD_CHANGE /* don't allow baudrate change */
78 #undef CONFIG_WATCHDOG /* watchdog disabled */
80 #undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */
82 #define CONFIG_STATUS_LED 1 /* Status LED enabled */
83 #define CONFIG_BOARD_SPECIFIC_LED /* version has board specific leds */
85 #define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE | CONFIG_BOOTP_NISDOMAIN)
87 #undef CONFIG_MAC_PARTITION
88 #undef CONFIG_DOS_PARTITION
90 #define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */
92 #define CONFIG_NET_MULTI 1 /* the only way to get the FEC in */
93 #define FEC_ENET 1 /* eth.c needs it that way... */
94 #undef CFG_DISCOVER_PHY
96 #define CONFIG_RMII 1 /* use RMII interface */
98 #define CONFIG_ETHER_ON_FEC1 1
99 #define CONFIG_FEC1_PHY 8 /* phy address of FEC */
100 #define CONFIG_FEC1_PHY_NORXERR 1
102 #define CONFIG_ETHER_ON_FEC2 1
103 #define CONFIG_FEC2_PHY 4
104 #define CONFIG_FEC2_PHY_NORXERR 1
106 #define CONFIG_ENV_OVERWRITE 1 /* allow modification of vendor params */
110 * Command line configuration.
112 #include <config_cmd_default.h>
114 #define CONFIG_CMD_NAND
115 #define CONFIG_CMD_DHCP
116 #define CONFIG_CMD_PING
117 #define CONFIG_CMD_MII
118 #define CONFIG_CMD_CDP
121 #define CONFIG_BOARD_EARLY_INIT_F 1
122 #define CONFIG_MISC_INIT_R
125 * Miscellaneous configurable options
127 #define CFG_LONGHELP /* undef to save memory */
128 #define CFG_PROMPT "=> " /* Monitor Command Prompt */
130 #define CFG_HUSH_PARSER 1
131 #define CFG_PROMPT_HUSH_PS2 "> "
133 #if defined(CONFIG_CMD_KGDB)
134 #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
136 #define CFG_CBSIZE 256 /* Console I/O Buffer Size */
138 #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
139 #define CFG_MAXARGS 16 /* max number of command args */
140 #define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
142 #define CFG_MEMTEST_START 0x0300000 /* memtest works on */
143 #define CFG_MEMTEST_END 0x0700000 /* 3 ... 7 MB in DRAM */
145 #define CFG_LOAD_ADDR 0x100000 /* default load address */
147 #define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
149 #define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
152 * Low Level Configuration Settings
153 * (address mappings, register initial values, etc.)
154 * You should know what you are doing if you make changes here.
156 /*-----------------------------------------------------------------------
157 * Internal Memory Mapped Register
159 #define CFG_IMMR 0xFF000000
161 /*-----------------------------------------------------------------------
162 * Definitions for initial stack pointer and data area (in DPRAM)
164 #define CFG_INIT_RAM_ADDR CFG_IMMR
165 #define CFG_INIT_RAM_END 0x3000 /* End of used area in DPRAM */
166 #define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */
167 #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
168 #define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
170 /*-----------------------------------------------------------------------
171 * Start addresses for the final memory configuration
172 * (Set up by the startup code)
173 * Please note that CFG_SDRAM_BASE _must_ start at 0
175 #define CFG_SDRAM_BASE 0x00000000
176 #define CFG_FLASH_BASE 0x40000000
178 #define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
180 #define CFG_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */
182 #define CFG_MONITOR_BASE CFG_FLASH_BASE
183 #define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
184 #if CONFIG_NETPHONE_VERSION == 2
185 #define CFG_FLASH_BASE4 0x40080000
188 #define CFG_RESET_ADDRESS 0x80000000
191 * For booting Linux, the board info and command line data
192 * have to be in the first 8 MB of memory, since this is
193 * the maximum mapped by the Linux kernel during initialization.
195 #define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
197 /*-----------------------------------------------------------------------
200 #if CONFIG_NETPHONE_VERSION == 1
201 #define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
202 #elif CONFIG_NETPHONE_VERSION == 2
203 #define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */
205 #define CFG_MAX_FLASH_SECT 8 /* max number of sectors on one chip */
207 #define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
208 #define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
210 #define CFG_ENV_IS_IN_FLASH 1
211 #define CFG_ENV_SECT_SIZE 0x10000
213 #define CFG_ENV_ADDR (CFG_FLASH_BASE + 0x60000)
214 #define CFG_ENV_OFFSET 0
215 #define CFG_ENV_SIZE 0x4000
217 #define CFG_ENV_ADDR_REDUND (CFG_FLASH_BASE + 0x70000)
218 #define CFG_ENV_OFFSET_REDUND 0
219 #define CFG_ENV_SIZE_REDUND CFG_ENV_SIZE
221 /*-----------------------------------------------------------------------
222 * Cache Configuration
224 #define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
225 #if defined(CONFIG_CMD_KGDB)
226 #define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */
229 /*-----------------------------------------------------------------------
230 * SYPCR - System Protection Control 11-9
231 * SYPCR can only be written once after reset!
232 *-----------------------------------------------------------------------
233 * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
235 #if defined(CONFIG_WATCHDOG)
236 #define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
237 SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP)
239 #define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
242 /*-----------------------------------------------------------------------
243 * SIUMCR - SIU Module Configuration 11-6
244 *-----------------------------------------------------------------------
245 * PCMCIA config., multi-function pin tri-state
247 #ifndef CONFIG_CAN_DRIVER
248 #define CFG_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01 | SIUMCR_FRC)
249 #else /* we must activate GPL5 in the SIUMCR for CAN */
250 #define CFG_SIUMCR (SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01 | SIUMCR_FRC)
251 #endif /* CONFIG_CAN_DRIVER */
253 /*-----------------------------------------------------------------------
254 * TBSCR - Time Base Status and Control 11-26
255 *-----------------------------------------------------------------------
256 * Clear Reference Interrupt Status, Timebase freezing enabled
258 #define CFG_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
260 /*-----------------------------------------------------------------------
261 * RTCSC - Real-Time Clock Status and Control Register 11-27
262 *-----------------------------------------------------------------------
264 #define CFG_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)
266 /*-----------------------------------------------------------------------
267 * PISCR - Periodic Interrupt Status and Control 11-31
268 *-----------------------------------------------------------------------
269 * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
271 #define CFG_PISCR (PISCR_PS | PISCR_PITF)
273 /*-----------------------------------------------------------------------
274 * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30
275 *-----------------------------------------------------------------------
276 * Reset PLL lock status sticky bit, timer expired status bit and timer
277 * interrupt status bit
281 #if CONFIG_XIN == 10000000
283 #if MPC8XX_HZ == 120000000
284 #define CFG_PLPRCR ((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \
285 (0 << PLPRCR_S_SHIFT) | (12 << PLPRCR_MFI_SHIFT) | (0 << PLPRCR_PDF_SHIFT) | \
287 #elif MPC8XX_HZ == 100000000
288 #define CFG_PLPRCR ((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \
289 (0 << PLPRCR_S_SHIFT) | (10 << PLPRCR_MFI_SHIFT) | (0 << PLPRCR_PDF_SHIFT) | \
291 #elif MPC8XX_HZ == 50000000
292 #define CFG_PLPRCR ((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \
293 (1 << PLPRCR_S_SHIFT) | (8 << PLPRCR_MFI_SHIFT) | (3 << PLPRCR_PDF_SHIFT) | \
295 #elif MPC8XX_HZ == 25000000
296 #define CFG_PLPRCR ((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \
297 (2 << PLPRCR_S_SHIFT) | (8 << PLPRCR_MFI_SHIFT) | (3 << PLPRCR_PDF_SHIFT) | \
299 #elif MPC8XX_HZ == 40000000
300 #define CFG_PLPRCR ((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \
301 (1 << PLPRCR_S_SHIFT) | (8 << PLPRCR_MFI_SHIFT) | (4 << PLPRCR_PDF_SHIFT) | \
303 #elif MPC8XX_HZ == 75000000
304 #define CFG_PLPRCR ((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \
305 (1 << PLPRCR_S_SHIFT) | (15 << PLPRCR_MFI_SHIFT) | (0 << PLPRCR_PDF_SHIFT) | \
308 #error unsupported CPU freq for XIN = 10MHz
311 #elif CONFIG_XIN == 50000000
313 #if MPC8XX_HZ == 120000000
314 #define CFG_PLPRCR ((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \
315 (0 << PLPRCR_S_SHIFT) | (12 << PLPRCR_MFI_SHIFT) | (4 << PLPRCR_PDF_SHIFT) | \
317 #elif MPC8XX_HZ == 100000000
318 #define CFG_PLPRCR ((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \
319 (0 << PLPRCR_S_SHIFT) | (6 << PLPRCR_MFI_SHIFT) | (2 << PLPRCR_PDF_SHIFT) | \
321 #elif MPC8XX_HZ == 66666666
322 #define CFG_PLPRCR ((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \
323 (1 << PLPRCR_S_SHIFT) | (8 << PLPRCR_MFI_SHIFT) | (2 << PLPRCR_PDF_SHIFT) | \
326 #error unsupported CPU freq for XIN = 50MHz
331 #error unsupported XIN freq
336 *-----------------------------------------------------------------------
337 * SCCR - System Clock and reset Control Register 15-27
338 *-----------------------------------------------------------------------
339 * Set clock output, timebase and RTC source and divider,
340 * power management and some other internal clocks
342 * Note: When TBS == 0 the timebase is independent of current cpu clock.
345 #define SCCR_MASK SCCR_EBDF11
346 #if MPC8XX_HZ > 66666666
347 #define CFG_SCCR (/* SCCR_TBS | */ SCCR_CRQEN | \
348 SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \
349 SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \
350 SCCR_DFALCD00 | SCCR_EBDF01)
352 #define CFG_SCCR (/* SCCR_TBS | */ SCCR_CRQEN | \
353 SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \
354 SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \
358 /*-----------------------------------------------------------------------
360 *-----------------------------------------------------------------------
363 /*#define CFG_DER 0x2002000F*/
367 * Init Memory Controller:
369 * BR0/1 and OR0/1 (FLASH)
372 #define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */
374 /* used to re-map FLASH both when starting from SRAM or FLASH:
375 * restrict access enough to keep SRAM working (if any)
376 * but not too much to meddle with FLASH accesses
378 #define CFG_REMAP_OR_AM 0x80000000 /* OR addr mask */
379 #define CFG_PRELIM_OR_AM 0xE0000000 /* OR addr mask */
381 /* FLASH timing: ACS = 11, TRLX = 0, CSNT = 1, SCY = 5, EHTR = 1 */
382 #define CFG_OR_TIMING_FLASH (OR_CSNT_SAM | OR_BI | OR_SCY_5_CLK | OR_TRLX)
384 #define CFG_OR0_REMAP (CFG_REMAP_OR_AM | CFG_OR_TIMING_FLASH)
385 #define CFG_OR0_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH)
386 #define CFG_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_PS_8 | BR_V )
388 #if CONFIG_NETPHONE_VERSION == 2
390 #define FLASH_BASE4_PRELIM 0x40080000 /* FLASH bank #1 */
392 #define CFG_OR4_REMAP (CFG_REMAP_OR_AM | CFG_OR_TIMING_FLASH)
393 #define CFG_OR4_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH)
394 #define CFG_BR4_PRELIM ((FLASH_BASE4_PRELIM & BR_BA_MSK) | BR_PS_8 | BR_V )
399 * BR3 and OR3 (SDRAM)
402 #define SDRAM_BASE3_PRELIM 0x00000000 /* SDRAM bank #0 */
403 #define SDRAM_MAX_SIZE (256 << 20) /* max 256MB per bank */
405 /* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */
406 #define CFG_OR_TIMING_SDRAM (OR_CSNT_SAM | OR_G5LS)
408 #define CFG_OR3_PRELIM ((0xFFFFFFFFLU & ~(SDRAM_MAX_SIZE - 1)) | CFG_OR_TIMING_SDRAM)
409 #define CFG_BR3_PRELIM ((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMB | BR_PS_32 | BR_V)
412 * Memory Periodic Timer Prescaler
416 * Memory Periodic Timer Prescaler
418 * The Divider for PTA (refresh timer) configuration is based on an
419 * example SDRAM configuration (64 MBit, one bank). The adjustment to
420 * the number of chip selects (NCS) and the actually needed refresh
421 * rate is done by setting MPTPR.
423 * PTA is calculated from
424 * PTA = (gclk * Trefresh) / ((2 ^ (2 * DFBRG)) * PTP * NCS)
426 * gclk CPU clock (not bus clock!)
427 * Trefresh Refresh cycle * 4 (four word bursts used)
429 * 4096 Rows from SDRAM example configuration
430 * 1000 factor s -> ms
431 * 32 PTP (pre-divider from MPTPR) from SDRAM example configuration
432 * 4 Number of refresh cycles per period
433 * 64 Refresh cycle in ms per number of rows
434 * --------------------------------------------
435 * Divider = 4096 * 32 * 1000 / (4 * 64) = 512000
437 * 50 MHz => 50.000.000 / Divider = 98
438 * 66 Mhz => 66.000.000 / Divider = 129
439 * 80 Mhz => 80.000.000 / Divider = 156
442 #define CFG_MAMR_PTA 234
445 * For 16 MBit, refresh rates could be 31.3 us
446 * (= 64 ms / 2K = 125 / quad bursts).
447 * For a simpler initialization, 15.6 us is used instead.
449 * #define CFG_MPTPR_2BK_2K MPTPR_PTP_DIV32 for 2 banks
450 * #define CFG_MPTPR_1BK_2K MPTPR_PTP_DIV64 for 1 bank
452 #define CFG_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */
453 #define CFG_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */
455 /* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */
456 #define CFG_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */
457 #define CFG_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */
460 * MAMR settings for SDRAM
464 #define CFG_MAMR_8COL ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
465 MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \
466 MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
469 #define CFG_MAMR_9COL ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
470 MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \
471 MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
474 * Internal Definitions
478 #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
479 #define BOOTFLAG_WARM 0x02 /* Software reboot */
481 #define CONFIG_ARTOS /* include ARTOS support */
483 #define CONFIG_LAST_STAGE_INIT /* needed to reset the damn phys */
485 /****************************************************************/
487 #define DSP_SIZE 0x00010000 /* 64K */
488 #define NAND_SIZE 0x00010000 /* 64K */
490 #define DSP_BASE 0xF1000000
491 #define NAND_BASE 0xF1010000
493 /****************************************************************/
496 #define CFG_NAND_LEGACY
497 #define CFG_NAND_BASE NAND_BASE
498 #define CONFIG_MTD_NAND_ECC_JFFS2
499 #define CONFIG_MTD_NAND_VERIFY_WRITE
500 #define CONFIG_MTD_NAND_UNSAFE
502 #define CFG_MAX_NAND_DEVICE 1
504 #define SECTORSIZE 512
505 #define ADDR_COLUMN 1
507 #define ADDR_COLUMN_PAGE 3
508 #define NAND_ChipID_UNKNOWN 0x00
509 #define NAND_MAX_FLOORS 1
510 #define NAND_MAX_CHIPS 1
512 /* ALE = PD17, CLE = PE18, CE = PE20, F_RY_BY = PE31 */
513 #define NAND_DISABLE_CE(nand) \
515 (((volatile immap_t *)CFG_IMMR)->im_cpm.cp_pedat) |= (1 << (31 - 20)); \
518 #define NAND_ENABLE_CE(nand) \
520 (((volatile immap_t *)CFG_IMMR)->im_cpm.cp_pedat) &= ~(1 << (31 - 20)); \
523 #define NAND_CTL_CLRALE(nandptr) \
525 (((volatile immap_t *)CFG_IMMR)->im_cpm.cp_pedat) &= ~(1 << (31 - 17)); \
528 #define NAND_CTL_SETALE(nandptr) \
530 (((volatile immap_t *)CFG_IMMR)->im_cpm.cp_pedat) |= (1 << (31 - 17)); \
533 #define NAND_CTL_CLRCLE(nandptr) \
535 (((volatile immap_t *)CFG_IMMR)->im_cpm.cp_pedat) &= ~(1 << (31 - 18)); \
538 #define NAND_CTL_SETCLE(nandptr) \
540 (((volatile immap_t *)CFG_IMMR)->im_cpm.cp_pedat) |= (1 << (31 - 18)); \
543 #if CONFIG_NETPHONE_VERSION == 1
544 #define NAND_WAIT_READY(nand) \
547 while ((((volatile immap_t *)CFG_IMMR)->im_cpm.cp_pedat & (1 << (31 - 31))) == 0) \
548 if (++_tries > 100000) \
551 #elif CONFIG_NETPHONE_VERSION == 2
552 #define NAND_WAIT_READY(nand) \
555 while ((((volatile immap_t *)CFG_IMMR)->im_ioport.iop_pcdat & (1 << (15 - 15))) == 0) \
556 if (++_tries > 100000) \
561 #define WRITE_NAND_COMMAND(d, adr) \
563 *(volatile unsigned char *)((unsigned long)(adr)) = (unsigned char)(d); \
566 #define WRITE_NAND_ADDRESS(d, adr) \
568 *(volatile unsigned char *)((unsigned long)(adr)) = (unsigned char)(d); \
571 #define WRITE_NAND(d, adr) \
573 *(volatile unsigned char *)((unsigned long)(adr)) = (unsigned char)(d); \
576 #define READ_NAND(adr) \
577 ((unsigned char)(*(volatile unsigned char *)(unsigned long)(adr)))
579 /*****************************************************************************/
581 #define CFG_DIRECT_FLASH_TFTP
582 #define CFG_DIRECT_NAND_TFTP
584 /*****************************************************************************/
586 #if CONFIG_NETPHONE_VERSION == 1
587 #define STATUS_LED_BIT 0x00000008 /* bit 28 */
588 #elif CONFIG_NETPHONE_VERSION == 2
589 #define STATUS_LED_BIT 0x00000080 /* bit 24 */
592 #define STATUS_LED_PERIOD (CFG_HZ / 2)
593 #define STATUS_LED_STATE STATUS_LED_BLINKING
595 #define STATUS_LED_ACTIVE 0 /* LED on for bit == 0 */
596 #define STATUS_LED_BOOT 0 /* LED 0 used for boot status */
602 /* led_id_t is unsigned int mask */
603 typedef unsigned int led_id_t;
605 #define __led_toggle(_msk) \
607 ((volatile immap_t *)CFG_IMMR)->im_cpm.cp_pedat ^= (_msk); \
610 #define __led_set(_msk, _st) \
613 ((volatile immap_t *)CFG_IMMR)->im_cpm.cp_pedat |= (_msk); \
615 ((volatile immap_t *)CFG_IMMR)->im_cpm.cp_pedat &= ~(_msk); \
618 #define __led_init(msk, st) __led_set(msk, st)
622 /***********************************************************************************************************
624 ----------------------------------------------------------------------------------------------
626 (V1) version 1 of the board
627 (V2) version 2 of the board
629 ----------------------------------------------------------------------------------------------
633 +------+----------------+--------+------------------------------------------------------------
634 | # | Name | Type | Comment
635 +------+----------------+--------+------------------------------------------------------------
636 | PA3 | SPIEN_MAX | Output | MAX serial to uart chip select
637 | PA7 | DSP_INT | Output | DSP interrupt
638 | PA10 | DSP_RESET | Output | DSP reset
639 | PA14 | USBOE | Output | USB (1)
640 | PA15 | USBRXD | Output | USB (1)
641 | PB19 | BT_RTS | Output | Bluetooth (0)
642 | PB23 | BT_CTS | Output | Bluetooth (0)
643 | PB26 | SPIEN_SEP | Output | Serial EEPROM chip select
644 | PB27 | SPICS_DISP | Output | Display chip select
645 | PB28 | SPI_RXD_3V | Input | SPI Data Rx
646 | PB29 | SPI_TXD | Output | SPI Data Tx
647 | PB30 | SPI_CLK | Output | SPI Clock
648 | PC10 | DISPA0 | Output | Display A0
649 | PC11 | BACKLIGHT | Output | Display backlit
650 | PC12 | SPI2RXD | Input | (V1) 2nd SPI RXD
651 | | IO_RESET | Output | (V2) General I/O reset
652 | PC13 | SPI2TXD | Output | (V1) 2nd SPI TXD (V1)
653 | | HOOK | Input | (V2) Hook input interrupt
654 | PC15 | SPI2CLK | Output | (V1) 2nd SPI CLK
655 | | F_RY_BY | Input | (V2) NAND F_RY_BY
656 | PE17 | F_ALE | Output | NAND F_ALE
657 | PE18 | F_CLE | Output | NAND F_CLE
658 | PE20 | F_CE | Output | NAND F_CE
659 | PE24 | SPICS_SCOUT | Output | (V1) Codec chip select
660 | | LED | Output | (V2) LED
661 | PE27 | SPICS_ER | Output | External serial register CS
662 | PE28 | LEDIO1 | Output | (V1) LED
663 | | BKBR1 | Input | (V2) Keyboard input scan
664 | PE29 | LEDIO2 | Output | (V1) LED hook for A (TA2)
665 | | BKBR2 | Input | (V2) Keyboard input scan
666 | PE30 | LEDIO3 | Output | (V1) LED hook for A (TA2)
667 | | BKBR3 | Input | (V2) Keyboard input scan
668 | PE31 | F_RY_BY | Input | (V1) NAND F_RY_BY
669 | | BKBR4 | Input | (V2) Keyboard input scan
670 +------+----------------+--------+---------------------------------------------------
672 ----------------------------------------------------------------------------------------------
674 Serial register input:
676 +------+----------------+------------------------------------------------------------
678 +------+----------------+------------------------------------------------------------
679 | 0 | BKBR1 | (V1) Keyboard input scan
680 | 1 | BKBR3 | (V1) Keyboard input scan
681 | 2 | BKBR4 | (V1) Keyboard input scan
682 | 3 | BKBR2 | (V1) Keyboard input scan
683 | 4 | HOOK | (V1) Hook switch
684 | 5 | BT_LINK | (V1) Bluetooth link status
685 | 6 | HOST_WAKE | (V1) Bluetooth host wake up
686 | 7 | OK_ETH | (V1) Cisco inline power OK status
687 +------+----------------+------------------------------------------------------------
689 ----------------------------------------------------------------------------------------------
691 Serial register output:
693 +------+----------------+------------------------------------------------------------
695 +------+----------------+------------------------------------------------------------
696 | 0 | KEY1 | Keyboard output scan
697 | 1 | KEY2 | Keyboard output scan
698 | 2 | KEY3 | Keyboard output scan
699 | 3 | KEY4 | Keyboard output scan
700 | 4 | KEY5 | Keyboard output scan
701 | 5 | KEY6 | Keyboard output scan
702 | 6 | KEY7 | Keyboard output scan
703 | 7 | BT_WAKE | Bluetooth wake up
704 +------+----------------+------------------------------------------------------------
706 ----------------------------------------------------------------------------------------------
710 +------+----------------+------------------------------------------------------------
712 +------+----------------+------------------------------------------------------------
713 | CS0 | CS0 | Boot flash
714 | CS1 | CS_FLASH | NAND flash
716 | CS3 | DCS_DRAM | DRAM
717 | CS4 | CS_FLASH2 | (V2) 2nd flash
718 +------+----------------+------------------------------------------------------------
720 ----------------------------------------------------------------------------------------------
724 +------+----------------+------------------------------------------------------------
726 +------+----------------+------------------------------------------------------------
727 | IRQ1 | IRQ_DSP | DSP interrupt
728 | IRQ3 | S_INTER | DUSLIC ???
729 | IRQ4 | F_RY_BY | NAND
730 | IRQ7 | IRQ_MAX | MAX 3100 interrupt
731 +------+----------------+------------------------------------------------------------
733 ----------------------------------------------------------------------------------------------
735 Interrupts on PCMCIA pins:
737 +------+----------------+------------------------------------------------------------
739 +------+----------------+------------------------------------------------------------
740 | IP_A0| PHY1_LINK | Link status changed for #1 Ethernet interface
741 | IP_A1| PHY2_LINK | Link status changed for #2 Ethernet interface
742 | IP_A2| RMII1_MDINT | PHY interrupt for #1
743 | IP_A3| RMII2_MDINT | PHY interrupt for #2
744 | IP_A5| HOST_WAKE | (V2) Bluetooth host wake
745 | IP_A6| OK_ETH | (V2) Cisco inline power OK
746 +------+----------------+------------------------------------------------------------
748 *************************************************************************************************/
750 #define CONFIG_SED156X 1 /* use SED156X */
751 #define CONFIG_SED156X_PG12864Q 1 /* type of display used */
753 /* serial interfacing macros */
755 #define SED156X_SPI_RXD_PORT (((volatile immap_t *)CFG_IMMR)->im_cpm.cp_pbdat)
756 #define SED156X_SPI_RXD_MASK 0x00000008
758 #define SED156X_SPI_TXD_PORT (((volatile immap_t *)CFG_IMMR)->im_cpm.cp_pbdat)
759 #define SED156X_SPI_TXD_MASK 0x00000004
761 #define SED156X_SPI_CLK_PORT (((volatile immap_t *)CFG_IMMR)->im_cpm.cp_pbdat)
762 #define SED156X_SPI_CLK_MASK 0x00000002
764 #define SED156X_CS_PORT (((volatile immap_t *)CFG_IMMR)->im_cpm.cp_pbdat)
765 #define SED156X_CS_MASK 0x00000010
767 #define SED156X_A0_PORT (((volatile immap_t *)CFG_IMMR)->im_ioport.iop_pcdat)
768 #define SED156X_A0_MASK 0x0020
770 /*************************************************************************************************/
772 #define CFG_CONSOLE_IS_IN_ENV 1
773 #define CFG_CONSOLE_OVERWRITE_ROUTINE 1
774 #define CFG_CONSOLE_ENV_OVERWRITE 1
776 /*************************************************************************************************/
778 /* use board specific hardware */
779 #undef CONFIG_WATCHDOG /* watchdog disabled */
780 #define CONFIG_HW_WATCHDOG
781 #define CONFIG_SHOW_ACTIVITY
783 /*************************************************************************************************/
785 /* phone console configuration */
787 #define PHONE_CONSOLE_POLL_HZ (CFG_HZ/200) /* poll every 5ms */
789 /*************************************************************************************************/
791 #define CONFIG_CDP_DEVICE_ID 20
792 #define CONFIG_CDP_DEVICE_ID_PREFIX "NP" /* netphone */
793 #define CONFIG_CDP_PORT_ID "eth%d"
794 #define CONFIG_CDP_CAPABILITIES 0x00000010
795 #define CONFIG_CDP_VERSION "u-boot" " " __DATE__ " " __TIME__
796 #define CONFIG_CDP_PLATFORM "Intracom NetPhone"
797 #define CONFIG_CDP_TRIGGER 0x20020001
798 #define CONFIG_CDP_POWER_CONSUMPTION 4300 /* 90 mA @ 48V */
799 #define CONFIG_CDP_APPLIANCE_VLAN_TYPE 0x01 /* ipphone */
801 /*************************************************************************************************/
803 #define CONFIG_AUTO_COMPLETE 1
805 /*************************************************************************************************/
807 #define CONFIG_CRC32_VERIFY 1
809 /*************************************************************************************************/
811 #define CONFIG_HUSH_OLD_PARSER_COMPATIBLE 1
813 /*************************************************************************************************/
814 #endif /* __CONFIG_H */