2 * (C) Copyright 2000-2010
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
5 * SPDX-License-Identifier: GPL-2.0+
9 * Pantelis Antoniou, Intracom S.A., panto@intracom.gr
10 * U-Boot port on NetTA4 board
17 * High Level Configuration Options
21 #define CONFIG_MPC885 1 /* This is a MPC885 CPU */
22 #define CONFIG_NETTA 1 /* ...on a NetTA board */
24 #define CONFIG_SYS_TEXT_BASE 0x40000000
26 #define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */
27 #undef CONFIG_8xx_CONS_SMC2
28 #undef CONFIG_8xx_CONS_NONE
30 #define CONFIG_BAUDRATE 115200 /* console baudrate = 115kbps */
32 /* #define CONFIG_XIN 10000000 */
33 #define CONFIG_XIN 50000000
34 #define MPC8XX_HZ 120000000
35 /* #define MPC8XX_HZ 100000000 */
36 /* #define MPC8XX_HZ 50000000 */
37 /* #define MPC8XX_HZ 80000000 */
39 #define CONFIG_8xx_GCLK_FREQ MPC8XX_HZ
42 #define CONFIG_BOOTDELAY -1 /* autoboot disabled */
44 #define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
47 #undef CONFIG_CLOCKS_IN_MHZ /* clocks NOT passsed to Linux in MHz */
49 #define CONFIG_PREBOOT "echo;echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;echo"
51 #undef CONFIG_BOOTARGS
52 #define CONFIG_BOOTCOMMAND \
54 "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \
55 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off;" \
58 #define CONFIG_LOADS_ECHO 0 /* echo off for serial download */
59 #undef CONFIG_SYS_LOADS_BAUD_CHANGE /* don't allow baudrate change */
61 #undef CONFIG_WATCHDOG /* watchdog disabled */
62 #define CONFIG_HW_WATCHDOG
64 #undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */
69 #define CONFIG_BOOTP_SUBNETMASK
70 #define CONFIG_BOOTP_GATEWAY
71 #define CONFIG_BOOTP_HOSTNAME
72 #define CONFIG_BOOTP_BOOTPATH
73 #define CONFIG_BOOTP_BOOTFILESIZE
74 #define CONFIG_BOOTP_NISDOMAIN
77 #undef CONFIG_MAC_PARTITION
78 #undef CONFIG_DOS_PARTITION
80 #define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */
82 #define FEC_ENET 1 /* eth.c needs it that way... */
83 #undef CONFIG_SYS_DISCOVER_PHY /* do not discover phys */
85 #define CONFIG_MII_INIT 1
86 #define CONFIG_RMII 1 /* use RMII interface */
88 #if defined(CONFIG_NETTA_ISDN)
89 #define CONFIG_ETHER_ON_FEC1 1
90 #define CONFIG_FEC1_PHY 1 /* phy address of FEC1 */
91 #define CONFIG_FEC1_PHY_NORXERR 1
92 #undef CONFIG_ETHER_ON_FEC2
94 #define CONFIG_ETHER_ON_FEC1 1
95 #define CONFIG_FEC1_PHY 8 /* phy address of FEC1 */
96 #define CONFIG_FEC1_PHY_NORXERR 1
97 #define CONFIG_ETHER_ON_FEC2 1
98 #define CONFIG_FEC2_PHY 1 /* phy address of FEC2 */
99 #define CONFIG_FEC2_PHY_NORXERR 1
102 #define CONFIG_ENV_OVERWRITE 1 /* allow modification of vendor params */
105 #define CONFIG_POST (CONFIG_SYS_POST_MEMORY | \
106 CONFIG_SYS_POST_CODEC | \
107 CONFIG_SYS_POST_DSP )
111 * Command line configuration.
113 #include <config_cmd_default.h>
115 #define CONFIG_CMD_CDP
116 #define CONFIG_CMD_DHCP
117 #define CONFIG_CMD_DIAG
118 #define CONFIG_CMD_FAT
119 #define CONFIG_CMD_IDE
120 #define CONFIG_CMD_JFFS2
121 #define CONFIG_CMD_MII
122 #define CONFIG_CMD_NFS
123 #define CONFIG_CMD_PCMCIA
124 #define CONFIG_CMD_PING
127 #define CONFIG_BOARD_EARLY_INIT_F 1
128 #define CONFIG_MISC_INIT_R
131 * Miscellaneous configurable options
133 #define CONFIG_SYS_LONGHELP /* undef to save memory */
135 #define CONFIG_SYS_HUSH_PARSER 1
137 #if defined(CONFIG_CMD_KGDB)
138 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
140 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
142 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
143 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */
144 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
146 #define CONFIG_SYS_MEMTEST_START 0x0300000 /* memtest works on */
147 #define CONFIG_SYS_MEMTEST_END 0x0700000 /* 3 ... 7 MB in DRAM */
149 #define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
151 #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
154 * Low Level Configuration Settings
155 * (address mappings, register initial values, etc.)
156 * You should know what you are doing if you make changes here.
158 /*-----------------------------------------------------------------------
159 * Internal Memory Mapped Register
161 #define CONFIG_SYS_IMMR 0xFF000000
163 /*-----------------------------------------------------------------------
164 * Definitions for initial stack pointer and data area (in DPRAM)
166 #define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR
167 #define CONFIG_SYS_INIT_RAM_SIZE 0x3000 /* Size of used area in DPRAM */
168 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
169 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
171 /*-----------------------------------------------------------------------
172 * Start addresses for the final memory configuration
173 * (Set up by the startup code)
174 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
176 #define CONFIG_SYS_SDRAM_BASE 0x00000000
177 #define CONFIG_SYS_FLASH_BASE 0x40000000
179 #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
181 #define CONFIG_SYS_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */
183 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
184 #define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
187 * For booting Linux, the board info and command line data
188 * have to be in the first 8 MB of memory, since this is
189 * the maximum mapped by the Linux kernel during initialization.
191 #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
193 /*-----------------------------------------------------------------------
196 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
197 #define CONFIG_SYS_MAX_FLASH_SECT 8 /* max number of sectors on one chip */
199 #define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
200 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
202 #define CONFIG_ENV_IS_IN_FLASH 1
203 #define CONFIG_ENV_SECT_SIZE 0x10000
205 #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x60000)
206 #define CONFIG_ENV_SIZE 0x4000
208 #define CONFIG_ENV_ADDR_REDUND (CONFIG_SYS_FLASH_BASE + 0x70000)
209 #define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE
211 /*-----------------------------------------------------------------------
212 * Cache Configuration
214 #define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
215 #if defined(CONFIG_CMD_KGDB)
216 #define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of the above value */
219 /*-----------------------------------------------------------------------
220 * SYPCR - System Protection Control 11-9
221 * SYPCR can only be written once after reset!
222 *-----------------------------------------------------------------------
223 * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
225 #if defined(CONFIG_WATCHDOG)
226 #define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
227 SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP)
229 #define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
232 /*-----------------------------------------------------------------------
233 * SIUMCR - SIU Module Configuration 11-6
234 *-----------------------------------------------------------------------
235 * PCMCIA config., multi-function pin tri-state
237 #ifndef CONFIG_CAN_DRIVER
238 #define CONFIG_SYS_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01 | SIUMCR_FRC)
239 #else /* we must activate GPL5 in the SIUMCR for CAN */
240 #define CONFIG_SYS_SIUMCR (SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01 | SIUMCR_FRC)
241 #endif /* CONFIG_CAN_DRIVER */
243 /*-----------------------------------------------------------------------
244 * TBSCR - Time Base Status and Control 11-26
245 *-----------------------------------------------------------------------
246 * Clear Reference Interrupt Status, Timebase freezing enabled
248 #define CONFIG_SYS_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
250 /*-----------------------------------------------------------------------
251 * RTCSC - Real-Time Clock Status and Control Register 11-27
252 *-----------------------------------------------------------------------
254 #define CONFIG_SYS_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)
256 /*-----------------------------------------------------------------------
257 * PISCR - Periodic Interrupt Status and Control 11-31
258 *-----------------------------------------------------------------------
259 * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
261 #define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF)
263 /*-----------------------------------------------------------------------
264 * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30
265 *-----------------------------------------------------------------------
266 * Reset PLL lock status sticky bit, timer expired status bit and timer
267 * interrupt status bit
271 #if CONFIG_XIN == 10000000
273 #if MPC8XX_HZ == 120000000
274 #define CONFIG_SYS_PLPRCR ((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \
275 (0 << PLPRCR_S_SHIFT) | (12 << PLPRCR_MFI_SHIFT) | (0 << PLPRCR_PDF_SHIFT) | \
277 #elif MPC8XX_HZ == 100000000
278 #define CONFIG_SYS_PLPRCR ((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \
279 (0 << PLPRCR_S_SHIFT) | (10 << PLPRCR_MFI_SHIFT) | (0 << PLPRCR_PDF_SHIFT) | \
281 #elif MPC8XX_HZ == 50000000
282 #define CONFIG_SYS_PLPRCR ((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \
283 (1 << PLPRCR_S_SHIFT) | (8 << PLPRCR_MFI_SHIFT) | (3 << PLPRCR_PDF_SHIFT) | \
285 #elif MPC8XX_HZ == 25000000
286 #define CONFIG_SYS_PLPRCR ((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \
287 (2 << PLPRCR_S_SHIFT) | (8 << PLPRCR_MFI_SHIFT) | (3 << PLPRCR_PDF_SHIFT) | \
289 #elif MPC8XX_HZ == 40000000
290 #define CONFIG_SYS_PLPRCR ((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \
291 (1 << PLPRCR_S_SHIFT) | (8 << PLPRCR_MFI_SHIFT) | (4 << PLPRCR_PDF_SHIFT) | \
293 #elif MPC8XX_HZ == 75000000
294 #define CONFIG_SYS_PLPRCR ((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \
295 (1 << PLPRCR_S_SHIFT) | (15 << PLPRCR_MFI_SHIFT) | (0 << PLPRCR_PDF_SHIFT) | \
298 #error unsupported CPU freq for XIN = 10MHz
301 #elif CONFIG_XIN == 50000000
303 #if MPC8XX_HZ == 120000000
304 #define CONFIG_SYS_PLPRCR ((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \
305 (0 << PLPRCR_S_SHIFT) | (12 << PLPRCR_MFI_SHIFT) | (4 << PLPRCR_PDF_SHIFT) | \
307 #elif MPC8XX_HZ == 100000000
308 #define CONFIG_SYS_PLPRCR ((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \
309 (0 << PLPRCR_S_SHIFT) | (6 << PLPRCR_MFI_SHIFT) | (2 << PLPRCR_PDF_SHIFT) | \
311 #elif MPC8XX_HZ == 80000000
312 #define CONFIG_SYS_PLPRCR ((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \
313 (0 << PLPRCR_S_SHIFT) | (8 << PLPRCR_MFI_SHIFT) | (4 << PLPRCR_PDF_SHIFT) | \
315 #elif MPC8XX_HZ == 50000000
316 #define CONFIG_SYS_PLPRCR ((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \
317 (1 << PLPRCR_S_SHIFT) | (6 << PLPRCR_MFI_SHIFT) | (2 << PLPRCR_PDF_SHIFT) | \
320 #error unsupported CPU freq for XIN = 50MHz
325 #error unsupported XIN freq
330 *-----------------------------------------------------------------------
331 * SCCR - System Clock and reset Control Register 15-27
332 *-----------------------------------------------------------------------
333 * Set clock output, timebase and RTC source and divider,
334 * power management and some other internal clocks
336 * Note: When TBS == 0 the timebase is independent of current cpu clock.
339 #define SCCR_MASK SCCR_EBDF11
340 #if MPC8XX_HZ > 66666666
341 #define CONFIG_SYS_SCCR (/* SCCR_TBS | */ SCCR_CRQEN | \
342 SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \
343 SCCR_DFNL111 | SCCR_DFNH000 | SCCR_DFLCD000 | \
344 SCCR_DFALCD00 | SCCR_EBDF01)
346 #define CONFIG_SYS_SCCR (/* SCCR_TBS | */ SCCR_CRQEN | \
347 SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \
348 SCCR_DFNL111 | SCCR_DFNH000 | SCCR_DFLCD000 | \
352 /*-----------------------------------------------------------------------
354 *-----------------------------------------------------------------------
357 /*#define CONFIG_SYS_DER 0x2002000F*/
358 #define CONFIG_SYS_DER 0
361 * Init Memory Controller:
363 * BR0/1 and OR0/1 (FLASH)
366 #define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */
368 /* used to re-map FLASH both when starting from SRAM or FLASH:
369 * restrict access enough to keep SRAM working (if any)
370 * but not too much to meddle with FLASH accesses
372 #define CONFIG_SYS_REMAP_OR_AM 0x80000000 /* OR addr mask */
373 #define CONFIG_SYS_PRELIM_OR_AM 0xE0000000 /* OR addr mask */
375 /* FLASH timing: ACS = 11, TRLX = 0, CSNT = 1, SCY = 5, EHTR = 1 */
376 #define CONFIG_SYS_OR_TIMING_FLASH (OR_CSNT_SAM | OR_BI | OR_SCY_5_CLK | OR_TRLX)
378 #define CONFIG_SYS_OR0_REMAP (CONFIG_SYS_REMAP_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
379 #define CONFIG_SYS_OR0_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
380 #define CONFIG_SYS_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_PS_8 | BR_V )
383 * BR3 and OR3 (SDRAM)
386 #define SDRAM_BASE3_PRELIM 0x00000000 /* SDRAM bank #0 */
387 #define SDRAM_MAX_SIZE (256 << 20) /* max 256MB per bank */
389 /* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */
390 #define CONFIG_SYS_OR_TIMING_SDRAM (OR_CSNT_SAM | OR_G5LS)
392 #define CONFIG_SYS_OR3_PRELIM ((0xFFFFFFFFLU & ~(SDRAM_MAX_SIZE - 1)) | CONFIG_SYS_OR_TIMING_SDRAM)
393 #define CONFIG_SYS_BR3_PRELIM ((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMB | BR_PS_32 | BR_V)
396 * Memory Periodic Timer Prescaler
400 * Memory Periodic Timer Prescaler
402 * The Divider for PTA (refresh timer) configuration is based on an
403 * example SDRAM configuration (64 MBit, one bank). The adjustment to
404 * the number of chip selects (NCS) and the actually needed refresh
405 * rate is done by setting MPTPR.
407 * PTA is calculated from
408 * PTA = (gclk * Trefresh) / ((2 ^ (2 * DFBRG)) * PTP * NCS)
410 * gclk CPU clock (not bus clock!)
411 * Trefresh Refresh cycle * 4 (four word bursts used)
413 * 4096 Rows from SDRAM example configuration
414 * 1000 factor s -> ms
415 * 32 PTP (pre-divider from MPTPR) from SDRAM example configuration
416 * 4 Number of refresh cycles per period
417 * 64 Refresh cycle in ms per number of rows
418 * --------------------------------------------
419 * Divider = 4096 * 32 * 1000 / (4 * 64) = 512000
421 * 50 MHz => 50.000.000 / Divider = 98
422 * 66 Mhz => 66.000.000 / Divider = 129
423 * 80 Mhz => 80.000.000 / Divider = 156
426 #if MPC8XX_HZ == 120000000
427 #define CONFIG_SYS_MAMR_PTA 234
428 #elif MPC8XX_HZ == 100000000
429 #define CONFIG_SYS_MAMR_PTA 195
430 #elif MPC8XX_HZ == 80000000
431 #define CONFIG_SYS_MAMR_PTA 156
432 #elif MPC8XX_HZ == 50000000
433 #define CONFIG_SYS_MAMR_PTA 98
435 #error Unknown frequency
440 * For 16 MBit, refresh rates could be 31.3 us
441 * (= 64 ms / 2K = 125 / quad bursts).
442 * For a simpler initialization, 15.6 us is used instead.
444 * #define CONFIG_SYS_MPTPR_2BK_2K MPTPR_PTP_DIV32 for 2 banks
445 * #define CONFIG_SYS_MPTPR_1BK_2K MPTPR_PTP_DIV64 for 1 bank
447 #define CONFIG_SYS_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */
448 #define CONFIG_SYS_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */
450 /* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */
451 #define CONFIG_SYS_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */
452 #define CONFIG_SYS_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */
455 * MAMR settings for SDRAM
459 #define CONFIG_SYS_MAMR_8COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
460 MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \
461 MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
464 #define CONFIG_SYS_MAMR_9COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
465 MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \
466 MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
468 #define CONFIG_LAST_STAGE_INIT /* needed to reset the damn phys */
470 /***********************************************************************************************************
474 +------+----------------+--------+------------------------------------------------------------
475 | # | Name | Type | Comment
476 +------+----------------+--------+------------------------------------------------------------
477 | PA3 | OK_ETH_3V | Input | CISCO Ethernet power OK
478 | | | | (NetRoute: FEC1, TA: FEC2) (0=power OK)
479 | PA6 | P_VCCD1 | Output | TPS2211A PCMCIA
480 | PA7 | DCL1_3V | Periph | IDL1 PCM clock
481 | PA8 | DSP_DR1 | Periph | IDL1 PCM Data Rx
482 | PA9 | L1TXDA | Periph | IDL1 PCM Data Tx
483 | PA10 | P_VCCD0 | Output | TPS2211A PCMCIA
484 | PA12 | P_SHDN | Output | TPS2211A PCMCIA
485 | PA13 | ETH_LOOP | Output | CISCO Loopback remote power
486 | | | | (NetRoute: FEC1, TA: FEC2) (1=NORMAL)
487 | PA14 | P_VPPD0 | Output | TPS2211A PCMCIA
488 | PA15 | P_VPPD1 | Output | TPS2211A PCMCIA
489 | PB14 | SPIEN_FXO | Output | SPI CS for FXO daughter-board
490 | PB15 | SPIEN_S1 | Output | SPI CS for S-interface 1 (NetRoute only)
491 | PB16 | DREQ1 | Output | D channel request for S-interface chip 1.
492 | PB17 | L1ST3 | Periph | IDL1 timeslot enable signal for PPC
493 | PB18 | L1ST2 | Periph | IDL1 timeslot enable signal for PPC
494 | PB19 | SPIEN_S2 | Output | SPI CS for S-interface 2 (NetRoute only)
495 | PB20 | SPIEN_SEEPROM | Output | SPI CS for serial eeprom
496 | PB21 | LEDIO | Output | Led mode indication for PHY
497 | PB22 | UART_CTS | Input | UART CTS
498 | PB23 | UART_RTS | Output | UART RTS
499 | PB24 | UART_RX | Periph | UART Data Rx
500 | PB25 | UART_TX | Periph | UART Data Tx
501 | PB26 | RMII-MDC | Periph | Free for future use (MII mgt clock)
502 | PB27 | RMII-MDIO | Periph | Free for future use (MII mgt data)
503 | PB28 | SPI_RXD_3V | Input | SPI Data Rx
504 | PB29 | SPI_TXD | Output | SPI Data Tx
505 | PB30 | SPI_CLK | Output | SPI Clock
506 | PB31 | RMII1-REFCLK | Periph | RMII reference clock for FEC1
507 | PC4 | PHY1_LINK | Input | PHY link state FEC1 (interrupt)
508 | PC5 | PHY2_LINK | Input | PHY link state FEC2 (interrupt)
509 | PC6 | RMII1-MDINT | Input | PHY prog interrupt FEC1 (interrupt)
510 | PC7 | RMII2-MDINT | Input | PHY prog interrupt FEC1 (interrupt)
511 | PC8 | P_OC | Input | TPS2211A PCMCIA overcurrent (interrupt) (1=OK)
512 | PC9 | COM_HOOK1 | Input | Codec interrupt chip #1 (interrupt)
513 | PC10 | COM_HOOK2 | Input | Codec interrupt chip #2 (interrupt)
514 | PC11 | COM_HOOK4 | Input | Codec interrupt chip #4 (interrupt)
515 | PC12 | COM_HOOK3 | Input | Codec interrupt chip #3 (interrupt)
516 | PC13 | F_RY_BY | Input | NAND ready signal (interrupt)
517 | PC14 | FAN_OK | Input | Fan status signal (interrupt) (1=OK)
518 | PC15 | PC15_DIRECT0 | Periph | PCMCIA DMA request.
519 | PD3 | F_ALE | Output | NAND
520 | PD4 | F_CLE | Output | NAND
521 | PD5 | F_CE | Output | NAND
522 | PD6 | DSP_INT | Output | DSP debug interrupt
523 | PD7 | DSP_RESET | Output | DSP reset
524 | PD8 | RMII_MDC | Periph | MII mgt clock
525 | PD9 | SPIEN_C1 | Output | SPI CS for codec #1
526 | PD10 | SPIEN_C2 | Output | SPI CS for codec #2
527 | PD11 | SPIEN_C3 | Output | SPI CS for codec #3
528 | PD12 | FSC2 | Periph | IDL2 frame sync
529 | PD13 | DGRANT2 | Input | D channel grant from S #2
530 | PD14 | SPIEN_C4 | Output | SPI CS for codec #4
531 | PD15 | TP700 | Output | Testpoint for software debugging
532 | PE14 | RMII2-TXD0 | Periph | FEC2 transmit data
533 | PE15 | RMII2-TXD1 | Periph | FEC2 transmit data
534 | PE16 | RMII2-REFCLK | Periph | TA: RMII ref clock for
535 | | DCL2 | Periph | NetRoute: PCM clock #2
536 | PE17 | TP703 | Output | Testpoint for software debugging
537 | PE18 | DGRANT1 | Input | D channel grant from S #1
538 | PE19 | RMII2-TXEN | Periph | TA: FEC2 tx enable
539 | | PCM2OUT | Periph | NetRoute: Tx data for IDL2
540 | PE20 | FSC1 | Periph | IDL1 frame sync
541 | PE21 | RMII2-RXD0 | Periph | FEC2 receive data
542 | PE22 | RMII2-RXD1 | Periph | FEC2 receive data
543 | PE23 | L1ST1 | Periph | IDL1 timeslot enable signal for PPC
544 | PE24 | U-N1 | Output | Select user/network for S #1 (0=user)
545 | PE25 | U-N2 | Output | Select user/network for S #2 (0=user)
546 | PE26 | RMII2-RXDV | Periph | FEC2 valid
547 | PE27 | DREQ2 | Output | D channel request for S #2.
548 | PE28 | FPGA_DONE | Input | FPGA done signal
549 | PE29 | FPGA_INIT | Output | FPGA init signal
550 | PE30 | UDOUT2_3V | Input | IDL2 PCM input
552 +------+----------------+--------+---------------------------------------------------
556 +------+----------------+------------------------------------------------------------
558 +------+----------------+------------------------------------------------------------
559 | CS0 | CS0 | Boot flash
560 | CS1 | CS_FLASH | NAND flash
562 | CS3 | DCS_DRAM | DRAM
563 | CS4 | CS_ER1 | External output register
564 +------+----------------+------------------------------------------------------------
568 +------+----------------+------------------------------------------------------------
570 +------+----------------+------------------------------------------------------------
571 | IRQ1 | UINTER_3V | S interrupt chips interrupt (common)
572 | IRQ3 | IRQ_DSP | DSP interrupt
573 | IRQ4 | IRQ_DSP1 | Extra DSP interrupt
574 +------+----------------+------------------------------------------------------------
576 *************************************************************************************************/
578 #define DSP_SIZE 0x00010000 /* 64K */
579 #define NAND_SIZE 0x00010000 /* 64K */
580 #define ER_SIZE 0x00010000 /* 64K */
581 #define DUMMY_SIZE 0x00010000 /* 64K */
583 #define DSP_BASE 0xF1000000
584 #define NAND_BASE 0xF1010000
585 #define ER_BASE 0xF1020000
586 #define DUMMY_BASE 0xF1FF0000
588 /*****************************************************************************/
590 #define CONFIG_SYS_DIRECT_FLASH_TFTP
591 #define CONFIG_SYS_DIRECT_NAND_TFTP
593 /*****************************************************************************/
596 /*-----------------------------------------------------------------------
598 *-----------------------------------------------------------------------
601 #define CONFIG_SYS_PCMCIA_MEM_ADDR (0xE0000000)
602 #define CONFIG_SYS_PCMCIA_MEM_SIZE ( 64 << 20 )
603 #define CONFIG_SYS_PCMCIA_DMA_ADDR (0xE4000000)
604 #define CONFIG_SYS_PCMCIA_DMA_SIZE ( 64 << 20 )
605 #define CONFIG_SYS_PCMCIA_ATTRB_ADDR (0xE8000000)
606 #define CONFIG_SYS_PCMCIA_ATTRB_SIZE ( 64 << 20 )
607 #define CONFIG_SYS_PCMCIA_IO_ADDR (0xEC000000)
608 #define CONFIG_SYS_PCMCIA_IO_SIZE ( 64 << 20 )
610 /*-----------------------------------------------------------------------
611 * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter)
612 *-----------------------------------------------------------------------
615 #define CONFIG_IDE_PREINIT 1 /* Use preinit IDE hook */
616 #define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */
618 #undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
619 #undef CONFIG_IDE_LED /* LED for ide not supported */
620 #undef CONFIG_IDE_RESET /* reset for ide not supported */
622 #define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */
623 #define CONFIG_SYS_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */
625 #define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000
627 #define CONFIG_SYS_ATA_BASE_ADDR CONFIG_SYS_PCMCIA_MEM_ADDR
629 /* Offset for data I/O */
630 #define CONFIG_SYS_ATA_DATA_OFFSET (CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320)
632 /* Offset for normal register accesses */
633 #define CONFIG_SYS_ATA_REG_OFFSET (2 * CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320)
635 /* Offset for alternate registers */
636 #define CONFIG_SYS_ATA_ALT_OFFSET 0x0100
638 #define CONFIG_MAC_PARTITION
639 #define CONFIG_DOS_PARTITION
642 /*************************************************************************************************/
644 #define CONFIG_CDP_DEVICE_ID 20
645 #define CONFIG_CDP_DEVICE_ID_PREFIX "NT" /* netta */
646 #define CONFIG_CDP_PORT_ID "eth%d"
647 #define CONFIG_CDP_CAPABILITIES 0x00000010
648 #define CONFIG_CDP_VERSION "u-boot 1.0" " " U_BOOT_DATE " " U_BOOT_TIME
649 #define CONFIG_CDP_PLATFORM "Intracom NetTA"
650 #define CONFIG_CDP_TRIGGER 0x20020001
651 #define CONFIG_CDP_POWER_CONSUMPTION 4300 /* 90 mA @ 48V */
652 #define CONFIG_CDP_APPLIANCE_VLAN_TYPE 0x01 /* ipphone? */
654 /*************************************************************************************************/
656 #define CONFIG_AUTO_COMPLETE 1
658 /*************************************************************************************************/
660 #define CONFIG_CRC32_VERIFY 1
662 /*************************************************************************************************/
664 #define CONFIG_HUSH_OLD_PARSER_COMPATIBLE 1
666 /*************************************************************************************************/
668 #endif /* __CONFIG_H */