git.sur5r.net Git - u-boot/blob - include/configs/P1010RDB.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * Copyright 2010-2011 Freescale Semiconductor, Inc.
   4  */
   5
   6 /*
   7  * P010 RDB board configuration file
   8  */
   9
  10 #ifndef __CONFIG_H
  11 #define __CONFIG_H
  12
  13 #include <asm/config_mpc85xx.h>
  14 #define CONFIG_NAND_FSL_IFC
  15
  16 #ifdef CONFIG_SDCARD
  17 #define CONFIG_SPL_FLUSH_IMAGE
  18 #define CONFIG_SPL_TARGET               "u-boot-with-spl.bin"
  19 #define CONFIG_SPL_TEXT_BASE            0xD0001000
  20 #define CONFIG_SPL_PAD_TO               0x18000
  21 #define CONFIG_SPL_MAX_SIZE             (96 * 1024)
  22 #define CONFIG_SYS_MMC_U_BOOT_SIZE      (512 << 10)
  23 #define CONFIG_SYS_MMC_U_BOOT_DST       (0x11000000)
  24 #define CONFIG_SYS_MMC_U_BOOT_START     (0x11000000)
  25 #define CONFIG_SYS_MMC_U_BOOT_OFFS      (96 << 10)
  26 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
  27 #define CONFIG_SYS_LDSCRIPT     "arch/powerpc/cpu/mpc85xx/u-boot.lds"
  28 #define CONFIG_SPL_MMC_BOOT
  29 #ifdef CONFIG_SPL_BUILD
  30 #define CONFIG_SPL_COMMON_INIT_DDR
  31 #endif
  32 #endif
  33
  34 #ifdef CONFIG_SPIFLASH
  35 #ifdef CONFIG_SECURE_BOOT
  36 #define CONFIG_RAMBOOT_SPIFLASH
  37 #define CONFIG_RESET_VECTOR_ADDRESS     0x110bfffc
  38 #else
  39 #define CONFIG_SPL_SPI_FLASH_MINIMAL
  40 #define CONFIG_SPL_FLUSH_IMAGE
  41 #define CONFIG_SPL_TARGET               "u-boot-with-spl.bin"
  42 #define CONFIG_SPL_TEXT_BASE                    0xD0001000
  43 #define CONFIG_SPL_PAD_TO                       0x18000
  44 #define CONFIG_SPL_MAX_SIZE                     (96 * 1024)
  45 #define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE        (512 << 10)
  46 #define CONFIG_SYS_SPI_FLASH_U_BOOT_DST         (0x11000000)
  47 #define CONFIG_SYS_SPI_FLASH_U_BOOT_START       (0x11000000)
  48 #define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS        (96 << 10)
  49 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
  50 #define CONFIG_SYS_LDSCRIPT     "arch/powerpc/cpu/mpc85xx/u-boot.lds"
  51 #define CONFIG_SPL_SPI_BOOT
  52 #ifdef CONFIG_SPL_BUILD
  53 #define CONFIG_SPL_COMMON_INIT_DDR
  54 #endif
  55 #endif
  56 #endif
  57
  58 #ifdef CONFIG_NAND
  59 #ifdef CONFIG_SECURE_BOOT
  60 #define CONFIG_SPL_INIT_MINIMAL
  61 #define CONFIG_SPL_NAND_BOOT
  62 #define CONFIG_SPL_FLUSH_IMAGE
  63 #define CONFIG_SPL_TARGET               "u-boot-with-spl.bin"
  64
  65 #define CONFIG_SPL_TEXT_BASE            0xFFFFE000
  66 #define CONFIG_SPL_MAX_SIZE             8192
  67 #define CONFIG_SPL_RELOC_TEXT_BASE      0x00100000
  68 #define CONFIG_SPL_RELOC_STACK          0x00100000
  69 #define CONFIG_SYS_NAND_U_BOOT_SIZE     ((768 << 10) - 0x2000)
  70 #define CONFIG_SYS_NAND_U_BOOT_DST      (0x00200000 - CONFIG_SPL_MAX_SIZE)
  71 #define CONFIG_SYS_NAND_U_BOOT_START    0x00200000
  72 #define CONFIG_SYS_NAND_U_BOOT_OFFS     0
  73 #define CONFIG_SYS_LDSCRIPT     "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
  74 #else
  75 #ifdef CONFIG_TPL_BUILD
  76 #define CONFIG_SPL_NAND_BOOT
  77 #define CONFIG_SPL_FLUSH_IMAGE
  78 #define CONFIG_SPL_NAND_INIT
  79 #define CONFIG_SPL_COMMON_INIT_DDR
  80 #define CONFIG_SPL_MAX_SIZE             (128 << 10)
  81 #define CONFIG_SPL_TEXT_BASE            0xD0001000
  82 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
  83 #define CONFIG_SYS_NAND_U_BOOT_SIZE     (576 << 10)
  84 #define CONFIG_SYS_NAND_U_BOOT_DST      (0x11000000)
  85 #define CONFIG_SYS_NAND_U_BOOT_START    (0x11000000)
  86 #define CONFIG_SYS_NAND_U_BOOT_OFFS     ((128 + 128) << 10)
  87 #elif defined(CONFIG_SPL_BUILD)
  88 #define CONFIG_SPL_INIT_MINIMAL
  89 #define CONFIG_SPL_NAND_MINIMAL
  90 #define CONFIG_SPL_FLUSH_IMAGE
  91 #define CONFIG_SPL_TEXT_BASE            0xff800000
  92 #define CONFIG_SPL_MAX_SIZE             8192
  93 #define CONFIG_SYS_NAND_U_BOOT_SIZE     (128 << 10)
  94 #define CONFIG_SYS_NAND_U_BOOT_DST      0xD0000000
  95 #define CONFIG_SYS_NAND_U_BOOT_START    0xD0000000
  96 #define CONFIG_SYS_NAND_U_BOOT_OFFS     (128 << 10)
  97 #endif
  98 #define CONFIG_SPL_PAD_TO       0x20000
  99 #define CONFIG_TPL_PAD_TO       0x20000
 100 #define CONFIG_SPL_TARGET       "u-boot-with-spl.bin"
 101 #define CONFIG_SYS_LDSCRIPT     "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
 102 #endif
 103 #endif
 104
 105 #ifdef CONFIG_NAND_SECBOOT      /* NAND Boot */
 106 #define CONFIG_RAMBOOT_NAND
 107 #define CONFIG_RESET_VECTOR_ADDRESS     0x110bfffc
 108 #endif
 109
 110 #ifndef CONFIG_RESET_VECTOR_ADDRESS
 111 #define CONFIG_RESET_VECTOR_ADDRESS     0xeffffffc
 112 #endif
 113
 114 #ifdef CONFIG_SPL_BUILD
 115 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
 116 #else
 117 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE    /* start of monitor */
 118 #endif
 119
 120 /* High Level Configuration Options */
 121 #define CONFIG_SYS_HAS_SERDES           /* common SERDES init code */
 122
 123 #if defined(CONFIG_PCI)
 124 #define CONFIG_PCIE1                    /* PCIE controller 1 (slot 1) */
 125 #define CONFIG_PCIE2                    /* PCIE controller 2 (slot 2) */
 126 #define CONFIG_FSL_PCI_INIT             /* Use common FSL init code */
 127 #define CONFIG_PCI_INDIRECT_BRIDGE      /* indirect PCI bridge support */
 128 #define CONFIG_FSL_PCIE_RESET           /* need PCIe reset errata */
 129 #define CONFIG_SYS_PCI_64BIT            /* enable 64-bit PCI resources */
 130
 131 /*
 132  * PCI Windows
 133  * Memory space is mapped 1-1, but I/O space must start from 0.
 134  */
 135 /* controller 1, Slot 1, tgtid 1, Base address a000 */
 136 #define CONFIG_SYS_PCIE1_NAME           "mini PCIe Slot"
 137 #define CONFIG_SYS_PCIE1_MEM_VIRT       0x80000000
 138 #ifdef CONFIG_PHYS_64BIT
 139 #define CONFIG_SYS_PCIE1_MEM_BUS        0x80000000
 140 #define CONFIG_SYS_PCIE1_MEM_PHYS       0xc00000000ull
 141 #else
 142 #define CONFIG_SYS_PCIE1_MEM_BUS        0x80000000
 143 #define CONFIG_SYS_PCIE1_MEM_PHYS       0x80000000
 144 #endif
 145 #define CONFIG_SYS_PCIE1_MEM_SIZE       0x20000000      /* 512M */
 146 #define CONFIG_SYS_PCIE1_IO_VIRT        0xffc00000
 147 #define CONFIG_SYS_PCIE1_IO_BUS         0x00000000
 148 #define CONFIG_SYS_PCIE1_IO_SIZE        0x00010000      /* 64k */
 149 #ifdef CONFIG_PHYS_64BIT
 150 #define CONFIG_SYS_PCIE1_IO_PHYS        0xfffc00000ull
 151 #else
 152 #define CONFIG_SYS_PCIE1_IO_PHYS        0xffc00000
 153 #endif
 154
 155 /* controller 2, Slot 2, tgtid 2, Base address 9000 */
 156 #if defined(CONFIG_TARGET_P1010RDB_PA)
 157 #define CONFIG_SYS_PCIE2_NAME           "PCIe Slot"
 158 #elif defined(CONFIG_TARGET_P1010RDB_PB)
 159 #define CONFIG_SYS_PCIE2_NAME           "mini PCIe Slot"
 160 #endif
 161 #define CONFIG_SYS_PCIE2_MEM_VIRT       0xa0000000
 162 #ifdef CONFIG_PHYS_64BIT
 163 #define CONFIG_SYS_PCIE2_MEM_BUS        0xc0000000
 164 #define CONFIG_SYS_PCIE2_MEM_PHYS       0xc20000000ull
 165 #else
 166 #define CONFIG_SYS_PCIE2_MEM_BUS        0xa0000000
 167 #define CONFIG_SYS_PCIE2_MEM_PHYS       0xa0000000
 168 #endif
 169 #define CONFIG_SYS_PCIE2_MEM_SIZE       0x20000000      /* 512M */
 170 #define CONFIG_SYS_PCIE2_IO_VIRT        0xffc10000
 171 #define CONFIG_SYS_PCIE2_IO_BUS         0x00000000
 172 #define CONFIG_SYS_PCIE2_IO_SIZE        0x00010000      /* 64k */
 173 #ifdef CONFIG_PHYS_64BIT
 174 #define CONFIG_SYS_PCIE2_IO_PHYS        0xfffc10000ull
 175 #else
 176 #define CONFIG_SYS_PCIE2_IO_PHYS        0xffc10000
 177 #endif
 178
 179 #define CONFIG_PCI_SCAN_SHOW            /* show pci devices on startup */
 180 #endif
 181
 182 #define CONFIG_ENV_OVERWRITE
 183
 184 #define CONFIG_DDR_CLK_FREQ     66666666 /* DDRCLK on P1010 RDB */
 185 #define CONFIG_SYS_CLK_FREQ     66666666 /* SYSCLK for P1010 RDB */
 186
 187 #define CONFIG_MISC_INIT_R
 188 #define CONFIG_HWCONFIG
 189 /*
 190  * These can be toggled for performance analysis, otherwise use default.
 191  */
 192 #define CONFIG_L2_CACHE                 /* toggle L2 cache */
 193 #define CONFIG_BTB                      /* toggle branch predition */
 194
 195
 196 #define CONFIG_ENABLE_36BIT_PHYS
 197
 198 #ifdef CONFIG_PHYS_64BIT
 199 #define CONFIG_ADDR_MAP                 1
 200 #define CONFIG_SYS_NUM_ADDR_MAP         16      /* number of TLB1 entries */
 201 #endif
 202
 203 #define CONFIG_SYS_MEMTEST_START        0x00200000      /* memtest works on */
 204 #define CONFIG_SYS_MEMTEST_END          0x1fffffff
 205
 206 /* DDR Setup */
 207 #define CONFIG_SYS_DDR_RAW_TIMING
 208 #define CONFIG_DDR_SPD
 209 #define CONFIG_SYS_SPD_BUS_NUM          1
 210 #define SPD_EEPROM_ADDRESS              0x52
 211
 212 #define CONFIG_MEM_INIT_VALUE           0xDeadBeef
 213
 214 #ifndef __ASSEMBLY__
 215 extern unsigned long get_sdram_size(void);
 216 #endif
 217 #define CONFIG_SYS_SDRAM_SIZE           get_sdram_size() /* DDR size */
 218 #define CONFIG_SYS_DDR_SDRAM_BASE       0x00000000
 219 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_SDRAM_BASE
 220
 221 #define CONFIG_DIMM_SLOTS_PER_CTLR      1
 222 #define CONFIG_CHIP_SELECTS_PER_CTRL    1
 223
 224 /* DDR3 Controller Settings */
 225 #define CONFIG_SYS_DDR_CS0_BNDS         0x0000003f
 226 #define CONFIG_SYS_DDR_CS0_CONFIG       0x80014302
 227 #define CONFIG_SYS_DDR_CS0_CONFIG_2     0x00000000
 228 #define CONFIG_SYS_DDR_DATA_INIT        0xdeadbeef
 229 #define CONFIG_SYS_DDR_INIT_ADDR        0x00000000
 230 #define CONFIG_SYS_DDR_INIT_EXT_ADDR    0x00000000
 231 #define CONFIG_SYS_DDR_MODE_CONTROL     0x00000000
 232 #define CONFIG_SYS_DDR_ZQ_CONTROL       0x89080600
 233 #define CONFIG_SYS_DDR_SR_CNTR          0x00000000
 234 #define CONFIG_SYS_DDR_RCW_1            0x00000000
 235 #define CONFIG_SYS_DDR_RCW_2            0x00000000
 236 #define CONFIG_SYS_DDR_CONTROL          0xc70c0008      /* Type = DDR3  */
 237 #define CONFIG_SYS_DDR_CONTROL_2        0x24401000
 238 #define CONFIG_SYS_DDR_TIMING_4         0x00000001
 239 #define CONFIG_SYS_DDR_TIMING_5         0x03402400
 240
 241 #define CONFIG_SYS_DDR_TIMING_3_800     0x00030000
 242 #define CONFIG_SYS_DDR_TIMING_0_800     0x00110104
 243 #define CONFIG_SYS_DDR_TIMING_1_800     0x6f6b8644
 244 #define CONFIG_SYS_DDR_TIMING_2_800     0x0FA888CF
 245 #define CONFIG_SYS_DDR_CLK_CTRL_800     0x03000000
 246 #define CONFIG_SYS_DDR_MODE_1_800       0x00441420
 247 #define CONFIG_SYS_DDR_MODE_2_800       0x00000000
 248 #define CONFIG_SYS_DDR_INTERVAL_800     0x0C300100
 249 #define CONFIG_SYS_DDR_WRLVL_CONTROL_800 0x8675f608
 250
 251 /* settings for DDR3 at 667MT/s */
 252 #define CONFIG_SYS_DDR_TIMING_3_667             0x00010000
 253 #define CONFIG_SYS_DDR_TIMING_0_667             0x00110004
 254 #define CONFIG_SYS_DDR_TIMING_1_667             0x5d59e544
 255 #define CONFIG_SYS_DDR_TIMING_2_667             0x0FA890CD
 256 #define CONFIG_SYS_DDR_CLK_CTRL_667             0x03000000
 257 #define CONFIG_SYS_DDR_MODE_1_667               0x00441210
 258 #define CONFIG_SYS_DDR_MODE_2_667               0x00000000
 259 #define CONFIG_SYS_DDR_INTERVAL_667             0x0a280000
 260 #define CONFIG_SYS_DDR_WRLVL_CONTROL_667        0x8675F608
 261
 262 #define CONFIG_SYS_CCSRBAR                      0xffe00000
 263 #define CONFIG_SYS_CCSRBAR_PHYS_LOW             CONFIG_SYS_CCSRBAR
 264
 265 /* Don't relocate CCSRBAR while in NAND_SPL */
 266 #ifdef CONFIG_SPL_BUILD
 267 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
 268 #endif
 269
 270 /*
 271  * Memory map
 272  *
 273  * 0x0000_0000  0x3fff_ffff     DDR                     1G cacheable
 274  * 0x8000_0000  0xbfff_ffff     PCI Express Mem         1.5G non-cacheable
 275  * 0xffc0_0000  0xffc3_ffff     PCI IO range            256k non-cacheable
 276  *
 277  * Localbus non-cacheable
 278  * 0xff80_0000  0xff8f_ffff     NAND Flash              1M non-cacheable
 279  * 0xffb0_0000  0xffbf_ffff     Board CPLD              1M non-cacheable
 280  * 0xffd0_0000  0xffd0_3fff     L1 for stack            16K Cacheable TLB0
 281  * 0xffe0_0000  0xffef_ffff     CCSR                    1M non-cacheable
 282  */
 283
 284 /*
 285  * IFC Definitions
 286  */
 287 /* NOR Flash on IFC */
 288
 289 #define CONFIG_SYS_FLASH_BASE           0xee000000
 290 #define CONFIG_SYS_MAX_FLASH_SECT       256     /* 32M */
 291
 292 #ifdef CONFIG_PHYS_64BIT
 293 #define CONFIG_SYS_FLASH_BASE_PHYS      (0xf00000000ull | CONFIG_SYS_FLASH_BASE)
 294 #else
 295 #define CONFIG_SYS_FLASH_BASE_PHYS      CONFIG_SYS_FLASH_BASE
 296 #endif
 297
 298 #define CONFIG_SYS_NOR_CSPR     (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
 299                                 CSPR_PORT_SIZE_16 | \
 300                                 CSPR_MSEL_NOR | \
 301                                 CSPR_V)
 302 #define CONFIG_SYS_NOR_AMASK    IFC_AMASK(32*1024*1024)
 303 #define CONFIG_SYS_NOR_CSOR     CSOR_NOR_ADM_SHIFT(7)
 304 /* NOR Flash Timing Params */
 305 #define CONFIG_SYS_NOR_FTIM0    FTIM0_NOR_TACSE(0x4) | \
 306                                 FTIM0_NOR_TEADC(0x5) | \
 307                                 FTIM0_NOR_TEAHC(0x5)
 308 #define CONFIG_SYS_NOR_FTIM1    FTIM1_NOR_TACO(0x1e) | \
 309                                 FTIM1_NOR_TRAD_NOR(0x0f)
 310 #define CONFIG_SYS_NOR_FTIM2    FTIM2_NOR_TCS(0x4) | \
 311                                 FTIM2_NOR_TCH(0x4) | \
 312                                 FTIM2_NOR_TWP(0x1c)
 313 #define CONFIG_SYS_NOR_FTIM3    0x0
 314
 315 #define CONFIG_SYS_FLASH_BANKS_LIST     {CONFIG_SYS_FLASH_BASE_PHYS}
 316 #define CONFIG_SYS_FLASH_QUIET_TEST
 317 #define CONFIG_FLASH_SHOW_PROGRESS      45      /* count down from 45/5: 9..1 */
 318 #define CONFIG_SYS_MAX_FLASH_BANKS      1       /* number of banks */
 319
 320 #undef CONFIG_SYS_FLASH_CHECKSUM
 321 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000   /* Flash Erase Timeout (ms) */
 322 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Flash Write Timeout (ms) */
 323
 324 /* CFI for NOR Flash */
 325 #define CONFIG_FLASH_CFI_DRIVER
 326 #define CONFIG_SYS_FLASH_CFI
 327 #define CONFIG_SYS_FLASH_EMPTY_INFO
 328 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
 329
 330 /* NAND Flash on IFC */
 331 #define CONFIG_SYS_NAND_BASE            0xff800000
 332 #ifdef CONFIG_PHYS_64BIT
 333 #define CONFIG_SYS_NAND_BASE_PHYS       0xfff800000ull
 334 #else
 335 #define CONFIG_SYS_NAND_BASE_PHYS       CONFIG_SYS_NAND_BASE
 336 #endif
 337
 338 #define CONFIG_MTD_DEVICE
 339 #define CONFIG_MTD_PARTITION
 340
 341 #define CONFIG_SYS_NAND_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
 342                                 | CSPR_PORT_SIZE_8      \
 343                                 | CSPR_MSEL_NAND        \
 344                                 | CSPR_V)
 345 #define CONFIG_SYS_NAND_AMASK   IFC_AMASK(64*1024)
 346
 347 #if defined(CONFIG_TARGET_P1010RDB_PA)
 348 #define CONFIG_SYS_NAND_CSOR    (CSOR_NAND_ECC_ENC_EN   /* ECC on encode */ \
 349                                 | CSOR_NAND_ECC_DEC_EN  /* ECC on decode */ \
 350                                 | CSOR_NAND_ECC_MODE_4  /* 4-bit ECC */ \
 351                                 | CSOR_NAND_RAL_2       /* RAL = 2 Bytes */ \
 352                                 | CSOR_NAND_PGS_512     /* Page Size = 512b */ \
 353                                 | CSOR_NAND_SPRZ_16     /* Spare size = 16 */ \
 354                                 | CSOR_NAND_PB(32))     /* 32 Pages Per Block */
 355 #define CONFIG_SYS_NAND_BLOCK_SIZE      (16 * 1024)
 356
 357 #elif defined(CONFIG_TARGET_P1010RDB_PB)
 358 #define CONFIG_SYS_NAND_ONFI_DETECTION
 359 #define CONFIG_SYS_NAND_CSOR   (CSOR_NAND_ECC_ENC_EN   /* ECC on encode */ \
 360                                 | CSOR_NAND_ECC_DEC_EN  /* ECC on decode */ \
 361                                 | CSOR_NAND_ECC_MODE_4  /* 4-bit ECC */ \
 362                                 | CSOR_NAND_RAL_3       /* RAL = 3Byes */ \
 363                                 | CSOR_NAND_PGS_4K      /* Page Size = 4K */ \
 364                                 | CSOR_NAND_SPRZ_224    /* Spare size = 224 */ \
 365                                 | CSOR_NAND_PB(128))  /*Pages Per Block = 128 */
 366 #define CONFIG_SYS_NAND_BLOCK_SIZE     (512 * 1024)
 367 #endif
 368
 369 #define CONFIG_SYS_NAND_BASE_LIST       { CONFIG_SYS_NAND_BASE }
 370 #define CONFIG_SYS_MAX_NAND_DEVICE      1
 371
 372 #if defined(CONFIG_TARGET_P1010RDB_PA)
 373 /* NAND Flash Timing Params */
 374 #define CONFIG_SYS_NAND_FTIM0           FTIM0_NAND_TCCST(0x01) | \
 375                                         FTIM0_NAND_TWP(0x0C)   | \
 376                                         FTIM0_NAND_TWCHT(0x04) | \
 377                                         FTIM0_NAND_TWH(0x05)
 378 #define CONFIG_SYS_NAND_FTIM1           FTIM1_NAND_TADLE(0x1d) | \
 379                                         FTIM1_NAND_TWBE(0x1d)  | \
 380                                         FTIM1_NAND_TRR(0x07)   | \
 381                                         FTIM1_NAND_TRP(0x0c)
 382 #define CONFIG_SYS_NAND_FTIM2           FTIM2_NAND_TRAD(0x0c) | \
 383                                         FTIM2_NAND_TREH(0x05) | \
 384                                         FTIM2_NAND_TWHRE(0x0f)
 385 #define CONFIG_SYS_NAND_FTIM3           FTIM3_NAND_TWW(0x04)
 386
 387 #elif defined(CONFIG_TARGET_P1010RDB_PB)
 388 /* support MT29F16G08ABABAWP 4k-pagesize 2G-bytes NAND */
 389 /* ONFI NAND Flash mode0 Timing Params */
 390 #define CONFIG_SYS_NAND_FTIM0  (FTIM0_NAND_TCCST(0x07)| \
 391                                         FTIM0_NAND_TWP(0x18)   | \
 392                                         FTIM0_NAND_TWCHT(0x07) | \
 393                                         FTIM0_NAND_TWH(0x0a))
 394 #define CONFIG_SYS_NAND_FTIM1  (FTIM1_NAND_TADLE(0x32)| \
 395                                         FTIM1_NAND_TWBE(0x39)  | \
 396                                         FTIM1_NAND_TRR(0x0e)   | \
 397                                         FTIM1_NAND_TRP(0x18))
 398 #define CONFIG_SYS_NAND_FTIM2  (FTIM2_NAND_TRAD(0x0f) | \
 399                                         FTIM2_NAND_TREH(0x0a)  | \
 400                                         FTIM2_NAND_TWHRE(0x1e))
 401 #define CONFIG_SYS_NAND_FTIM3   0x0
 402 #endif
 403
 404 #define CONFIG_SYS_NAND_DDR_LAW         11
 405
 406 /* Set up IFC registers for boot location NOR/NAND */
 407 #if defined(CONFIG_NAND) || defined(CONFIG_NAND_SECBOOT)
 408 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NAND_CSPR
 409 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NAND_AMASK
 410 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NAND_CSOR
 411 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NAND_FTIM0
 412 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NAND_FTIM1
 413 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NAND_FTIM2
 414 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NAND_FTIM3
 415 #define CONFIG_SYS_CSPR1                CONFIG_SYS_NOR_CSPR
 416 #define CONFIG_SYS_AMASK1               CONFIG_SYS_NOR_AMASK
 417 #define CONFIG_SYS_CSOR1                CONFIG_SYS_NOR_CSOR
 418 #define CONFIG_SYS_CS1_FTIM0            CONFIG_SYS_NOR_FTIM0
 419 #define CONFIG_SYS_CS1_FTIM1            CONFIG_SYS_NOR_FTIM1
 420 #define CONFIG_SYS_CS1_FTIM2            CONFIG_SYS_NOR_FTIM2
 421 #define CONFIG_SYS_CS1_FTIM3            CONFIG_SYS_NOR_FTIM3
 422 #else
 423 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NOR_CSPR
 424 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NOR_AMASK
 425 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NOR_CSOR
 426 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NOR_FTIM0
 427 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NOR_FTIM1
 428 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NOR_FTIM2
 429 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NOR_FTIM3
 430 #define CONFIG_SYS_CSPR1                CONFIG_SYS_NAND_CSPR
 431 #define CONFIG_SYS_AMASK1               CONFIG_SYS_NAND_AMASK
 432 #define CONFIG_SYS_CSOR1                CONFIG_SYS_NAND_CSOR
 433 #define CONFIG_SYS_CS1_FTIM0            CONFIG_SYS_NAND_FTIM0
 434 #define CONFIG_SYS_CS1_FTIM1            CONFIG_SYS_NAND_FTIM1
 435 #define CONFIG_SYS_CS1_FTIM2            CONFIG_SYS_NAND_FTIM2
 436 #define CONFIG_SYS_CS1_FTIM3            CONFIG_SYS_NAND_FTIM3
 437 #endif
 438
 439 /* CPLD on IFC */
 440 #define CONFIG_SYS_CPLD_BASE            0xffb00000
 441
 442 #ifdef CONFIG_PHYS_64BIT
 443 #define CONFIG_SYS_CPLD_BASE_PHYS       0xfffb00000ull
 444 #else
 445 #define CONFIG_SYS_CPLD_BASE_PHYS       CONFIG_SYS_CPLD_BASE
 446 #endif
 447
 448 #define CONFIG_SYS_CSPR3        (CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE_PHYS) \
 449                                 | CSPR_PORT_SIZE_8 \
 450                                 | CSPR_MSEL_GPCM \
 451                                 | CSPR_V)
 452 #define CONFIG_SYS_AMASK3               IFC_AMASK(64*1024)
 453 #define CONFIG_SYS_CSOR3                0x0
 454 /* CPLD Timing parameters for IFC CS3 */
 455 #define CONFIG_SYS_CS3_FTIM0            (FTIM0_GPCM_TACSE(0x0e) | \
 456                                         FTIM0_GPCM_TEADC(0x0e) | \
 457                                         FTIM0_GPCM_TEAHC(0x0e))
 458 #define CONFIG_SYS_CS3_FTIM1            (FTIM1_GPCM_TACO(0x0e) | \
 459                                         FTIM1_GPCM_TRAD(0x1f))
 460 #define CONFIG_SYS_CS3_FTIM2            (FTIM2_GPCM_TCS(0x0e) | \
 461                                         FTIM2_GPCM_TCH(0x8) | \
 462                                         FTIM2_GPCM_TWP(0x1f))
 463 #define CONFIG_SYS_CS3_FTIM3            0x0
 464
 465 #if defined(CONFIG_RAMBOOT_SDCARD) || defined(CONFIG_RAMBOOT_SPIFLASH) || \
 466         defined(CONFIG_RAMBOOT_NAND)
 467 #define CONFIG_SYS_RAMBOOT
 468 #define CONFIG_SYS_EXTRA_ENV_RELOC
 469 #else
 470 #undef CONFIG_SYS_RAMBOOT
 471 #endif
 472
 473 #ifdef CONFIG_SYS_FSL_ERRATUM_IFC_A003399
 474 #if !defined(CONFIG_SPL) && !defined(CONFIG_SYS_RAMBOOT)
 475 #define CONFIG_A003399_NOR_WORKAROUND
 476 #endif
 477 #endif
 478
 479 #define CONFIG_SYS_INIT_RAM_LOCK
 480 #define CONFIG_SYS_INIT_RAM_ADDR        0xffd00000 /* stack in RAM */
 481 #define CONFIG_SYS_INIT_RAM_SIZE        0x00004000 /* End of used area in RAM */
 482
 483 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE \
 484                                                 - GENERATED_GBL_DATA_SIZE)
 485 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 486
 487 #define CONFIG_SYS_MONITOR_LEN          (768 * 1024)
 488 #define CONFIG_SYS_MALLOC_LEN           (1024 * 1024)   /* Reserved for malloc*/
 489
 490 /*
 491  * Config the L2 Cache as L2 SRAM
 492  */
 493 #if defined(CONFIG_SPL_BUILD)
 494 #if defined(CONFIG_SDCARD) || defined(CONFIG_SPIFLASH)
 495 #define CONFIG_SYS_INIT_L2_ADDR         0xD0000000
 496 #define CONFIG_SYS_INIT_L2_ADDR_PHYS    CONFIG_SYS_INIT_L2_ADDR
 497 #define CONFIG_SYS_L2_SIZE              (256 << 10)
 498 #define CONFIG_SYS_INIT_L2_END  (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
 499 #define CONFIG_SPL_RELOC_TEXT_BASE      0xD0001000
 500 #define CONFIG_SPL_RELOC_STACK          (CONFIG_SYS_INIT_L2_ADDR + 112 * 1024)
 501 #define CONFIG_SPL_RELOC_STACK_SIZE     (16 << 10)
 502 #define CONFIG_SPL_RELOC_MALLOC_ADDR    (CONFIG_SYS_INIT_L2_ADDR + 128 * 1024)
 503 #define CONFIG_SPL_RELOC_MALLOC_SIZE    (128 << 10)
 504 #define CONFIG_SPL_GD_ADDR              (CONFIG_SYS_INIT_L2_ADDR + 96 * 1024)
 505 #elif defined(CONFIG_NAND)
 506 #ifdef CONFIG_TPL_BUILD
 507 #define CONFIG_SYS_INIT_L2_ADDR         0xD0000000
 508 #define CONFIG_SYS_INIT_L2_ADDR_PHYS    CONFIG_SYS_INIT_L2_ADDR
 509 #define CONFIG_SYS_L2_SIZE              (256 << 10)
 510 #define CONFIG_SYS_INIT_L2_END  (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
 511 #define CONFIG_SPL_RELOC_TEXT_BASE      0xD0001000
 512 #define CONFIG_SPL_RELOC_STACK          (CONFIG_SYS_INIT_L2_ADDR + 192 * 1024)
 513 #define CONFIG_SPL_RELOC_MALLOC_ADDR    (CONFIG_SYS_INIT_L2_ADDR + 208 * 1024)
 514 #define CONFIG_SPL_RELOC_MALLOC_SIZE    (48 << 10)
 515 #define CONFIG_SPL_GD_ADDR              (CONFIG_SYS_INIT_L2_ADDR + 176 * 1024)
 516 #else
 517 #define CONFIG_SYS_INIT_L2_ADDR         0xD0000000
 518 #define CONFIG_SYS_INIT_L2_ADDR_PHYS    CONFIG_SYS_INIT_L2_ADDR
 519 #define CONFIG_SYS_L2_SIZE              (256 << 10)
 520 #define CONFIG_SYS_INIT_L2_END  (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
 521 #define CONFIG_SPL_RELOC_TEXT_BASE      (CONFIG_SYS_INIT_L2_END - 0x3000)
 522 #define CONFIG_SPL_RELOC_STACK          ((CONFIG_SYS_INIT_L2_END - 1) & ~0xF)
 523 #endif
 524 #endif
 525 #endif
 526
 527 /* Serial Port */
 528 #undef  CONFIG_SERIAL_SOFTWARE_FIFO
 529 #define CONFIG_SYS_NS16550_SERIAL
 530 #define CONFIG_SYS_NS16550_REG_SIZE     1
 531 #define CONFIG_SYS_NS16550_CLK          get_bus_freq(0)
 532 #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_INIT_MINIMAL)
 533 #define CONFIG_NS16550_MIN_FUNCTIONS
 534 #endif
 535
 536 #define CONFIG_SYS_BAUDRATE_TABLE       \
 537         {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
 538
 539 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
 540 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
 541
 542 /* I2C */
 543 #define CONFIG_SYS_I2C
 544 #define CONFIG_SYS_I2C_FSL
 545 #define CONFIG_SYS_FSL_I2C_SPEED        400000
 546 #define CONFIG_SYS_FSL_I2C_SLAVE        0x7F
 547 #define CONFIG_SYS_FSL_I2C_OFFSET       0x3000
 548 #define CONFIG_SYS_FSL_I2C2_SPEED       400000
 549 #define CONFIG_SYS_FSL_I2C2_SLAVE       0x7F
 550 #define CONFIG_SYS_FSL_I2C2_OFFSET      0x3100
 551 #define I2C_PCA9557_ADDR1               0x18
 552 #define I2C_PCA9557_ADDR2               0x19
 553 #define I2C_PCA9557_BUS_NUM             0
 554
 555 /* I2C EEPROM */
 556 #if defined(CONFIG_TARGET_P1010RDB_PB)
 557 #define CONFIG_ID_EEPROM
 558 #ifdef CONFIG_ID_EEPROM
 559 #define CONFIG_SYS_I2C_EEPROM_NXID
 560 #endif
 561 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN  1
 562 #define CONFIG_SYS_I2C_EEPROM_ADDR      0x57
 563 #define CONFIG_SYS_EEPROM_BUS_NUM       0
 564 #define MAX_NUM_PORTS                   9 /* for 128Bytes EEPROM */
 565 #endif
 566 /* enable read and write access to EEPROM */
 567 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
 568 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
 569 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
 570
 571 /* RTC */
 572 #define CONFIG_RTC_PT7C4338
 573 #define CONFIG_SYS_I2C_RTC_ADDR 0x68
 574
 575 /*
 576  * SPI interface will not be available in case of NAND boot SPI CS0 will be
 577  * used for SLIC
 578  */
 579 #if !defined(CONFIG_NAND) || !defined(CONFIG_NAND_SECBOOT)
 580 /* eSPI - Enhanced SPI */
 581 #define CONFIG_SF_DEFAULT_SPEED         10000000
 582 #define CONFIG_SF_DEFAULT_MODE          SPI_MODE_0
 583 #endif
 584
 585 #if defined(CONFIG_TSEC_ENET)
 586 #define CONFIG_MII                      /* MII PHY management */
 587 #define CONFIG_MII_DEFAULT_TSEC 1       /* Allow unregistered phys */
 588 #define CONFIG_TSEC1    1
 589 #define CONFIG_TSEC1_NAME       "eTSEC1"
 590 #define CONFIG_TSEC2    1
 591 #define CONFIG_TSEC2_NAME       "eTSEC2"
 592 #define CONFIG_TSEC3    1
 593 #define CONFIG_TSEC3_NAME       "eTSEC3"
 594
 595 #define TSEC1_PHY_ADDR          1
 596 #define TSEC2_PHY_ADDR          0
 597 #define TSEC3_PHY_ADDR          2
 598
 599 #define TSEC1_FLAGS             (TSEC_GIGABIT | TSEC_REDUCED)
 600 #define TSEC2_FLAGS             (TSEC_GIGABIT | TSEC_REDUCED)
 601 #define TSEC3_FLAGS             (TSEC_GIGABIT | TSEC_REDUCED)
 602
 603 #define TSEC1_PHYIDX            0
 604 #define TSEC2_PHYIDX            0
 605 #define TSEC3_PHYIDX            0
 606
 607 #define CONFIG_ETHPRIME         "eTSEC1"
 608
 609 /* TBI PHY configuration for SGMII mode */
 610 #define CONFIG_TSEC_TBICR_SETTINGS ( \
 611                 TBICR_PHY_RESET \
 612                 | TBICR_ANEG_ENABLE \
 613                 | TBICR_FULL_DUPLEX \
 614                 | TBICR_SPEED1_SET \
 615                 )
 616
 617 #endif  /* CONFIG_TSEC_ENET */
 618
 619 /* SATA */
 620 #define CONFIG_FSL_SATA_V2
 621
 622 #ifdef CONFIG_FSL_SATA
 623 #define CONFIG_SYS_SATA_MAX_DEVICE      2
 624 #define CONFIG_SATA1
 625 #define CONFIG_SYS_SATA1                CONFIG_SYS_MPC85xx_SATA1_ADDR
 626 #define CONFIG_SYS_SATA1_FLAGS          FLAGS_DMA
 627 #define CONFIG_SATA2
 628 #define CONFIG_SYS_SATA2                CONFIG_SYS_MPC85xx_SATA2_ADDR
 629 #define CONFIG_SYS_SATA2_FLAGS          FLAGS_DMA
 630
 631 #define CONFIG_LBA48
 632 #endif /* #ifdef CONFIG_FSL_SATA  */
 633
 634 #ifdef CONFIG_MMC
 635 #define CONFIG_SYS_FSL_ESDHC_ADDR       CONFIG_SYS_MPC85xx_ESDHC_ADDR
 636 #endif
 637
 638 #define CONFIG_HAS_FSL_DR_USB
 639
 640 #if defined(CONFIG_HAS_FSL_DR_USB)
 641 #ifdef CONFIG_USB_EHCI_HCD
 642 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
 643 #define CONFIG_USB_EHCI_FSL
 644 #endif
 645 #endif
 646
 647 /*
 648  * Environment
 649  */
 650 #if defined(CONFIG_SDCARD)
 651 #define CONFIG_FSL_FIXED_MMC_LOCATION
 652 #define CONFIG_SYS_MMC_ENV_DEV          0
 653 #define CONFIG_ENV_SIZE                 0x2000
 654 #elif defined(CONFIG_SPIFLASH)
 655 #define CONFIG_ENV_SPI_BUS      0
 656 #define CONFIG_ENV_SPI_CS       0
 657 #define CONFIG_ENV_SPI_MAX_HZ   10000000
 658 #define CONFIG_ENV_SPI_MODE     0
 659 #define CONFIG_ENV_OFFSET       0x100000        /* 1MB */
 660 #define CONFIG_ENV_SECT_SIZE    0x10000
 661 #define CONFIG_ENV_SIZE         0x2000
 662 #elif defined(CONFIG_NAND)
 663 #ifdef CONFIG_TPL_BUILD
 664 #define CONFIG_ENV_SIZE         0x2000
 665 #define CONFIG_ENV_ADDR         (CONFIG_SYS_INIT_L2_ADDR + (160 << 10))
 666 #else
 667 #if defined(CONFIG_TARGET_P1010RDB_PA)
 668 #define CONFIG_ENV_SIZE         CONFIG_SYS_NAND_BLOCK_SIZE
 669 #define CONFIG_ENV_RANGE        (3 * CONFIG_ENV_SIZE) /* 3*16=48K for env */
 670 #elif defined(CONFIG_TARGET_P1010RDB_PB)
 671 #define CONFIG_ENV_SIZE         (16 * 1024)
 672 #define CONFIG_ENV_RANGE        (32 * CONFIG_ENV_SIZE) /* new block size 512K */
 673 #endif
 674 #endif
 675 #define CONFIG_ENV_OFFSET       (1024 * 1024)
 676 #elif defined(CONFIG_SYS_RAMBOOT)
 677 #define CONFIG_ENV_ADDR                 (CONFIG_SYS_MONITOR_BASE - 0x1000)
 678 #define CONFIG_ENV_SIZE                 0x2000
 679 #else
 680 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
 681 #define CONFIG_ENV_SIZE         0x2000
 682 #define CONFIG_ENV_SECT_SIZE    0x20000 /* 128K (one sector) */
 683 #endif
 684
 685 #define CONFIG_LOADS_ECHO               /* echo on for serial download */
 686 #define CONFIG_SYS_LOADS_BAUD_CHANGE    /* allow baudrate change */
 687
 688 #undef CONFIG_WATCHDOG                  /* watchdog disabled */
 689
 690 #if defined(CONFIG_MMC) || defined(CONFIG_USB_EHCI_HCD) \
 691                  || defined(CONFIG_FSL_SATA)
 692 #endif
 693
 694 /*
 695  * Miscellaneous configurable options
 696  */
 697 #define CONFIG_SYS_LOAD_ADDR    0x2000000       /* default load address */
 698
 699 /*
 700  * For booting Linux, the board info and command line data
 701  * have to be in the first 64 MB of memory, since this is
 702  * the maximum mapped by the Linux kernel during initialization.
 703  */
 704 #define CONFIG_SYS_BOOTMAPSZ    (64 << 20) /* Initial Memory map for Linux */
 705 #define CONFIG_SYS_BOOTM_LEN    (64 << 20) /* Increase max gunzip size */
 706
 707 #if defined(CONFIG_CMD_KGDB)
 708 #define CONFIG_KGDB_BAUDRATE    230400  /* speed to run kgdb serial port */
 709 #endif
 710
 711 /*
 712  * Environment Configuration
 713  */
 714
 715 #if defined(CONFIG_TSEC_ENET)
 716 #define CONFIG_HAS_ETH0
 717 #define CONFIG_HAS_ETH1
 718 #define CONFIG_HAS_ETH2
 719 #endif
 720
 721 #define CONFIG_ROOTPATH         "/opt/nfsroot"
 722 #define CONFIG_BOOTFILE         "uImage"
 723 #define CONFIG_UBOOTPATH        u-boot.bin/* U-Boot image on TFTP server */
 724
 725 /* default location for tftp and bootm */
 726 #define CONFIG_LOADADDR         1000000
 727
 728 #define CONFIG_EXTRA_ENV_SETTINGS                               \
 729         "hwconfig=" __stringify(CONFIG_DEF_HWCONFIG)  "\0"      \
 730         "netdev=eth0\0"                                         \
 731         "uboot=" __stringify(CONFIG_UBOOTPATH) "\0"             \
 732         "loadaddr=1000000\0"                    \
 733         "consoledev=ttyS0\0"                            \
 734         "ramdiskaddr=2000000\0"                 \
 735         "ramdiskfile=rootfs.ext2.gz.uboot\0"            \
 736         "fdtaddr=1e00000\0"                             \
 737         "fdtfile=p1010rdb.dtb\0"                \
 738         "bdev=sda1\0"   \
 739         "hwconfig=usb1:dr_mode=host,phy_type=utmi\0"    \
 740         "othbootargs=ramdisk_size=600000\0" \
 741         "usbfatboot=setenv bootargs root=/dev/ram rw "  \
 742         "console=$consoledev,$baudrate $othbootargs; "  \
 743         "usb start;"                    \
 744         "fatload usb 0:2 $loadaddr $bootfile;"          \
 745         "fatload usb 0:2 $fdtaddr $fdtfile;"    \
 746         "fatload usb 0:2 $ramdiskaddr $ramdiskfile;"    \
 747         "bootm $loadaddr $ramdiskaddr $fdtaddr\0"               \
 748         "usbext2boot=setenv bootargs root=/dev/ram rw " \
 749         "console=$consoledev,$baudrate $othbootargs; "  \
 750         "usb start;"                    \
 751         "ext2load usb 0:4 $loadaddr $bootfile;"         \
 752         "ext2load usb 0:4 $fdtaddr $fdtfile;"   \
 753         "ext2load usb 0:4 $ramdiskaddr $ramdiskfile;"   \
 754         "bootm $loadaddr $ramdiskaddr $fdtaddr\0"       \
 755         CONFIG_BOOTMODE
 756
 757 #if defined(CONFIG_TARGET_P1010RDB_PA)
 758 #define CONFIG_BOOTMODE \
 759         "boot_bank0=i2c dev 0; i2c mw 18 1 f1; i2c mw 18 3 f0;" \
 760         "mw.b ffb00011 0; mw.b ffb00009 0; reset\0" \
 761         "boot_bank1=i2c dev 0; i2c mw 18 1 f1; i2c mw 18 3 f0;" \
 762         "mw.b ffb00011 0; mw.b ffb00009 1; reset\0" \
 763         "boot_nand=i2c dev 0; i2c mw 18 1 f9; i2c mw 18 3 f0;" \
 764         "mw.b ffb00011 0; mw.b ffb00017 1; reset\0"
 765
 766 #elif defined(CONFIG_TARGET_P1010RDB_PB)
 767 #define CONFIG_BOOTMODE \
 768         "boot_bank0=i2c dev 0; i2c mw 18 1 fe; i2c mw 18 3 0;" \
 769         "i2c mw 19 1 2; i2c mw 19 3 e1; reset\0" \
 770         "boot_bank1=i2c dev 0; i2c mw 18 1 fe; i2c mw 18 3 0;" \
 771         "i2c mw 19 1 12; i2c mw 19 3 e1; reset\0" \
 772         "boot_nand=i2c dev 0; i2c mw 18 1 fc; i2c mw 18 3 0;" \
 773         "i2c mw 19 1 8; i2c mw 19 3 f7; reset\0" \
 774         "boot_spi=i2c dev 0; i2c mw 18 1 fa; i2c mw 18 3 0;" \
 775         "i2c mw 19 1 0; i2c mw 19 3 f7; reset\0" \
 776         "boot_sd=i2c dev 0; i2c mw 18 1 f8; i2c mw 18 3 0;" \
 777         "i2c mw 19 1 4; i2c mw 19 3 f3; reset\0"
 778 #endif
 779
 780 #define CONFIG_RAMBOOTCOMMAND           \
 781         "setenv bootargs root=/dev/ram rw "     \
 782         "console=$consoledev,$baudrate $othbootargs; "  \
 783         "tftp $ramdiskaddr $ramdiskfile;"       \
 784         "tftp $loadaddr $bootfile;"             \
 785         "tftp $fdtaddr $fdtfile;"               \
 786         "bootm $loadaddr $ramdiskaddr $fdtaddr"
 787
 788 #define CONFIG_BOOTCOMMAND CONFIG_RAMBOOTCOMMAND
 789
 790 #include <asm/fsl_secure_boot.h>
 791
 792 #endif  /* __CONFIG_H */