git.sur5r.net Git - u-boot/blob - include/configs/P1010RDB.h

   1 /*
   2  * Copyright 2010-2011 Freescale Semiconductor, Inc.
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+
   5  */
   6
   7 /*
   8  * P010 RDB board configuration file
   9  */
  10
  11 #ifndef __CONFIG_H
  12 #define __CONFIG_H
  13
  14 #include <asm/config_mpc85xx.h>
  15 #define CONFIG_NAND_FSL_IFC
  16
  17 #ifdef CONFIG_SDCARD
  18 #define CONFIG_SPL_MMC_MINIMAL
  19 #define CONFIG_SPL_FLUSH_IMAGE
  20 #define CONFIG_SPL_TARGET               "u-boot-with-spl.bin"
  21 #define CONFIG_SYS_TEXT_BASE            0x11001000
  22 #define CONFIG_SPL_TEXT_BASE            0xD0001000
  23 #define CONFIG_SPL_PAD_TO               0x18000
  24 #define CONFIG_SPL_MAX_SIZE             (96 * 1024)
  25 #define CONFIG_SYS_MMC_U_BOOT_SIZE      (512 << 10)
  26 #define CONFIG_SYS_MMC_U_BOOT_DST       (0x11000000)
  27 #define CONFIG_SYS_MMC_U_BOOT_START     (0x11000000)
  28 #define CONFIG_SYS_MMC_U_BOOT_OFFS      (96 << 10)
  29 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
  30 #define CONFIG_SYS_LDSCRIPT     "arch/powerpc/cpu/mpc85xx/u-boot.lds"
  31 #define CONFIG_SPL_MMC_BOOT
  32 #ifdef CONFIG_SPL_BUILD
  33 #define CONFIG_SPL_COMMON_INIT_DDR
  34 #endif
  35 #endif
  36
  37 #ifdef CONFIG_SPIFLASH
  38 #ifdef CONFIG_SECURE_BOOT
  39 #define CONFIG_RAMBOOT_SPIFLASH
  40 #define CONFIG_SYS_TEXT_BASE            0x11000000
  41 #define CONFIG_RESET_VECTOR_ADDRESS     0x110bfffc
  42 #else
  43 #define CONFIG_SPL_SPI_FLASH_MINIMAL
  44 #define CONFIG_SPL_FLUSH_IMAGE
  45 #define CONFIG_SPL_TARGET               "u-boot-with-spl.bin"
  46 #define CONFIG_SYS_TEXT_BASE                    0x11001000
  47 #define CONFIG_SPL_TEXT_BASE                    0xD0001000
  48 #define CONFIG_SPL_PAD_TO                       0x18000
  49 #define CONFIG_SPL_MAX_SIZE                     (96 * 1024)
  50 #define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE        (512 << 10)
  51 #define CONFIG_SYS_SPI_FLASH_U_BOOT_DST         (0x11000000)
  52 #define CONFIG_SYS_SPI_FLASH_U_BOOT_START       (0x11000000)
  53 #define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS        (96 << 10)
  54 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
  55 #define CONFIG_SYS_LDSCRIPT     "arch/powerpc/cpu/mpc85xx/u-boot.lds"
  56 #define CONFIG_SPL_SPI_BOOT
  57 #ifdef CONFIG_SPL_BUILD
  58 #define CONFIG_SPL_COMMON_INIT_DDR
  59 #endif
  60 #endif
  61 #endif
  62
  63 #ifdef CONFIG_NAND
  64 #ifdef CONFIG_SECURE_BOOT
  65 #define CONFIG_SPL_INIT_MINIMAL
  66 #define CONFIG_SPL_NAND_BOOT
  67 #define CONFIG_SPL_FLUSH_IMAGE
  68 #define CONFIG_SPL_TARGET               "u-boot-with-spl.bin"
  69
  70 #define CONFIG_SYS_TEXT_BASE            0x00201000
  71 #define CONFIG_SPL_TEXT_BASE            0xFFFFE000
  72 #define CONFIG_SPL_MAX_SIZE             8192
  73 #define CONFIG_SPL_RELOC_TEXT_BASE      0x00100000
  74 #define CONFIG_SPL_RELOC_STACK          0x00100000
  75 #define CONFIG_SYS_NAND_U_BOOT_SIZE     ((768 << 10) - 0x2000)
  76 #define CONFIG_SYS_NAND_U_BOOT_DST      (0x00200000 - CONFIG_SPL_MAX_SIZE)
  77 #define CONFIG_SYS_NAND_U_BOOT_START    0x00200000
  78 #define CONFIG_SYS_NAND_U_BOOT_OFFS     0
  79 #define CONFIG_SYS_LDSCRIPT     "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
  80 #else
  81 #ifdef CONFIG_TPL_BUILD
  82 #define CONFIG_SPL_NAND_BOOT
  83 #define CONFIG_SPL_FLUSH_IMAGE
  84 #define CONFIG_SPL_NAND_INIT
  85 #define CONFIG_SPL_COMMON_INIT_DDR
  86 #define CONFIG_SPL_MAX_SIZE             (128 << 10)
  87 #define CONFIG_SPL_TEXT_BASE            0xD0001000
  88 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
  89 #define CONFIG_SYS_NAND_U_BOOT_SIZE     (576 << 10)
  90 #define CONFIG_SYS_NAND_U_BOOT_DST      (0x11000000)
  91 #define CONFIG_SYS_NAND_U_BOOT_START    (0x11000000)
  92 #define CONFIG_SYS_NAND_U_BOOT_OFFS     ((128 + 128) << 10)
  93 #elif defined(CONFIG_SPL_BUILD)
  94 #define CONFIG_SPL_INIT_MINIMAL
  95 #define CONFIG_SPL_NAND_MINIMAL
  96 #define CONFIG_SPL_FLUSH_IMAGE
  97 #define CONFIG_SPL_TEXT_BASE            0xff800000
  98 #define CONFIG_SPL_MAX_SIZE             8192
  99 #define CONFIG_SYS_NAND_U_BOOT_SIZE     (128 << 10)
 100 #define CONFIG_SYS_NAND_U_BOOT_DST      0xD0000000
 101 #define CONFIG_SYS_NAND_U_BOOT_START    0xD0000000
 102 #define CONFIG_SYS_NAND_U_BOOT_OFFS     (128 << 10)
 103 #endif
 104 #define CONFIG_SPL_PAD_TO       0x20000
 105 #define CONFIG_TPL_PAD_TO       0x20000
 106 #define CONFIG_SPL_TARGET       "u-boot-with-spl.bin"
 107 #define CONFIG_SYS_TEXT_BASE    0x11001000
 108 #define CONFIG_SYS_LDSCRIPT     "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
 109 #endif
 110 #endif
 111
 112 #ifdef CONFIG_NAND_SECBOOT      /* NAND Boot */
 113 #define CONFIG_RAMBOOT_NAND
 114 #define CONFIG_SYS_TEXT_BASE            0x11000000
 115 #define CONFIG_RESET_VECTOR_ADDRESS     0x110bfffc
 116 #endif
 117
 118 #ifndef CONFIG_SYS_TEXT_BASE
 119 #define CONFIG_SYS_TEXT_BASE            0xeff40000
 120 #endif
 121
 122 #ifndef CONFIG_RESET_VECTOR_ADDRESS
 123 #define CONFIG_RESET_VECTOR_ADDRESS     0xeffffffc
 124 #endif
 125
 126 #ifdef CONFIG_SPL_BUILD
 127 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
 128 #else
 129 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE    /* start of monitor */
 130 #endif
 131
 132 /* High Level Configuration Options */
 133 #define CONFIG_SYS_HAS_SERDES           /* common SERDES init code */
 134
 135 #if defined(CONFIG_PCI)
 136 #define CONFIG_PCIE1                    /* PCIE controller 1 (slot 1) */
 137 #define CONFIG_PCIE2                    /* PCIE controller 2 (slot 2) */
 138 #define CONFIG_FSL_PCI_INIT             /* Use common FSL init code */
 139 #define CONFIG_PCI_INDIRECT_BRIDGE      /* indirect PCI bridge support */
 140 #define CONFIG_FSL_PCIE_RESET           /* need PCIe reset errata */
 141 #define CONFIG_SYS_PCI_64BIT            /* enable 64-bit PCI resources */
 142
 143 /*
 144  * PCI Windows
 145  * Memory space is mapped 1-1, but I/O space must start from 0.
 146  */
 147 /* controller 1, Slot 1, tgtid 1, Base address a000 */
 148 #define CONFIG_SYS_PCIE1_NAME           "mini PCIe Slot"
 149 #define CONFIG_SYS_PCIE1_MEM_VIRT       0x80000000
 150 #ifdef CONFIG_PHYS_64BIT
 151 #define CONFIG_SYS_PCIE1_MEM_BUS        0x80000000
 152 #define CONFIG_SYS_PCIE1_MEM_PHYS       0xc00000000ull
 153 #else
 154 #define CONFIG_SYS_PCIE1_MEM_BUS        0x80000000
 155 #define CONFIG_SYS_PCIE1_MEM_PHYS       0x80000000
 156 #endif
 157 #define CONFIG_SYS_PCIE1_MEM_SIZE       0x20000000      /* 512M */
 158 #define CONFIG_SYS_PCIE1_IO_VIRT        0xffc00000
 159 #define CONFIG_SYS_PCIE1_IO_BUS         0x00000000
 160 #define CONFIG_SYS_PCIE1_IO_SIZE        0x00010000      /* 64k */
 161 #ifdef CONFIG_PHYS_64BIT
 162 #define CONFIG_SYS_PCIE1_IO_PHYS        0xfffc00000ull
 163 #else
 164 #define CONFIG_SYS_PCIE1_IO_PHYS        0xffc00000
 165 #endif
 166
 167 /* controller 2, Slot 2, tgtid 2, Base address 9000 */
 168 #if defined(CONFIG_TARGET_P1010RDB_PA)
 169 #define CONFIG_SYS_PCIE2_NAME           "PCIe Slot"
 170 #elif defined(CONFIG_TARGET_P1010RDB_PB)
 171 #define CONFIG_SYS_PCIE2_NAME           "mini PCIe Slot"
 172 #endif
 173 #define CONFIG_SYS_PCIE2_MEM_VIRT       0xa0000000
 174 #ifdef CONFIG_PHYS_64BIT
 175 #define CONFIG_SYS_PCIE2_MEM_BUS        0xc0000000
 176 #define CONFIG_SYS_PCIE2_MEM_PHYS       0xc20000000ull
 177 #else
 178 #define CONFIG_SYS_PCIE2_MEM_BUS        0xa0000000
 179 #define CONFIG_SYS_PCIE2_MEM_PHYS       0xa0000000
 180 #endif
 181 #define CONFIG_SYS_PCIE2_MEM_SIZE       0x20000000      /* 512M */
 182 #define CONFIG_SYS_PCIE2_IO_VIRT        0xffc10000
 183 #define CONFIG_SYS_PCIE2_IO_BUS         0x00000000
 184 #define CONFIG_SYS_PCIE2_IO_SIZE        0x00010000      /* 64k */
 185 #ifdef CONFIG_PHYS_64BIT
 186 #define CONFIG_SYS_PCIE2_IO_PHYS        0xfffc10000ull
 187 #else
 188 #define CONFIG_SYS_PCIE2_IO_PHYS        0xffc10000
 189 #endif
 190
 191 #define CONFIG_PCI_SCAN_SHOW            /* show pci devices on startup */
 192 #endif
 193
 194 #define CONFIG_TSEC_ENET
 195 #define CONFIG_ENV_OVERWRITE
 196
 197 #define CONFIG_DDR_CLK_FREQ     66666666 /* DDRCLK on P1010 RDB */
 198 #define CONFIG_SYS_CLK_FREQ     66666666 /* SYSCLK for P1010 RDB */
 199
 200 #define CONFIG_MISC_INIT_R
 201 #define CONFIG_HWCONFIG
 202 /*
 203  * These can be toggled for performance analysis, otherwise use default.
 204  */
 205 #define CONFIG_L2_CACHE                 /* toggle L2 cache */
 206 #define CONFIG_BTB                      /* toggle branch predition */
 207
 208
 209 #define CONFIG_ENABLE_36BIT_PHYS
 210
 211 #ifdef CONFIG_PHYS_64BIT
 212 #define CONFIG_ADDR_MAP                 1
 213 #define CONFIG_SYS_NUM_ADDR_MAP         16      /* number of TLB1 entries */
 214 #endif
 215
 216 #define CONFIG_SYS_MEMTEST_START        0x00200000      /* memtest works on */
 217 #define CONFIG_SYS_MEMTEST_END          0x1fffffff
 218 #define CONFIG_PANIC_HANG               /* do not reset board on panic */
 219
 220 /* DDR Setup */
 221 #define CONFIG_SYS_DDR_RAW_TIMING
 222 #define CONFIG_DDR_SPD
 223 #define CONFIG_SYS_SPD_BUS_NUM          1
 224 #define SPD_EEPROM_ADDRESS              0x52
 225
 226 #define CONFIG_MEM_INIT_VALUE           0xDeadBeef
 227
 228 #ifndef __ASSEMBLY__
 229 extern unsigned long get_sdram_size(void);
 230 #endif
 231 #define CONFIG_SYS_SDRAM_SIZE           get_sdram_size() /* DDR size */
 232 #define CONFIG_SYS_DDR_SDRAM_BASE       0x00000000
 233 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_SDRAM_BASE
 234
 235 #define CONFIG_DIMM_SLOTS_PER_CTLR      1
 236 #define CONFIG_CHIP_SELECTS_PER_CTRL    1
 237
 238 /* DDR3 Controller Settings */
 239 #define CONFIG_SYS_DDR_CS0_BNDS         0x0000003f
 240 #define CONFIG_SYS_DDR_CS0_CONFIG       0x80014302
 241 #define CONFIG_SYS_DDR_CS0_CONFIG_2     0x00000000
 242 #define CONFIG_SYS_DDR_DATA_INIT        0xdeadbeef
 243 #define CONFIG_SYS_DDR_INIT_ADDR        0x00000000
 244 #define CONFIG_SYS_DDR_INIT_EXT_ADDR    0x00000000
 245 #define CONFIG_SYS_DDR_MODE_CONTROL     0x00000000
 246 #define CONFIG_SYS_DDR_ZQ_CONTROL       0x89080600
 247 #define CONFIG_SYS_DDR_SR_CNTR          0x00000000
 248 #define CONFIG_SYS_DDR_RCW_1            0x00000000
 249 #define CONFIG_SYS_DDR_RCW_2            0x00000000
 250 #define CONFIG_SYS_DDR_CONTROL          0xc70c0008      /* Type = DDR3  */
 251 #define CONFIG_SYS_DDR_CONTROL_2        0x24401000
 252 #define CONFIG_SYS_DDR_TIMING_4         0x00000001
 253 #define CONFIG_SYS_DDR_TIMING_5         0x03402400
 254
 255 #define CONFIG_SYS_DDR_TIMING_3_800     0x00030000
 256 #define CONFIG_SYS_DDR_TIMING_0_800     0x00110104
 257 #define CONFIG_SYS_DDR_TIMING_1_800     0x6f6b8644
 258 #define CONFIG_SYS_DDR_TIMING_2_800     0x0FA888CF
 259 #define CONFIG_SYS_DDR_CLK_CTRL_800     0x03000000
 260 #define CONFIG_SYS_DDR_MODE_1_800       0x00441420
 261 #define CONFIG_SYS_DDR_MODE_2_800       0x00000000
 262 #define CONFIG_SYS_DDR_INTERVAL_800     0x0C300100
 263 #define CONFIG_SYS_DDR_WRLVL_CONTROL_800 0x8675f608
 264
 265 /* settings for DDR3 at 667MT/s */
 266 #define CONFIG_SYS_DDR_TIMING_3_667             0x00010000
 267 #define CONFIG_SYS_DDR_TIMING_0_667             0x00110004
 268 #define CONFIG_SYS_DDR_TIMING_1_667             0x5d59e544
 269 #define CONFIG_SYS_DDR_TIMING_2_667             0x0FA890CD
 270 #define CONFIG_SYS_DDR_CLK_CTRL_667             0x03000000
 271 #define CONFIG_SYS_DDR_MODE_1_667               0x00441210
 272 #define CONFIG_SYS_DDR_MODE_2_667               0x00000000
 273 #define CONFIG_SYS_DDR_INTERVAL_667             0x0a280000
 274 #define CONFIG_SYS_DDR_WRLVL_CONTROL_667        0x8675F608
 275
 276 #define CONFIG_SYS_CCSRBAR                      0xffe00000
 277 #define CONFIG_SYS_CCSRBAR_PHYS_LOW             CONFIG_SYS_CCSRBAR
 278
 279 /* Don't relocate CCSRBAR while in NAND_SPL */
 280 #ifdef CONFIG_SPL_BUILD
 281 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
 282 #endif
 283
 284 /*
 285  * Memory map
 286  *
 287  * 0x0000_0000  0x3fff_ffff     DDR                     1G cacheable
 288  * 0x8000_0000  0xbfff_ffff     PCI Express Mem         1.5G non-cacheable
 289  * 0xffc0_0000  0xffc3_ffff     PCI IO range            256k non-cacheable
 290  *
 291  * Localbus non-cacheable
 292  * 0xff80_0000  0xff8f_ffff     NAND Flash              1M non-cacheable
 293  * 0xffb0_0000  0xffbf_ffff     Board CPLD              1M non-cacheable
 294  * 0xffd0_0000  0xffd0_3fff     L1 for stack            16K Cacheable TLB0
 295  * 0xffe0_0000  0xffef_ffff     CCSR                    1M non-cacheable
 296  */
 297
 298 /*
 299  * IFC Definitions
 300  */
 301 /* NOR Flash on IFC */
 302
 303 #define CONFIG_SYS_FLASH_BASE           0xee000000
 304 #define CONFIG_SYS_MAX_FLASH_SECT       256     /* 32M */
 305
 306 #ifdef CONFIG_PHYS_64BIT
 307 #define CONFIG_SYS_FLASH_BASE_PHYS      (0xf00000000ull | CONFIG_SYS_FLASH_BASE)
 308 #else
 309 #define CONFIG_SYS_FLASH_BASE_PHYS      CONFIG_SYS_FLASH_BASE
 310 #endif
 311
 312 #define CONFIG_SYS_NOR_CSPR     (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
 313                                 CSPR_PORT_SIZE_16 | \
 314                                 CSPR_MSEL_NOR | \
 315                                 CSPR_V)
 316 #define CONFIG_SYS_NOR_AMASK    IFC_AMASK(32*1024*1024)
 317 #define CONFIG_SYS_NOR_CSOR     CSOR_NOR_ADM_SHIFT(7)
 318 /* NOR Flash Timing Params */
 319 #define CONFIG_SYS_NOR_FTIM0    FTIM0_NOR_TACSE(0x4) | \
 320                                 FTIM0_NOR_TEADC(0x5) | \
 321                                 FTIM0_NOR_TEAHC(0x5)
 322 #define CONFIG_SYS_NOR_FTIM1    FTIM1_NOR_TACO(0x1e) | \
 323                                 FTIM1_NOR_TRAD_NOR(0x0f)
 324 #define CONFIG_SYS_NOR_FTIM2    FTIM2_NOR_TCS(0x4) | \
 325                                 FTIM2_NOR_TCH(0x4) | \
 326                                 FTIM2_NOR_TWP(0x1c)
 327 #define CONFIG_SYS_NOR_FTIM3    0x0
 328
 329 #define CONFIG_SYS_FLASH_BANKS_LIST     {CONFIG_SYS_FLASH_BASE_PHYS}
 330 #define CONFIG_SYS_FLASH_QUIET_TEST
 331 #define CONFIG_FLASH_SHOW_PROGRESS      45      /* count down from 45/5: 9..1 */
 332 #define CONFIG_SYS_MAX_FLASH_BANKS      1       /* number of banks */
 333
 334 #undef CONFIG_SYS_FLASH_CHECKSUM
 335 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000   /* Flash Erase Timeout (ms) */
 336 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Flash Write Timeout (ms) */
 337
 338 /* CFI for NOR Flash */
 339 #define CONFIG_FLASH_CFI_DRIVER
 340 #define CONFIG_SYS_FLASH_CFI
 341 #define CONFIG_SYS_FLASH_EMPTY_INFO
 342 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
 343
 344 /* NAND Flash on IFC */
 345 #define CONFIG_SYS_NAND_BASE            0xff800000
 346 #ifdef CONFIG_PHYS_64BIT
 347 #define CONFIG_SYS_NAND_BASE_PHYS       0xfff800000ull
 348 #else
 349 #define CONFIG_SYS_NAND_BASE_PHYS       CONFIG_SYS_NAND_BASE
 350 #endif
 351
 352 #define CONFIG_MTD_DEVICE
 353 #define CONFIG_MTD_PARTITION
 354
 355 #define CONFIG_SYS_NAND_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
 356                                 | CSPR_PORT_SIZE_8      \
 357                                 | CSPR_MSEL_NAND        \
 358                                 | CSPR_V)
 359 #define CONFIG_SYS_NAND_AMASK   IFC_AMASK(64*1024)
 360
 361 #if defined(CONFIG_TARGET_P1010RDB_PA)
 362 #define CONFIG_SYS_NAND_CSOR    (CSOR_NAND_ECC_ENC_EN   /* ECC on encode */ \
 363                                 | CSOR_NAND_ECC_DEC_EN  /* ECC on decode */ \
 364                                 | CSOR_NAND_ECC_MODE_4  /* 4-bit ECC */ \
 365                                 | CSOR_NAND_RAL_2       /* RAL = 2 Bytes */ \
 366                                 | CSOR_NAND_PGS_512     /* Page Size = 512b */ \
 367                                 | CSOR_NAND_SPRZ_16     /* Spare size = 16 */ \
 368                                 | CSOR_NAND_PB(32))     /* 32 Pages Per Block */
 369 #define CONFIG_SYS_NAND_BLOCK_SIZE      (16 * 1024)
 370
 371 #elif defined(CONFIG_TARGET_P1010RDB_PB)
 372 #define CONFIG_SYS_NAND_ONFI_DETECTION
 373 #define CONFIG_SYS_NAND_CSOR   (CSOR_NAND_ECC_ENC_EN   /* ECC on encode */ \
 374                                 | CSOR_NAND_ECC_DEC_EN  /* ECC on decode */ \
 375                                 | CSOR_NAND_ECC_MODE_4  /* 4-bit ECC */ \
 376                                 | CSOR_NAND_RAL_3       /* RAL = 3Byes */ \
 377                                 | CSOR_NAND_PGS_4K      /* Page Size = 4K */ \
 378                                 | CSOR_NAND_SPRZ_224    /* Spare size = 224 */ \
 379                                 | CSOR_NAND_PB(128))  /*Pages Per Block = 128 */
 380 #define CONFIG_SYS_NAND_BLOCK_SIZE     (512 * 1024)
 381 #endif
 382
 383 #define CONFIG_SYS_NAND_BASE_LIST       { CONFIG_SYS_NAND_BASE }
 384 #define CONFIG_SYS_MAX_NAND_DEVICE      1
 385
 386 #if defined(CONFIG_TARGET_P1010RDB_PA)
 387 /* NAND Flash Timing Params */
 388 #define CONFIG_SYS_NAND_FTIM0           FTIM0_NAND_TCCST(0x01) | \
 389                                         FTIM0_NAND_TWP(0x0C)   | \
 390                                         FTIM0_NAND_TWCHT(0x04) | \
 391                                         FTIM0_NAND_TWH(0x05)
 392 #define CONFIG_SYS_NAND_FTIM1           FTIM1_NAND_TADLE(0x1d) | \
 393                                         FTIM1_NAND_TWBE(0x1d)  | \
 394                                         FTIM1_NAND_TRR(0x07)   | \
 395                                         FTIM1_NAND_TRP(0x0c)
 396 #define CONFIG_SYS_NAND_FTIM2           FTIM2_NAND_TRAD(0x0c) | \
 397                                         FTIM2_NAND_TREH(0x05) | \
 398                                         FTIM2_NAND_TWHRE(0x0f)
 399 #define CONFIG_SYS_NAND_FTIM3           FTIM3_NAND_TWW(0x04)
 400
 401 #elif defined(CONFIG_TARGET_P1010RDB_PB)
 402 /* support MT29F16G08ABABAWP 4k-pagesize 2G-bytes NAND */
 403 /* ONFI NAND Flash mode0 Timing Params */
 404 #define CONFIG_SYS_NAND_FTIM0  (FTIM0_NAND_TCCST(0x07)| \
 405                                         FTIM0_NAND_TWP(0x18)   | \
 406                                         FTIM0_NAND_TWCHT(0x07) | \
 407                                         FTIM0_NAND_TWH(0x0a))
 408 #define CONFIG_SYS_NAND_FTIM1  (FTIM1_NAND_TADLE(0x32)| \
 409                                         FTIM1_NAND_TWBE(0x39)  | \
 410                                         FTIM1_NAND_TRR(0x0e)   | \
 411                                         FTIM1_NAND_TRP(0x18))
 412 #define CONFIG_SYS_NAND_FTIM2  (FTIM2_NAND_TRAD(0x0f) | \
 413                                         FTIM2_NAND_TREH(0x0a)  | \
 414                                         FTIM2_NAND_TWHRE(0x1e))
 415 #define CONFIG_SYS_NAND_FTIM3   0x0
 416 #endif
 417
 418 #define CONFIG_SYS_NAND_DDR_LAW         11
 419
 420 /* Set up IFC registers for boot location NOR/NAND */
 421 #if defined(CONFIG_NAND) || defined(CONFIG_NAND_SECBOOT)
 422 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NAND_CSPR
 423 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NAND_AMASK
 424 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NAND_CSOR
 425 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NAND_FTIM0
 426 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NAND_FTIM1
 427 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NAND_FTIM2
 428 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NAND_FTIM3
 429 #define CONFIG_SYS_CSPR1                CONFIG_SYS_NOR_CSPR
 430 #define CONFIG_SYS_AMASK1               CONFIG_SYS_NOR_AMASK
 431 #define CONFIG_SYS_CSOR1                CONFIG_SYS_NOR_CSOR
 432 #define CONFIG_SYS_CS1_FTIM0            CONFIG_SYS_NOR_FTIM0
 433 #define CONFIG_SYS_CS1_FTIM1            CONFIG_SYS_NOR_FTIM1
 434 #define CONFIG_SYS_CS1_FTIM2            CONFIG_SYS_NOR_FTIM2
 435 #define CONFIG_SYS_CS1_FTIM3            CONFIG_SYS_NOR_FTIM3
 436 #else
 437 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NOR_CSPR
 438 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NOR_AMASK
 439 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NOR_CSOR
 440 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NOR_FTIM0
 441 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NOR_FTIM1
 442 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NOR_FTIM2
 443 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NOR_FTIM3
 444 #define CONFIG_SYS_CSPR1                CONFIG_SYS_NAND_CSPR
 445 #define CONFIG_SYS_AMASK1               CONFIG_SYS_NAND_AMASK
 446 #define CONFIG_SYS_CSOR1                CONFIG_SYS_NAND_CSOR
 447 #define CONFIG_SYS_CS1_FTIM0            CONFIG_SYS_NAND_FTIM0
 448 #define CONFIG_SYS_CS1_FTIM1            CONFIG_SYS_NAND_FTIM1
 449 #define CONFIG_SYS_CS1_FTIM2            CONFIG_SYS_NAND_FTIM2
 450 #define CONFIG_SYS_CS1_FTIM3            CONFIG_SYS_NAND_FTIM3
 451 #endif
 452
 453 /* CPLD on IFC */
 454 #define CONFIG_SYS_CPLD_BASE            0xffb00000
 455
 456 #ifdef CONFIG_PHYS_64BIT
 457 #define CONFIG_SYS_CPLD_BASE_PHYS       0xfffb00000ull
 458 #else
 459 #define CONFIG_SYS_CPLD_BASE_PHYS       CONFIG_SYS_CPLD_BASE
 460 #endif
 461
 462 #define CONFIG_SYS_CSPR3        (CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE_PHYS) \
 463                                 | CSPR_PORT_SIZE_8 \
 464                                 | CSPR_MSEL_GPCM \
 465                                 | CSPR_V)
 466 #define CONFIG_SYS_AMASK3               IFC_AMASK(64*1024)
 467 #define CONFIG_SYS_CSOR3                0x0
 468 /* CPLD Timing parameters for IFC CS3 */
 469 #define CONFIG_SYS_CS3_FTIM0            (FTIM0_GPCM_TACSE(0x0e) | \
 470                                         FTIM0_GPCM_TEADC(0x0e) | \
 471                                         FTIM0_GPCM_TEAHC(0x0e))
 472 #define CONFIG_SYS_CS3_FTIM1            (FTIM1_GPCM_TACO(0x0e) | \
 473                                         FTIM1_GPCM_TRAD(0x1f))
 474 #define CONFIG_SYS_CS3_FTIM2            (FTIM2_GPCM_TCS(0x0e) | \
 475                                         FTIM2_GPCM_TCH(0x8) | \
 476                                         FTIM2_GPCM_TWP(0x1f))
 477 #define CONFIG_SYS_CS3_FTIM3            0x0
 478
 479 #if defined(CONFIG_RAMBOOT_SDCARD) || defined(CONFIG_RAMBOOT_SPIFLASH) || \
 480         defined(CONFIG_RAMBOOT_NAND)
 481 #define CONFIG_SYS_RAMBOOT
 482 #define CONFIG_SYS_EXTRA_ENV_RELOC
 483 #else
 484 #undef CONFIG_SYS_RAMBOOT
 485 #endif
 486
 487 #ifdef CONFIG_SYS_FSL_ERRATUM_IFC_A003399
 488 #if !defined(CONFIG_SPL) && !defined(CONFIG_SYS_RAMBOOT)
 489 #define CONFIG_A003399_NOR_WORKAROUND
 490 #endif
 491 #endif
 492
 493 #define CONFIG_BOARD_EARLY_INIT_R
 494
 495 #define CONFIG_SYS_INIT_RAM_LOCK
 496 #define CONFIG_SYS_INIT_RAM_ADDR        0xffd00000 /* stack in RAM */
 497 #define CONFIG_SYS_INIT_RAM_SIZE        0x00004000 /* End of used area in RAM */
 498
 499 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE \
 500                                                 - GENERATED_GBL_DATA_SIZE)
 501 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 502
 503 #define CONFIG_SYS_MONITOR_LEN          (768 * 1024)
 504 #define CONFIG_SYS_MALLOC_LEN           (1024 * 1024)   /* Reserved for malloc*/
 505
 506 /*
 507  * Config the L2 Cache as L2 SRAM
 508  */
 509 #if defined(CONFIG_SPL_BUILD)
 510 #if defined(CONFIG_SDCARD) || defined(CONFIG_SPIFLASH)
 511 #define CONFIG_SYS_INIT_L2_ADDR         0xD0000000
 512 #define CONFIG_SYS_INIT_L2_ADDR_PHYS    CONFIG_SYS_INIT_L2_ADDR
 513 #define CONFIG_SYS_L2_SIZE              (256 << 10)
 514 #define CONFIG_SYS_INIT_L2_END  (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
 515 #define CONFIG_SPL_RELOC_TEXT_BASE      0xD0001000
 516 #define CONFIG_SPL_RELOC_STACK          (CONFIG_SYS_INIT_L2_ADDR + 112 * 1024)
 517 #define CONFIG_SPL_RELOC_STACK_SIZE     (16 << 10)
 518 #define CONFIG_SPL_RELOC_MALLOC_ADDR    (CONFIG_SYS_INIT_L2_ADDR + 128 * 1024)
 519 #define CONFIG_SPL_RELOC_MALLOC_SIZE    (128 << 10)
 520 #define CONFIG_SPL_GD_ADDR              (CONFIG_SYS_INIT_L2_ADDR + 96 * 1024)
 521 #elif defined(CONFIG_NAND)
 522 #ifdef CONFIG_TPL_BUILD
 523 #define CONFIG_SYS_INIT_L2_ADDR         0xD0000000
 524 #define CONFIG_SYS_INIT_L2_ADDR_PHYS    CONFIG_SYS_INIT_L2_ADDR
 525 #define CONFIG_SYS_L2_SIZE              (256 << 10)
 526 #define CONFIG_SYS_INIT_L2_END  (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
 527 #define CONFIG_SPL_RELOC_TEXT_BASE      0xD0001000
 528 #define CONFIG_SPL_RELOC_STACK          (CONFIG_SYS_INIT_L2_ADDR + 192 * 1024)
 529 #define CONFIG_SPL_RELOC_MALLOC_ADDR    (CONFIG_SYS_INIT_L2_ADDR + 208 * 1024)
 530 #define CONFIG_SPL_RELOC_MALLOC_SIZE    (48 << 10)
 531 #define CONFIG_SPL_GD_ADDR              (CONFIG_SYS_INIT_L2_ADDR + 176 * 1024)
 532 #else
 533 #define CONFIG_SYS_INIT_L2_ADDR         0xD0000000
 534 #define CONFIG_SYS_INIT_L2_ADDR_PHYS    CONFIG_SYS_INIT_L2_ADDR
 535 #define CONFIG_SYS_L2_SIZE              (256 << 10)
 536 #define CONFIG_SYS_INIT_L2_END  (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
 537 #define CONFIG_SPL_RELOC_TEXT_BASE      (CONFIG_SYS_INIT_L2_END - 0x3000)
 538 #define CONFIG_SPL_RELOC_STACK          ((CONFIG_SYS_INIT_L2_END - 1) & ~0xF)
 539 #endif
 540 #endif
 541 #endif
 542
 543 /* Serial Port */
 544 #define CONFIG_CONS_INDEX       1
 545 #undef  CONFIG_SERIAL_SOFTWARE_FIFO
 546 #define CONFIG_SYS_NS16550_SERIAL
 547 #define CONFIG_SYS_NS16550_REG_SIZE     1
 548 #define CONFIG_SYS_NS16550_CLK          get_bus_freq(0)
 549 #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_INIT_MINIMAL)
 550 #define CONFIG_NS16550_MIN_FUNCTIONS
 551 #endif
 552
 553 #define CONFIG_SYS_BAUDRATE_TABLE       \
 554         {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
 555
 556 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
 557 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
 558
 559 /* I2C */
 560 #define CONFIG_SYS_I2C
 561 #define CONFIG_SYS_I2C_FSL
 562 #define CONFIG_SYS_FSL_I2C_SPEED        400000
 563 #define CONFIG_SYS_FSL_I2C_SLAVE        0x7F
 564 #define CONFIG_SYS_FSL_I2C_OFFSET       0x3000
 565 #define CONFIG_SYS_FSL_I2C2_SPEED       400000
 566 #define CONFIG_SYS_FSL_I2C2_SLAVE       0x7F
 567 #define CONFIG_SYS_FSL_I2C2_OFFSET      0x3100
 568 #define I2C_PCA9557_ADDR1               0x18
 569 #define I2C_PCA9557_ADDR2               0x19
 570 #define I2C_PCA9557_BUS_NUM             0
 571
 572 /* I2C EEPROM */
 573 #if defined(CONFIG_TARGET_P1010RDB_PB)
 574 #define CONFIG_ID_EEPROM
 575 #ifdef CONFIG_ID_EEPROM
 576 #define CONFIG_SYS_I2C_EEPROM_NXID
 577 #endif
 578 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN  1
 579 #define CONFIG_SYS_I2C_EEPROM_ADDR      0x57
 580 #define CONFIG_SYS_EEPROM_BUS_NUM       0
 581 #define MAX_NUM_PORTS                   9 /* for 128Bytes EEPROM */
 582 #endif
 583 /* enable read and write access to EEPROM */
 584 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
 585 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
 586 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
 587
 588 /* RTC */
 589 #define CONFIG_RTC_PT7C4338
 590 #define CONFIG_SYS_I2C_RTC_ADDR 0x68
 591
 592 /*
 593  * SPI interface will not be available in case of NAND boot SPI CS0 will be
 594  * used for SLIC
 595  */
 596 #if !defined(CONFIG_NAND) || !defined(CONFIG_NAND_SECBOOT)
 597 /* eSPI - Enhanced SPI */
 598 #define CONFIG_SF_DEFAULT_SPEED         10000000
 599 #define CONFIG_SF_DEFAULT_MODE          SPI_MODE_0
 600 #endif
 601
 602 #if defined(CONFIG_TSEC_ENET)
 603 #define CONFIG_MII                      /* MII PHY management */
 604 #define CONFIG_MII_DEFAULT_TSEC 1       /* Allow unregistered phys */
 605 #define CONFIG_TSEC1    1
 606 #define CONFIG_TSEC1_NAME       "eTSEC1"
 607 #define CONFIG_TSEC2    1
 608 #define CONFIG_TSEC2_NAME       "eTSEC2"
 609 #define CONFIG_TSEC3    1
 610 #define CONFIG_TSEC3_NAME       "eTSEC3"
 611
 612 #define TSEC1_PHY_ADDR          1
 613 #define TSEC2_PHY_ADDR          0
 614 #define TSEC3_PHY_ADDR          2
 615
 616 #define TSEC1_FLAGS             (TSEC_GIGABIT | TSEC_REDUCED)
 617 #define TSEC2_FLAGS             (TSEC_GIGABIT | TSEC_REDUCED)
 618 #define TSEC3_FLAGS             (TSEC_GIGABIT | TSEC_REDUCED)
 619
 620 #define TSEC1_PHYIDX            0
 621 #define TSEC2_PHYIDX            0
 622 #define TSEC3_PHYIDX            0
 623
 624 #define CONFIG_ETHPRIME         "eTSEC1"
 625
 626 /* TBI PHY configuration for SGMII mode */
 627 #define CONFIG_TSEC_TBICR_SETTINGS ( \
 628                 TBICR_PHY_RESET \
 629                 | TBICR_ANEG_ENABLE \
 630                 | TBICR_FULL_DUPLEX \
 631                 | TBICR_SPEED1_SET \
 632                 )
 633
 634 #endif  /* CONFIG_TSEC_ENET */
 635
 636 /* SATA */
 637 #define CONFIG_FSL_SATA_V2
 638
 639 #ifdef CONFIG_FSL_SATA
 640 #define CONFIG_SYS_SATA_MAX_DEVICE      2
 641 #define CONFIG_SATA1
 642 #define CONFIG_SYS_SATA1                CONFIG_SYS_MPC85xx_SATA1_ADDR
 643 #define CONFIG_SYS_SATA1_FLAGS          FLAGS_DMA
 644 #define CONFIG_SATA2
 645 #define CONFIG_SYS_SATA2                CONFIG_SYS_MPC85xx_SATA2_ADDR
 646 #define CONFIG_SYS_SATA2_FLAGS          FLAGS_DMA
 647
 648 #define CONFIG_LBA48
 649 #endif /* #ifdef CONFIG_FSL_SATA  */
 650
 651 #ifdef CONFIG_MMC
 652 #define CONFIG_FSL_ESDHC
 653 #define CONFIG_SYS_FSL_ESDHC_ADDR       CONFIG_SYS_MPC85xx_ESDHC_ADDR
 654 #endif
 655
 656 #define CONFIG_HAS_FSL_DR_USB
 657
 658 #if defined(CONFIG_HAS_FSL_DR_USB)
 659 #ifdef CONFIG_USB_EHCI_HCD
 660 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
 661 #define CONFIG_USB_EHCI_FSL
 662 #endif
 663 #endif
 664
 665 /*
 666  * Environment
 667  */
 668 #if defined(CONFIG_SDCARD)
 669 #define CONFIG_FSL_FIXED_MMC_LOCATION
 670 #define CONFIG_SYS_MMC_ENV_DEV          0
 671 #define CONFIG_ENV_SIZE                 0x2000
 672 #elif defined(CONFIG_SPIFLASH)
 673 #define CONFIG_ENV_SPI_BUS      0
 674 #define CONFIG_ENV_SPI_CS       0
 675 #define CONFIG_ENV_SPI_MAX_HZ   10000000
 676 #define CONFIG_ENV_SPI_MODE     0
 677 #define CONFIG_ENV_OFFSET       0x100000        /* 1MB */
 678 #define CONFIG_ENV_SECT_SIZE    0x10000
 679 #define CONFIG_ENV_SIZE         0x2000
 680 #elif defined(CONFIG_NAND)
 681 #ifdef CONFIG_TPL_BUILD
 682 #define CONFIG_ENV_SIZE         0x2000
 683 #define CONFIG_ENV_ADDR         (CONFIG_SYS_INIT_L2_ADDR + (160 << 10))
 684 #else
 685 #if defined(CONFIG_TARGET_P1010RDB_PA)
 686 #define CONFIG_ENV_SIZE         CONFIG_SYS_NAND_BLOCK_SIZE
 687 #define CONFIG_ENV_RANGE        (3 * CONFIG_ENV_SIZE) /* 3*16=48K for env */
 688 #elif defined(CONFIG_TARGET_P1010RDB_PB)
 689 #define CONFIG_ENV_SIZE         (16 * 1024)
 690 #define CONFIG_ENV_RANGE        (32 * CONFIG_ENV_SIZE) /* new block size 512K */
 691 #endif
 692 #endif
 693 #define CONFIG_ENV_OFFSET       (1024 * 1024)
 694 #elif defined(CONFIG_SYS_RAMBOOT)
 695 #define CONFIG_ENV_ADDR                 (CONFIG_SYS_MONITOR_BASE - 0x1000)
 696 #define CONFIG_ENV_SIZE                 0x2000
 697 #else
 698 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
 699 #define CONFIG_ENV_SIZE         0x2000
 700 #define CONFIG_ENV_SECT_SIZE    0x20000 /* 128K (one sector) */
 701 #endif
 702
 703 #define CONFIG_LOADS_ECHO               /* echo on for serial download */
 704 #define CONFIG_SYS_LOADS_BAUD_CHANGE    /* allow baudrate change */
 705
 706 #undef CONFIG_WATCHDOG                  /* watchdog disabled */
 707
 708 #if defined(CONFIG_MMC) || defined(CONFIG_USB_EHCI_HCD) \
 709                  || defined(CONFIG_FSL_SATA)
 710 #endif
 711
 712 /*
 713  * Miscellaneous configurable options
 714  */
 715 #define CONFIG_SYS_LONGHELP                     /* undef to save memory */
 716 #define CONFIG_CMDLINE_EDITING                  /* Command-line editing */
 717 #define CONFIG_AUTO_COMPLETE                    /* add autocompletion support */
 718 #define CONFIG_SYS_LOAD_ADDR    0x2000000       /* default load address */
 719
 720 /*
 721  * For booting Linux, the board info and command line data
 722  * have to be in the first 64 MB of memory, since this is
 723  * the maximum mapped by the Linux kernel during initialization.
 724  */
 725 #define CONFIG_SYS_BOOTMAPSZ    (64 << 20) /* Initial Memory map for Linux */
 726 #define CONFIG_SYS_BOOTM_LEN    (64 << 20) /* Increase max gunzip size */
 727
 728 #if defined(CONFIG_CMD_KGDB)
 729 #define CONFIG_KGDB_BAUDRATE    230400  /* speed to run kgdb serial port */
 730 #endif
 731
 732 /*
 733  * Environment Configuration
 734  */
 735
 736 #if defined(CONFIG_TSEC_ENET)
 737 #define CONFIG_HAS_ETH0
 738 #define CONFIG_HAS_ETH1
 739 #define CONFIG_HAS_ETH2
 740 #endif
 741
 742 #define CONFIG_ROOTPATH         "/opt/nfsroot"
 743 #define CONFIG_BOOTFILE         "uImage"
 744 #define CONFIG_UBOOTPATH        u-boot.bin/* U-Boot image on TFTP server */
 745
 746 /* default location for tftp and bootm */
 747 #define CONFIG_LOADADDR         1000000
 748
 749 #define CONFIG_EXTRA_ENV_SETTINGS                               \
 750         "hwconfig=" __stringify(CONFIG_DEF_HWCONFIG)  "\0"      \
 751         "netdev=eth0\0"                                         \
 752         "uboot=" __stringify(CONFIG_UBOOTPATH) "\0"             \
 753         "loadaddr=1000000\0"                    \
 754         "consoledev=ttyS0\0"                            \
 755         "ramdiskaddr=2000000\0"                 \
 756         "ramdiskfile=rootfs.ext2.gz.uboot\0"            \
 757         "fdtaddr=1e00000\0"                             \
 758         "fdtfile=p1010rdb.dtb\0"                \
 759         "bdev=sda1\0"   \
 760         "hwconfig=usb1:dr_mode=host,phy_type=utmi\0"    \
 761         "othbootargs=ramdisk_size=600000\0" \
 762         "usbfatboot=setenv bootargs root=/dev/ram rw "  \
 763         "console=$consoledev,$baudrate $othbootargs; "  \
 764         "usb start;"                    \
 765         "fatload usb 0:2 $loadaddr $bootfile;"          \
 766         "fatload usb 0:2 $fdtaddr $fdtfile;"    \
 767         "fatload usb 0:2 $ramdiskaddr $ramdiskfile;"    \
 768         "bootm $loadaddr $ramdiskaddr $fdtaddr\0"               \
 769         "usbext2boot=setenv bootargs root=/dev/ram rw " \
 770         "console=$consoledev,$baudrate $othbootargs; "  \
 771         "usb start;"                    \
 772         "ext2load usb 0:4 $loadaddr $bootfile;"         \
 773         "ext2load usb 0:4 $fdtaddr $fdtfile;"   \
 774         "ext2load usb 0:4 $ramdiskaddr $ramdiskfile;"   \
 775         "bootm $loadaddr $ramdiskaddr $fdtaddr\0"       \
 776         CONFIG_BOOTMODE
 777
 778 #if defined(CONFIG_TARGET_P1010RDB_PA)
 779 #define CONFIG_BOOTMODE \
 780         "boot_bank0=i2c dev 0; i2c mw 18 1 f1; i2c mw 18 3 f0;" \
 781         "mw.b ffb00011 0; mw.b ffb00009 0; reset\0" \
 782         "boot_bank1=i2c dev 0; i2c mw 18 1 f1; i2c mw 18 3 f0;" \
 783         "mw.b ffb00011 0; mw.b ffb00009 1; reset\0" \
 784         "boot_nand=i2c dev 0; i2c mw 18 1 f9; i2c mw 18 3 f0;" \
 785         "mw.b ffb00011 0; mw.b ffb00017 1; reset\0"
 786
 787 #elif defined(CONFIG_TARGET_P1010RDB_PB)
 788 #define CONFIG_BOOTMODE \
 789         "boot_bank0=i2c dev 0; i2c mw 18 1 fe; i2c mw 18 3 0;" \
 790         "i2c mw 19 1 2; i2c mw 19 3 e1; reset\0" \
 791         "boot_bank1=i2c dev 0; i2c mw 18 1 fe; i2c mw 18 3 0;" \
 792         "i2c mw 19 1 12; i2c mw 19 3 e1; reset\0" \
 793         "boot_nand=i2c dev 0; i2c mw 18 1 fc; i2c mw 18 3 0;" \
 794         "i2c mw 19 1 8; i2c mw 19 3 f7; reset\0" \
 795         "boot_spi=i2c dev 0; i2c mw 18 1 fa; i2c mw 18 3 0;" \
 796         "i2c mw 19 1 0; i2c mw 19 3 f7; reset\0" \
 797         "boot_sd=i2c dev 0; i2c mw 18 1 f8; i2c mw 18 3 0;" \
 798         "i2c mw 19 1 4; i2c mw 19 3 f3; reset\0"
 799 #endif
 800
 801 #define CONFIG_RAMBOOTCOMMAND           \
 802         "setenv bootargs root=/dev/ram rw "     \
 803         "console=$consoledev,$baudrate $othbootargs; "  \
 804         "tftp $ramdiskaddr $ramdiskfile;"       \
 805         "tftp $loadaddr $bootfile;"             \
 806         "tftp $fdtaddr $fdtfile;"               \
 807         "bootm $loadaddr $ramdiskaddr $fdtaddr"
 808
 809 #define CONFIG_BOOTCOMMAND CONFIG_RAMBOOTCOMMAND
 810
 811 #include <asm/fsl_secure_boot.h>
 812
 813 #endif  /* __CONFIG_H */