git.sur5r.net Git - u-boot/blob - include/configs/P1023RDB.h

   1 /*
   2  * Copyright 2013 Freescale Semiconductor, Inc.
   3  *
   4  * Authors:  Roy Zang <tie-fei.zang@freescale.com>
   5  *           Chunhe Lan <Chunhe.Lan@freescale.com>
   6  *
   7  * SPDX-License-Identifier:     GPL-2.0+
   8  */
   9
  10 #ifndef __CONFIG_H
  11 #define __CONFIG_H
  12
  13 #define CONFIG_DISPLAY_BOARDINFO
  14
  15 #ifndef CONFIG_SYS_TEXT_BASE
  16 #define CONFIG_SYS_TEXT_BASE    0xeff40000
  17 #endif
  18
  19 #ifndef CONFIG_SYS_MONITOR_BASE
  20 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE    /* start of monitor */
  21 #endif
  22
  23 #ifndef CONFIG_RESET_VECTOR_ADDRESS
  24 #define CONFIG_RESET_VECTOR_ADDRESS     0xeffffffc
  25 #endif
  26
  27 /* High Level Configuration Options */
  28 #define CONFIG_BOOKE            /* BOOKE */
  29 #define CONFIG_E500             /* BOOKE e500 family */
  30 #define CONFIG_P1023
  31 #define CONFIG_MP               /* support multiple processors */
  32
  33 #define CONFIG_FSL_ELBC         /* Has Enhanced localbus controller */
  34 #define CONFIG_PCI              /* Enable PCI/PCIE */
  35 #define CONFIG_PCI_INDIRECT_BRIDGE     /* indirect PCI bridge support */
  36 #define CONFIG_PCIE1            /* PCIE controler 1 (slot 1) */
  37 #define CONFIG_PCIE2            /* PCIE controler 2 (slot 2) */
  38 #define CONFIG_PCIE3            /* PCIE controler 3 (slot 3) */
  39 #define CONFIG_FSL_PCI_INIT     /* Use common FSL init code */
  40 #define CONFIG_FSL_PCIE_RESET   /* need PCIe reset errata */
  41 #define CONFIG_SYS_PCI_64BIT    /* enable 64-bit PCI resources */
  42 #define CONFIG_FSL_LAW          /* Use common FSL init code */
  43
  44 #ifndef __ASSEMBLY__
  45 extern unsigned long get_clock_freq(void);
  46 #endif
  47
  48 #define CONFIG_SYS_CLK_FREQ     66666666
  49 #define CONFIG_DDR_CLK_FREQ     CONFIG_SYS_CLK_FREQ
  50
  51 /*
  52  * These can be toggled for performance analysis, otherwise use default.
  53  */
  54 #define CONFIG_L2_CACHE                 /* toggle L2 cache */
  55 #define CONFIG_BTB                      /* toggle branch predition */
  56 #define CONFIG_HWCONFIG
  57
  58 #define CONFIG_ENABLE_36BIT_PHYS
  59
  60 #define CONFIG_SYS_MEMTEST_START        0x01000000      /* memtest works on */
  61 #define CONFIG_SYS_MEMTEST_END          0x02000000
  62
  63 #define CONFIG_PANIC_HANG       /* do not reset board on panic */
  64
  65 /* Implement conversion of addresses in the LBC */
  66 #define CONFIG_SYS_LBC_LBCR             0x00000000
  67 #define CONFIG_SYS_LBC_LCRR             LCRR_CLKDIV_8
  68
  69 /* DDR Setup */
  70 #define CONFIG_VERY_BIG_RAM
  71 #define CONFIG_SYS_DDR_SDRAM_BASE       0x00000000
  72 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_SDRAM_BASE
  73
  74 #define CONFIG_DIMM_SLOTS_PER_CTLR      1
  75 #define CONFIG_CHIP_SELECTS_PER_CTRL    1
  76
  77 #define CONFIG_DDR_SPD
  78 #define CONFIG_SYS_FSL_DDR3
  79 #define CONFIG_FSL_DDR_INTERACTIVE
  80 #define CONFIG_SYS_SDRAM_SIZE           512u    /* DDR is 512M */
  81 #define CONFIG_SYS_SPD_BUS_NUM          0
  82 #define SPD_EEPROM_ADDRESS              0x50
  83 #define CONFIG_SYS_DDR_RAW_TIMING
  84
  85 /*
  86  * Memory map
  87  *
  88  * 0x0000_0000  0x1fff_ffff     DDR                     512M cacheable
  89  * 0x8000_0000  0xbfff_ffff     PCI Express Mem         1G non-cacheable
  90  * 0xc000_0000  0xdfff_ffff     PCI                     512M non-cacheable
  91  * 0xe100_0000  0xe3ff_ffff     PCI IO range            4M non-cacheable
  92  * 0xff00_0000  0xff3f_ffff     DPAA_QBMAN              4M cacheable
  93  * 0xff60_0000  0xff7f_ffff     CCSR                    2M non-cacheable
  94  * 0xffd0_0000  0xffd0_3fff     L1 for stack            16K cacheable TLB0
  95  *
  96  * Localbus non-cacheable
  97  *
  98  * 0xec00_0000  0xefff_ffff     NOR flash               64M non-cacheable
  99  * 0xffa0_0000  0xffaf_ffff     NAND                    1M non-cacheable
 100  */
 101
 102 /*
 103  * Local Bus Definitions
 104  */
 105 #define CONFIG_SYS_FLASH_BASE           0xec000000 /* start of FLASH 64M */
 106 #define CONFIG_SYS_FLASH_BASE_PHYS      CONFIG_SYS_FLASH_BASE
 107
 108 #define CONFIG_FLASH_BR_PRELIM  (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) \
 109                                 | BR_PS_16 | BR_V)
 110 #define CONFIG_FLASH_OR_PRELIM  0xfc000ff7
 111
 112 #define CONFIG_FLASH_CFI_DRIVER
 113 #define CONFIG_SYS_FLASH_CFI
 114 #define CONFIG_SYS_FLASH_EMPTY_INFO
 115 #define CONFIG_SYS_MAX_FLASH_BANKS      1       /* number of banks */
 116 #define CONFIG_SYS_MAX_FLASH_SECT       512     /* sectors per device */
 117 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000   /* Flash Erase Timeout (ms) */
 118 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Flash Write Timeout (ms) */
 119
 120 #define CONFIG_BOARD_EARLY_INIT_F       /* call board_early_init_f function */
 121 #define CONFIG_BOARD_EARLY_INIT_R       /* call board_early_init_r function */
 122
 123 #define CONFIG_SYS_INIT_RAM_LOCK
 124 #define CONFIG_SYS_INIT_RAM_ADDR        0xffd00000      /* Initial L1 address */
 125 #define CONFIG_SYS_INIT_RAM_SIZE        0x00004000/* Size of used area in RAM */
 126 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - \
 127                                         GENERATED_GBL_DATA_SIZE)
 128 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 129
 130 #define CONFIG_SYS_MONITOR_LEN  (768 * 1024)      /* Reserve 512 kB for Mon */
 131 #define CONFIG_SYS_MALLOC_LEN   (6 * 1024 * 1024) /* Reserved for malloc */
 132
 133 #define CONFIG_SYS_NAND_BASE            0xffa00000
 134 #define CONFIG_SYS_NAND_BASE_PHYS       CONFIG_SYS_NAND_BASE
 135
 136 #define CONFIG_SYS_NAND_BASE_LIST       { CONFIG_SYS_NAND_BASE }
 137 #define CONFIG_SYS_MAX_NAND_DEVICE      1
 138 #define CONFIG_CMD_NAND
 139 #define CONFIG_NAND_FSL_ELBC
 140 #define CONFIG_SYS_NAND_BLOCK_SIZE      (128 * 1024)
 141
 142 /* NAND flash config */
 143 #define CONFIG_SYS_NAND_BR_PRELIM  (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
 144                                 | (2<<BR_DECC_SHIFT)    /* Use HW ECC */ \
 145                                 | BR_PS_8               /* Port Size = 8bit */ \
 146                                 | BR_MS_FCM             /* MSEL = FCM */ \
 147                                 | BR_V)                 /* valid */
 148 #define CONFIG_SYS_NAND_OR_PRELIM  (OR_AM_256KB         /* length 256K */ \
 149                                 | OR_FCM_PGS \
 150                                 | OR_FCM_CSCT \
 151                                 | OR_FCM_CST \
 152                                 | OR_FCM_CHT \
 153                                 | OR_FCM_SCY_1 \
 154                                 | OR_FCM_TRLX \
 155                                 | OR_FCM_EHTR)
 156
 157 #define CONFIG_SYS_BR0_PRELIM   CONFIG_FLASH_BR_PRELIM  /* NOR Base Address */
 158 #define CONFIG_SYS_OR0_PRELIM   CONFIG_FLASH_OR_PRELIM  /* NOR Options */
 159 #define CONFIG_SYS_BR1_PRELIM   CONFIG_SYS_NAND_BR_PRELIM
 160 #define CONFIG_SYS_OR1_PRELIM   CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
 161
 162 /* Serial Port */
 163 #define CONFIG_CONS_INDEX               1
 164 #undef  CONFIG_SERIAL_SOFTWARE_FIFO
 165 #define CONFIG_SYS_NS16550
 166 #define CONFIG_SYS_NS16550_SERIAL
 167 #define CONFIG_SYS_NS16550_REG_SIZE     1
 168 #define CONFIG_SYS_NS16550_CLK          get_bus_freq(0)
 169
 170 #define CONFIG_SYS_BAUDRATE_TABLE       \
 171         {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
 172
 173 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR + 0x4500)
 174 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR + 0x4600)
 175
 176 /* Use the HUSH parser */
 177 #define CONFIG_SYS_HUSH_PARSER
 178
 179 /*
 180  * Pass open firmware flat tree
 181  */
 182 #define CONFIG_OF_LIBFDT
 183 #define CONFIG_OF_BOARD_SETUP
 184 #define CONFIG_OF_STDOUT_VIA_ALIAS
 185
 186 /* new uImage format support */
 187 #define CONFIG_FIT
 188 #define CONFIG_FIT_VERBOSE      /* enable fit_format_{error,warning}() */
 189
 190 /* I2C */
 191 #define CONFIG_SYS_I2C
 192 #define CONFIG_SYS_I2C_FSL
 193 #define CONFIG_SYS_FSL_I2C_SPEED        400000
 194 #define CONFIG_SYS_FSL_I2C_SLAVE        0x7F
 195 #define CONFIG_SYS_FSL_I2C_OFFSET       0x3000
 196 #define CONFIG_SYS_FSL_I2C2_SPEED       400000
 197 #define CONFIG_SYS_FSL_I2C2_SLAVE       0x7F
 198 #define CONFIG_SYS_FSL_I2C2_OFFSET      0x3100
 199
 200 /*
 201  * I2C2 EEPROM
 202  */
 203 #define CONFIG_ID_EEPROM
 204 #ifdef CONFIG_ID_EEPROM
 205 #define CONFIG_SYS_I2C_EEPROM_NXID
 206 #endif
 207 #define CONFIG_SYS_I2C_EEPROM_ADDR              0x50
 208 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN          1
 209 #define CONFIG_SYS_EEPROM_BUS_NUM               0
 210
 211 #define CONFIG_CMD_I2C
 212
 213 /*
 214  * General PCI
 215  * Memory space is mapped 1-1, but I/O space must start from 0.
 216  */
 217
 218 /* controller 3, Slot 1, tgtid 3, Base address b000 */
 219 #define CONFIG_SYS_PCIE3_NAME           "Slot 3"
 220 #define CONFIG_SYS_PCIE3_MEM_VIRT       0x80000000
 221 #define CONFIG_SYS_PCIE3_MEM_BUS        0x80000000
 222 #define CONFIG_SYS_PCIE3_MEM_PHYS       0x80000000
 223 #define CONFIG_SYS_PCIE3_MEM_SIZE       0x20000000      /* 512M */
 224 #define CONFIG_SYS_PCIE3_IO_VIRT        0xffc00000
 225 #define CONFIG_SYS_PCIE3_IO_BUS         0x00000000
 226 #define CONFIG_SYS_PCIE3_IO_PHYS        0xffc00000
 227 #define CONFIG_SYS_PCIE3_IO_SIZE        0x00010000      /* 64k */
 228
 229 /* controller 2, direct to uli, tgtid 2, Base address 9000 */
 230 #define CONFIG_SYS_PCIE2_NAME           "Slot 2"
 231 #define CONFIG_SYS_PCIE2_MEM_VIRT       0xa0000000
 232 #define CONFIG_SYS_PCIE2_MEM_BUS        0xa0000000
 233 #define CONFIG_SYS_PCIE2_MEM_PHYS       0xa0000000
 234 #define CONFIG_SYS_PCIE2_MEM_SIZE       0x20000000      /* 512M */
 235 #define CONFIG_SYS_PCIE2_IO_VIRT        0xffc10000
 236 #define CONFIG_SYS_PCIE2_IO_BUS         0x00000000
 237 #define CONFIG_SYS_PCIE2_IO_PHYS        0xffc10000
 238 #define CONFIG_SYS_PCIE2_IO_SIZE        0x00010000      /* 64k */
 239
 240 /* controller 1, Slot 2, tgtid 1, Base address a000 */
 241 #define CONFIG_SYS_PCIE1_NAME           "Slot 1"
 242 #define CONFIG_SYS_PCIE1_MEM_VIRT       0xc0000000
 243 #define CONFIG_SYS_PCIE1_MEM_BUS        0xc0000000
 244 #define CONFIG_SYS_PCIE1_MEM_PHYS       0xc0000000
 245 #define CONFIG_SYS_PCIE1_MEM_SIZE       0x20000000      /* 512M */
 246 #define CONFIG_SYS_PCIE1_IO_VIRT        0xffc20000
 247 #define CONFIG_SYS_PCIE1_IO_BUS         0x00000000
 248 #define CONFIG_SYS_PCIE1_IO_PHYS        0xffc20000
 249 #define CONFIG_SYS_PCIE1_IO_SIZE        0x00010000      /* 64k */
 250
 251 #if defined(CONFIG_PCI)
 252 #define CONFIG_PCI_PNP          /* do pci plug-and-play */
 253 #define CONFIG_PCI_SCAN_SHOW    /* show pci devices on startup */
 254 #endif  /* CONFIG_PCI */
 255
 256 /*
 257  * Environment
 258  */
 259 #define CONFIG_ENV_OVERWRITE
 260
 261 #define CONFIG_ENV_IS_IN_FLASH
 262 #define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
 263 #define CONFIG_ENV_SIZE         0x2000
 264 #define CONFIG_ENV_SECT_SIZE    0x20000 /* 128K (one sector) */
 265
 266 #define CONFIG_LOADS_ECHO               /* echo on for serial download */
 267 #define CONFIG_SYS_LOADS_BAUD_CHANGE    /* allow baudrate change */
 268
 269 /*
 270  * Command line configuration.
 271  */
 272 #define CONFIG_CMD_IRQ
 273 #define CONFIG_CMD_PING
 274 #define CONFIG_CMD_MII
 275 #define CONFIG_CMD_REGINFO
 276
 277 #if defined(CONFIG_PCI)
 278 #define CONFIG_CMD_PCI
 279 #endif
 280
 281 /*
 282  * USB
 283  */
 284 #define CONFIG_HAS_FSL_DR_USB
 285 #ifdef CONFIG_HAS_FSL_DR_USB
 286 #define CONFIG_USB_EHCI
 287
 288 #ifdef CONFIG_USB_EHCI
 289 #define CONFIG_CMD_USB
 290 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
 291 #define CONFIG_USB_EHCI_FSL
 292 #define CONFIG_USB_STORAGE
 293 #define CONFIG_CMD_FAT
 294 #define CONFIG_CMD_EXT2
 295 #define CONFIG_CMD_FAT
 296 #define CONFIG_DOS_PARTITION
 297 #endif
 298 #endif
 299
 300 /*
 301  * Miscellaneous configurable options
 302  */
 303 #define CONFIG_SYS_LONGHELP                     /* undef to save memory */
 304 #define CONFIG_CMDLINE_EDITING          /* Command-line editing */
 305 #define CONFIG_SYS_LOAD_ADDR    0x2000000       /* default load address */
 306 #if defined(CONFIG_CMD_KGDB)
 307 #define CONFIG_SYS_CBSIZE       1024            /* Console I/O Buffer Size */
 308 #else
 309 #define CONFIG_SYS_CBSIZE       256             /* Console I/O Buffer Size */
 310 #endif
 311 /* Print Buffer Size */
 312 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT)+16)
 313 #define CONFIG_SYS_MAXARGS      16              /* max number of command args */
 314 /* Boot Argument Buffer Size */
 315 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE
 316
 317 /*
 318  * For booting Linux, the board info and command line data
 319  * have to be in the first 64 MB of memory, since this is
 320  * the maximum mapped by the Linux kernel during initialization.
 321  */
 322 #define CONFIG_SYS_BOOTMAPSZ    (64 << 20)   /* Initial Memory map for Linux*/
 323 #define CONFIG_SYS_BOOTM_LEN    (64 << 20)   /* Increase max gunzip size */
 324
 325 /*
 326  * Environment Configuration
 327  */
 328 #define CONFIG_BOOTFILE         "uImage"
 329 #define CONFIG_UBOOTPATH        (u-boot.bin) /* U-Boot image on TFTP server */
 330
 331 /* default location for tftp and bootm */
 332 #define CONFIG_LOADADDR         1000000
 333
 334 #define CONFIG_BOOTDELAY -1     /* -1 disables auto-boot */
 335
 336 #define CONFIG_BAUDRATE 115200
 337
 338 /* Qman/Bman */
 339 #define CONFIG_SYS_DPAA_QBMAN           /* support Q/Bman */
 340 #define CONFIG_SYS_QMAN_MEM_BASE        0xff000000
 341 #define CONFIG_SYS_QMAN_MEM_PHYS        CONFIG_SYS_QMAN_MEM_BASE
 342 #define CONFIG_SYS_QMAN_MEM_SIZE        0x00200000
 343 #define CONFIG_SYS_QMAN_SP_CENA_SIZE    0x4000
 344 #define CONFIG_SYS_QMAN_SP_CINH_SIZE    0x1000
 345 #define CONFIG_SYS_QMAN_CENA_BASE       CONFIG_SYS_QMAN_MEM_BASE
 346 #define CONFIG_SYS_QMAN_CENA_SIZE       (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
 347 #define CONFIG_SYS_QMAN_CINH_BASE       (CONFIG_SYS_QMAN_MEM_BASE + \
 348                                         CONFIG_SYS_QMAN_CENA_SIZE)
 349 #define CONFIG_SYS_QMAN_CINH_SIZE       (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
 350 #define CONFIG_SYS_QMAN_SWP_ISDR_REG    0xE08
 351 #define CONFIG_SYS_BMAN_MEM_BASE        0xff200000
 352 #define CONFIG_SYS_BMAN_MEM_PHYS        CONFIG_SYS_BMAN_MEM_BASE
 353 #define CONFIG_SYS_BMAN_MEM_SIZE        0x00200000
 354 #define CONFIG_SYS_BMAN_SP_CENA_SIZE    0x4000
 355 #define CONFIG_SYS_BMAN_SP_CINH_SIZE    0x1000
 356 #define CONFIG_SYS_BMAN_CENA_BASE       CONFIG_SYS_BMAN_MEM_BASE
 357 #define CONFIG_SYS_BMAN_CENA_SIZE       (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
 358 #define CONFIG_SYS_BMAN_CINH_BASE       (CONFIG_SYS_BMAN_MEM_BASE + \
 359                                         CONFIG_SYS_BMAN_CENA_SIZE)
 360 #define CONFIG_SYS_BMAN_CINH_SIZE       (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
 361 #define CONFIG_SYS_BMAN_SWP_ISDR_REG    0xE08
 362
 363 /* For FM */
 364 #define CONFIG_SYS_DPAA_FMAN
 365 #define CONFIG_PHY_GIGE         /* Include GbE speed/duplex detection */
 366
 367 #ifdef CONFIG_SYS_DPAA_FMAN
 368 #define CONFIG_FMAN_ENET
 369 #define CONFIG_PHY_ATHEROS
 370 #endif
 371
 372 /* Default address of microcode for the Linux Fman driver */
 373 /* QE microcode/firmware address */
 374 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR
 375 #define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000
 376 #define CONFIG_SYS_QE_FMAN_FW_LENGTH    0x10000
 377 #define CONFIG_SYS_FDT_PAD              (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
 378
 379 #ifdef CONFIG_FMAN_ENET
 380 #define CONFIG_SYS_FM1_DTSEC1_PHY_ADDR  0x1
 381 #define CONFIG_SYS_FM1_DTSEC2_PHY_ADDR  0x2
 382
 383 #define CONFIG_SYS_TBIPA_VALUE  8
 384 #define CONFIG_MII              /* MII PHY management */
 385 #define CONFIG_ETHPRIME         "FM1@DTSEC1"
 386 #endif
 387
 388 #define CONFIG_EXTRA_ENV_SETTINGS       \
 389         "netdev=eth0\0"                                         \
 390         "uboot=" __stringify(CONFIG_UBOOTPATH) "\0"             \
 391         "loadaddr=1000000\0"                                    \
 392         "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0"     \
 393         "tftpflash=tftpboot $loadaddr $uboot; "                 \
 394                 "protect off $ubootaddr +$filesize; "           \
 395                 "erase $ubootaddr +$filesize; "                 \
 396                 "cp.b $loadaddr $ubootaddr $filesize; "         \
 397                 "protect on $ubootaddr +$filesize; "            \
 398                 "cmp.b $loadaddr $ubootaddr $filesize\0"        \
 399         "consoledev=ttyS0\0"                                    \
 400         "ramdiskaddr=2000000\0"                                 \
 401         "ramdiskfile=rootfs.ext2.gz.uboot\0"                    \
 402         "fdtaddr=c00000\0"                                      \
 403         "fdtfile=p1023rdb.dtb\0"                                \
 404         "othbootargs=ramdisk_size=600000\0"                     \
 405         "bdev=sda1\0"                                           \
 406         "hwconfig=usb1:dr_mode=host,phy_type=ulpi\0"
 407
 408 #define CONFIG_HDBOOT                                   \
 409         "setenv bootargs root=/dev/$bdev rw "           \
 410         "console=$consoledev,$baudrate $othbootargs;"   \
 411         "tftp $loadaddr $bootfile;"                     \
 412         "tftp $fdtaddr $fdtfile;"                       \
 413         "bootm $loadaddr - $fdtaddr"
 414
 415 #define CONFIG_NFSBOOTCOMMAND                                           \
 416         "setenv bootargs root=/dev/nfs rw "                             \
 417         "nfsroot=$serverip:$rootpath "                                  \
 418         "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
 419         "console=$consoledev,$baudrate $othbootargs;"                   \
 420         "tftp $loadaddr $bootfile;"                                     \
 421         "tftp $fdtaddr $fdtfile;"                                       \
 422         "bootm $loadaddr - $fdtaddr"
 423
 424 #define CONFIG_RAMBOOTCOMMAND                                           \
 425         "setenv bootargs root=/dev/ram rw "                             \
 426         "console=$consoledev,$baudrate $othbootargs;"                   \
 427         "tftp $ramdiskaddr $ramdiskfile;"                               \
 428         "tftp $loadaddr $bootfile;"                                     \
 429         "tftp $fdtaddr $fdtfile;"                                       \
 430         "bootm $loadaddr $ramdiskaddr $fdtaddr"
 431
 432 #define CONFIG_BOOTCOMMAND              CONFIG_RAMBOOTCOMMAND
 433
 434 #endif  /* __CONFIG_H */