1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright 2013 Freescale Semiconductor, Inc.
5 * Authors: Roy Zang <tie-fei.zang@freescale.com>
6 * Chunhe Lan <Chunhe.Lan@freescale.com>
12 #ifndef CONFIG_SYS_MONITOR_BASE
13 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
16 #ifndef CONFIG_RESET_VECTOR_ADDRESS
17 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
20 /* High Level Configuration Options */
22 #define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */
23 #define CONFIG_PCIE1 /* PCIE controller 1 (slot 1) */
24 #define CONFIG_PCIE2 /* PCIE controller 2 (slot 2) */
25 #define CONFIG_PCIE3 /* PCIE controller 3 (slot 3) */
26 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */
27 #define CONFIG_FSL_PCIE_RESET /* need PCIe reset errata */
28 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
31 extern unsigned long get_clock_freq(void);
34 #define CONFIG_SYS_CLK_FREQ 66666666
35 #define CONFIG_DDR_CLK_FREQ CONFIG_SYS_CLK_FREQ
38 * These can be toggled for performance analysis, otherwise use default.
40 #define CONFIG_L2_CACHE /* toggle L2 cache */
41 #define CONFIG_BTB /* toggle branch predition */
42 #define CONFIG_HWCONFIG
44 #define CONFIG_ENABLE_36BIT_PHYS
46 #define CONFIG_SYS_MEMTEST_START 0x01000000 /* memtest works on */
47 #define CONFIG_SYS_MEMTEST_END 0x02000000
49 /* Implement conversion of addresses in the LBC */
50 #define CONFIG_SYS_LBC_LBCR 0x00000000
51 #define CONFIG_SYS_LBC_LCRR LCRR_CLKDIV_8
54 #define CONFIG_VERY_BIG_RAM
55 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
56 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
58 #define CONFIG_DIMM_SLOTS_PER_CTLR 1
59 #define CONFIG_CHIP_SELECTS_PER_CTRL 1
61 #define CONFIG_DDR_SPD
62 #define CONFIG_FSL_DDR_INTERACTIVE
63 #define CONFIG_SYS_SDRAM_SIZE 512u /* DDR is 512M */
64 #define CONFIG_SYS_SPD_BUS_NUM 0
65 #define SPD_EEPROM_ADDRESS 0x50
66 #define CONFIG_SYS_DDR_RAW_TIMING
71 * 0x0000_0000 0x1fff_ffff DDR 512M cacheable
72 * 0x8000_0000 0xbfff_ffff PCI Express Mem 1G non-cacheable
73 * 0xc000_0000 0xdfff_ffff PCI 512M non-cacheable
74 * 0xe100_0000 0xe3ff_ffff PCI IO range 4M non-cacheable
75 * 0xff00_0000 0xff3f_ffff DPAA_QBMAN 4M cacheable
76 * 0xff60_0000 0xff7f_ffff CCSR 2M non-cacheable
77 * 0xffd0_0000 0xffd0_3fff L1 for stack 16K cacheable TLB0
79 * Localbus non-cacheable
81 * 0xec00_0000 0xefff_ffff NOR flash 64M non-cacheable
82 * 0xffa0_0000 0xffaf_ffff NAND 1M non-cacheable
86 * Local Bus Definitions
88 #define CONFIG_SYS_FLASH_BASE 0xec000000 /* start of FLASH 64M */
89 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
91 #define CONFIG_FLASH_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) \
93 #define CONFIG_FLASH_OR_PRELIM 0xfc000ff7
95 #define CONFIG_FLASH_CFI_DRIVER
96 #define CONFIG_SYS_FLASH_CFI
97 #define CONFIG_SYS_FLASH_EMPTY_INFO
98 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
99 #define CONFIG_SYS_MAX_FLASH_SECT 512 /* sectors per device */
100 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
101 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
103 #define CONFIG_SYS_INIT_RAM_LOCK
104 #define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* Initial L1 address */
105 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000/* Size of used area in RAM */
106 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
107 GENERATED_GBL_DATA_SIZE)
108 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
110 #define CONFIG_SYS_MONITOR_LEN (768 * 1024) /* Reserve 512 kB for Mon */
111 #define CONFIG_SYS_MALLOC_LEN (6 * 1024 * 1024) /* Reserved for malloc */
113 #define CONFIG_SYS_NAND_BASE 0xffa00000
114 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
116 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
117 #define CONFIG_SYS_MAX_NAND_DEVICE 1
118 #define CONFIG_NAND_FSL_ELBC
119 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
121 /* NAND flash config */
122 #define CONFIG_SYS_NAND_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
123 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
124 | BR_PS_8 /* Port Size = 8bit */ \
125 | BR_MS_FCM /* MSEL = FCM */ \
127 #define CONFIG_SYS_NAND_OR_PRELIM (OR_AM_256KB /* length 256K */ \
136 #define CONFIG_SYS_BR0_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */
137 #define CONFIG_SYS_OR0_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */
138 #define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_NAND_BR_PRELIM
139 #define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
142 #undef CONFIG_SERIAL_SOFTWARE_FIFO
143 #define CONFIG_SYS_NS16550_SERIAL
144 #define CONFIG_SYS_NS16550_REG_SIZE 1
145 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
147 #define CONFIG_SYS_BAUDRATE_TABLE \
148 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
150 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR + 0x4500)
151 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR + 0x4600)
154 #define CONFIG_SYS_I2C
155 #define CONFIG_SYS_I2C_FSL
156 #define CONFIG_SYS_FSL_I2C_SPEED 400000
157 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
158 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
159 #define CONFIG_SYS_FSL_I2C2_SPEED 400000
160 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
161 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
166 #define CONFIG_ID_EEPROM
167 #ifdef CONFIG_ID_EEPROM
168 #define CONFIG_SYS_I2C_EEPROM_NXID
170 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50
171 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
172 #define CONFIG_SYS_EEPROM_BUS_NUM 0
176 * Memory space is mapped 1-1, but I/O space must start from 0.
179 /* controller 3, Slot 1, tgtid 3, Base address b000 */
180 #define CONFIG_SYS_PCIE3_NAME "Slot 3"
181 #define CONFIG_SYS_PCIE3_MEM_VIRT 0x80000000
182 #define CONFIG_SYS_PCIE3_MEM_BUS 0x80000000
183 #define CONFIG_SYS_PCIE3_MEM_PHYS 0x80000000
184 #define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */
185 #define CONFIG_SYS_PCIE3_IO_VIRT 0xffc00000
186 #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000
187 #define CONFIG_SYS_PCIE3_IO_PHYS 0xffc00000
188 #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */
190 /* controller 2, direct to uli, tgtid 2, Base address 9000 */
191 #define CONFIG_SYS_PCIE2_NAME "Slot 2"
192 #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000
193 #define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000
194 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000
195 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */
196 #define CONFIG_SYS_PCIE2_IO_VIRT 0xffc10000
197 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
198 #define CONFIG_SYS_PCIE2_IO_PHYS 0xffc10000
199 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */
201 /* controller 1, Slot 2, tgtid 1, Base address a000 */
202 #define CONFIG_SYS_PCIE1_NAME "Slot 1"
203 #define CONFIG_SYS_PCIE1_MEM_VIRT 0xc0000000
204 #define CONFIG_SYS_PCIE1_MEM_BUS 0xc0000000
205 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc0000000
206 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */
207 #define CONFIG_SYS_PCIE1_IO_VIRT 0xffc20000
208 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
209 #define CONFIG_SYS_PCIE1_IO_PHYS 0xffc20000
210 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
212 #if defined(CONFIG_PCI)
213 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
214 #endif /* CONFIG_PCI */
219 #define CONFIG_ENV_OVERWRITE
221 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
222 #define CONFIG_ENV_SIZE 0x2000
223 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */
225 #define CONFIG_LOADS_ECHO /* echo on for serial download */
226 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */
231 #define CONFIG_HAS_FSL_DR_USB
232 #ifdef CONFIG_HAS_FSL_DR_USB
233 #ifdef CONFIG_USB_EHCI_HCD
234 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
235 #define CONFIG_USB_EHCI_FSL
240 * Miscellaneous configurable options
242 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
245 * For booting Linux, the board info and command line data
246 * have to be in the first 64 MB of memory, since this is
247 * the maximum mapped by the Linux kernel during initialization.
249 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux*/
250 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
253 * Environment Configuration
255 #define CONFIG_BOOTFILE "uImage"
256 #define CONFIG_UBOOTPATH (u-boot.bin) /* U-Boot image on TFTP server */
258 /* default location for tftp and bootm */
259 #define CONFIG_LOADADDR 1000000
262 #define CONFIG_SYS_QMAN_MEM_BASE 0xff000000
263 #define CONFIG_SYS_QMAN_MEM_PHYS CONFIG_SYS_QMAN_MEM_BASE
264 #define CONFIG_SYS_QMAN_MEM_SIZE 0x00200000
265 #define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000
266 #define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000
267 #define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE
268 #define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
269 #define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \
270 CONFIG_SYS_QMAN_CENA_SIZE)
271 #define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
272 #define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08
273 #define CONFIG_SYS_BMAN_MEM_BASE 0xff200000
274 #define CONFIG_SYS_BMAN_MEM_PHYS CONFIG_SYS_BMAN_MEM_BASE
275 #define CONFIG_SYS_BMAN_MEM_SIZE 0x00200000
276 #define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000
277 #define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000
278 #define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE
279 #define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
280 #define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \
281 CONFIG_SYS_BMAN_CENA_SIZE)
282 #define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
283 #define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08
286 #define CONFIG_SYS_DPAA_FMAN
288 #ifdef CONFIG_SYS_DPAA_FMAN
289 #define CONFIG_FMAN_ENET
290 #define CONFIG_PHY_ATHEROS
293 /* Default address of microcode for the Linux Fman driver */
294 /* QE microcode/firmware address */
295 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR
296 #define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000
297 #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000
298 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
300 #ifdef CONFIG_FMAN_ENET
301 #define CONFIG_SYS_FM1_DTSEC1_PHY_ADDR 0x1
302 #define CONFIG_SYS_FM1_DTSEC2_PHY_ADDR 0x2
304 #define CONFIG_SYS_TBIPA_VALUE 8
305 #define CONFIG_MII /* MII PHY management */
306 #define CONFIG_ETHPRIME "FM1@DTSEC1"
309 #define CONFIG_EXTRA_ENV_SETTINGS \
311 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
312 "loadaddr=1000000\0" \
313 "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \
314 "tftpflash=tftpboot $loadaddr $uboot; " \
315 "protect off $ubootaddr +$filesize; " \
316 "erase $ubootaddr +$filesize; " \
317 "cp.b $loadaddr $ubootaddr $filesize; " \
318 "protect on $ubootaddr +$filesize; " \
319 "cmp.b $loadaddr $ubootaddr $filesize\0" \
320 "consoledev=ttyS0\0" \
321 "ramdiskaddr=2000000\0" \
322 "ramdiskfile=rootfs.ext2.gz.uboot\0" \
323 "fdtaddr=1e00000\0" \
324 "fdtfile=p1023rdb.dtb\0" \
325 "othbootargs=ramdisk_size=600000\0" \
327 "hwconfig=usb1:dr_mode=host,phy_type=ulpi\0"
329 #define CONFIG_HDBOOT \
330 "setenv bootargs root=/dev/$bdev rw " \
331 "console=$consoledev,$baudrate $othbootargs;" \
332 "tftp $loadaddr $bootfile;" \
333 "tftp $fdtaddr $fdtfile;" \
334 "bootm $loadaddr - $fdtaddr"
336 #define CONFIG_NFSBOOTCOMMAND \
337 "setenv bootargs root=/dev/nfs rw " \
338 "nfsroot=$serverip:$rootpath " \
339 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
340 "console=$consoledev,$baudrate $othbootargs;" \
341 "tftp $loadaddr $bootfile;" \
342 "tftp $fdtaddr $fdtfile;" \
343 "bootm $loadaddr - $fdtaddr"
345 #define CONFIG_RAMBOOTCOMMAND \
346 "setenv bootargs root=/dev/ram rw " \
347 "console=$consoledev,$baudrate $othbootargs;" \
348 "tftp $ramdiskaddr $ramdiskfile;" \
349 "tftp $loadaddr $bootfile;" \
350 "tftp $fdtaddr $fdtfile;" \
351 "bootm $loadaddr $ramdiskaddr $fdtaddr"
353 #define CONFIG_BOOTCOMMAND CONFIG_RAMBOOTCOMMAND
355 #endif /* __CONFIG_H */