git.sur5r.net Git - u-boot/blob - include/configs/P1023RDB.h

   1 /*
   2  * Copyright 2013 Freescale Semiconductor, Inc.
   3  *
   4  * Authors:  Roy Zang <tie-fei.zang@freescale.com>
   5  *           Chunhe Lan <Chunhe.Lan@freescale.com>
   6  *
   7  * SPDX-License-Identifier:     GPL-2.0+
   8  */
   9
  10 #ifndef __CONFIG_H
  11 #define __CONFIG_H
  12
  13 #ifndef CONFIG_SYS_MONITOR_BASE
  14 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE    /* start of monitor */
  15 #endif
  16
  17 #ifndef CONFIG_RESET_VECTOR_ADDRESS
  18 #define CONFIG_RESET_VECTOR_ADDRESS     0xeffffffc
  19 #endif
  20
  21 /* High Level Configuration Options */
  22 #define CONFIG_MP               /* support multiple processors */
  23
  24 #define CONFIG_PCI_INDIRECT_BRIDGE     /* indirect PCI bridge support */
  25 #define CONFIG_PCIE1            /* PCIE controller 1 (slot 1) */
  26 #define CONFIG_PCIE2            /* PCIE controller 2 (slot 2) */
  27 #define CONFIG_PCIE3            /* PCIE controller 3 (slot 3) */
  28 #define CONFIG_FSL_PCI_INIT     /* Use common FSL init code */
  29 #define CONFIG_FSL_PCIE_RESET   /* need PCIe reset errata */
  30 #define CONFIG_SYS_PCI_64BIT    /* enable 64-bit PCI resources */
  31
  32 #ifndef __ASSEMBLY__
  33 extern unsigned long get_clock_freq(void);
  34 #endif
  35
  36 #define CONFIG_SYS_CLK_FREQ     66666666
  37 #define CONFIG_DDR_CLK_FREQ     CONFIG_SYS_CLK_FREQ
  38
  39 /*
  40  * These can be toggled for performance analysis, otherwise use default.
  41  */
  42 #define CONFIG_L2_CACHE                 /* toggle L2 cache */
  43 #define CONFIG_BTB                      /* toggle branch predition */
  44 #define CONFIG_HWCONFIG
  45
  46 #define CONFIG_ENABLE_36BIT_PHYS
  47
  48 #define CONFIG_SYS_MEMTEST_START        0x01000000      /* memtest works on */
  49 #define CONFIG_SYS_MEMTEST_END          0x02000000
  50
  51 /* Implement conversion of addresses in the LBC */
  52 #define CONFIG_SYS_LBC_LBCR             0x00000000
  53 #define CONFIG_SYS_LBC_LCRR             LCRR_CLKDIV_8
  54
  55 /* DDR Setup */
  56 #define CONFIG_VERY_BIG_RAM
  57 #define CONFIG_SYS_DDR_SDRAM_BASE       0x00000000
  58 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_SDRAM_BASE
  59
  60 #define CONFIG_DIMM_SLOTS_PER_CTLR      1
  61 #define CONFIG_CHIP_SELECTS_PER_CTRL    1
  62
  63 #define CONFIG_DDR_SPD
  64 #define CONFIG_FSL_DDR_INTERACTIVE
  65 #define CONFIG_SYS_SDRAM_SIZE           512u    /* DDR is 512M */
  66 #define CONFIG_SYS_SPD_BUS_NUM          0
  67 #define SPD_EEPROM_ADDRESS              0x50
  68 #define CONFIG_SYS_DDR_RAW_TIMING
  69
  70 /*
  71  * Memory map
  72  *
  73  * 0x0000_0000  0x1fff_ffff     DDR                     512M cacheable
  74  * 0x8000_0000  0xbfff_ffff     PCI Express Mem         1G non-cacheable
  75  * 0xc000_0000  0xdfff_ffff     PCI                     512M non-cacheable
  76  * 0xe100_0000  0xe3ff_ffff     PCI IO range            4M non-cacheable
  77  * 0xff00_0000  0xff3f_ffff     DPAA_QBMAN              4M cacheable
  78  * 0xff60_0000  0xff7f_ffff     CCSR                    2M non-cacheable
  79  * 0xffd0_0000  0xffd0_3fff     L1 for stack            16K cacheable TLB0
  80  *
  81  * Localbus non-cacheable
  82  *
  83  * 0xec00_0000  0xefff_ffff     NOR flash               64M non-cacheable
  84  * 0xffa0_0000  0xffaf_ffff     NAND                    1M non-cacheable
  85  */
  86
  87 /*
  88  * Local Bus Definitions
  89  */
  90 #define CONFIG_SYS_FLASH_BASE           0xec000000 /* start of FLASH 64M */
  91 #define CONFIG_SYS_FLASH_BASE_PHYS      CONFIG_SYS_FLASH_BASE
  92
  93 #define CONFIG_FLASH_BR_PRELIM  (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) \
  94                                 | BR_PS_16 | BR_V)
  95 #define CONFIG_FLASH_OR_PRELIM  0xfc000ff7
  96
  97 #define CONFIG_FLASH_CFI_DRIVER
  98 #define CONFIG_SYS_FLASH_CFI
  99 #define CONFIG_SYS_FLASH_EMPTY_INFO
 100 #define CONFIG_SYS_MAX_FLASH_BANKS      1       /* number of banks */
 101 #define CONFIG_SYS_MAX_FLASH_SECT       512     /* sectors per device */
 102 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000   /* Flash Erase Timeout (ms) */
 103 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Flash Write Timeout (ms) */
 104
 105 #define CONFIG_SYS_INIT_RAM_LOCK
 106 #define CONFIG_SYS_INIT_RAM_ADDR        0xffd00000      /* Initial L1 address */
 107 #define CONFIG_SYS_INIT_RAM_SIZE        0x00004000/* Size of used area in RAM */
 108 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - \
 109                                         GENERATED_GBL_DATA_SIZE)
 110 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 111
 112 #define CONFIG_SYS_MONITOR_LEN  (768 * 1024)      /* Reserve 512 kB for Mon */
 113 #define CONFIG_SYS_MALLOC_LEN   (6 * 1024 * 1024) /* Reserved for malloc */
 114
 115 #define CONFIG_SYS_NAND_BASE            0xffa00000
 116 #define CONFIG_SYS_NAND_BASE_PHYS       CONFIG_SYS_NAND_BASE
 117
 118 #define CONFIG_SYS_NAND_BASE_LIST       { CONFIG_SYS_NAND_BASE }
 119 #define CONFIG_SYS_MAX_NAND_DEVICE      1
 120 #define CONFIG_NAND_FSL_ELBC
 121 #define CONFIG_SYS_NAND_BLOCK_SIZE      (128 * 1024)
 122
 123 /* NAND flash config */
 124 #define CONFIG_SYS_NAND_BR_PRELIM  (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
 125                                 | (2<<BR_DECC_SHIFT)    /* Use HW ECC */ \
 126                                 | BR_PS_8               /* Port Size = 8bit */ \
 127                                 | BR_MS_FCM             /* MSEL = FCM */ \
 128                                 | BR_V)                 /* valid */
 129 #define CONFIG_SYS_NAND_OR_PRELIM  (OR_AM_256KB         /* length 256K */ \
 130                                 | OR_FCM_PGS \
 131                                 | OR_FCM_CSCT \
 132                                 | OR_FCM_CST \
 133                                 | OR_FCM_CHT \
 134                                 | OR_FCM_SCY_1 \
 135                                 | OR_FCM_TRLX \
 136                                 | OR_FCM_EHTR)
 137
 138 #define CONFIG_SYS_BR0_PRELIM   CONFIG_FLASH_BR_PRELIM  /* NOR Base Address */
 139 #define CONFIG_SYS_OR0_PRELIM   CONFIG_FLASH_OR_PRELIM  /* NOR Options */
 140 #define CONFIG_SYS_BR1_PRELIM   CONFIG_SYS_NAND_BR_PRELIM
 141 #define CONFIG_SYS_OR1_PRELIM   CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
 142
 143 /* Serial Port */
 144 #undef  CONFIG_SERIAL_SOFTWARE_FIFO
 145 #define CONFIG_SYS_NS16550_SERIAL
 146 #define CONFIG_SYS_NS16550_REG_SIZE     1
 147 #define CONFIG_SYS_NS16550_CLK          get_bus_freq(0)
 148
 149 #define CONFIG_SYS_BAUDRATE_TABLE       \
 150         {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
 151
 152 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR + 0x4500)
 153 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR + 0x4600)
 154
 155 /* I2C */
 156 #define CONFIG_SYS_I2C
 157 #define CONFIG_SYS_I2C_FSL
 158 #define CONFIG_SYS_FSL_I2C_SPEED        400000
 159 #define CONFIG_SYS_FSL_I2C_SLAVE        0x7F
 160 #define CONFIG_SYS_FSL_I2C_OFFSET       0x3000
 161 #define CONFIG_SYS_FSL_I2C2_SPEED       400000
 162 #define CONFIG_SYS_FSL_I2C2_SLAVE       0x7F
 163 #define CONFIG_SYS_FSL_I2C2_OFFSET      0x3100
 164
 165 /*
 166  * I2C2 EEPROM
 167  */
 168 #define CONFIG_ID_EEPROM
 169 #ifdef CONFIG_ID_EEPROM
 170 #define CONFIG_SYS_I2C_EEPROM_NXID
 171 #endif
 172 #define CONFIG_SYS_I2C_EEPROM_ADDR              0x50
 173 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN          1
 174 #define CONFIG_SYS_EEPROM_BUS_NUM               0
 175
 176 /*
 177  * General PCI
 178  * Memory space is mapped 1-1, but I/O space must start from 0.
 179  */
 180
 181 /* controller 3, Slot 1, tgtid 3, Base address b000 */
 182 #define CONFIG_SYS_PCIE3_NAME           "Slot 3"
 183 #define CONFIG_SYS_PCIE3_MEM_VIRT       0x80000000
 184 #define CONFIG_SYS_PCIE3_MEM_BUS        0x80000000
 185 #define CONFIG_SYS_PCIE3_MEM_PHYS       0x80000000
 186 #define CONFIG_SYS_PCIE3_MEM_SIZE       0x20000000      /* 512M */
 187 #define CONFIG_SYS_PCIE3_IO_VIRT        0xffc00000
 188 #define CONFIG_SYS_PCIE3_IO_BUS         0x00000000
 189 #define CONFIG_SYS_PCIE3_IO_PHYS        0xffc00000
 190 #define CONFIG_SYS_PCIE3_IO_SIZE        0x00010000      /* 64k */
 191
 192 /* controller 2, direct to uli, tgtid 2, Base address 9000 */
 193 #define CONFIG_SYS_PCIE2_NAME           "Slot 2"
 194 #define CONFIG_SYS_PCIE2_MEM_VIRT       0xa0000000
 195 #define CONFIG_SYS_PCIE2_MEM_BUS        0xa0000000
 196 #define CONFIG_SYS_PCIE2_MEM_PHYS       0xa0000000
 197 #define CONFIG_SYS_PCIE2_MEM_SIZE       0x20000000      /* 512M */
 198 #define CONFIG_SYS_PCIE2_IO_VIRT        0xffc10000
 199 #define CONFIG_SYS_PCIE2_IO_BUS         0x00000000
 200 #define CONFIG_SYS_PCIE2_IO_PHYS        0xffc10000
 201 #define CONFIG_SYS_PCIE2_IO_SIZE        0x00010000      /* 64k */
 202
 203 /* controller 1, Slot 2, tgtid 1, Base address a000 */
 204 #define CONFIG_SYS_PCIE1_NAME           "Slot 1"
 205 #define CONFIG_SYS_PCIE1_MEM_VIRT       0xc0000000
 206 #define CONFIG_SYS_PCIE1_MEM_BUS        0xc0000000
 207 #define CONFIG_SYS_PCIE1_MEM_PHYS       0xc0000000
 208 #define CONFIG_SYS_PCIE1_MEM_SIZE       0x20000000      /* 512M */
 209 #define CONFIG_SYS_PCIE1_IO_VIRT        0xffc20000
 210 #define CONFIG_SYS_PCIE1_IO_BUS         0x00000000
 211 #define CONFIG_SYS_PCIE1_IO_PHYS        0xffc20000
 212 #define CONFIG_SYS_PCIE1_IO_SIZE        0x00010000      /* 64k */
 213
 214 #if defined(CONFIG_PCI)
 215 #define CONFIG_PCI_SCAN_SHOW    /* show pci devices on startup */
 216 #endif  /* CONFIG_PCI */
 217
 218 /*
 219  * Environment
 220  */
 221 #define CONFIG_ENV_OVERWRITE
 222
 223 #define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
 224 #define CONFIG_ENV_SIZE         0x2000
 225 #define CONFIG_ENV_SECT_SIZE    0x20000 /* 128K (one sector) */
 226
 227 #define CONFIG_LOADS_ECHO               /* echo on for serial download */
 228 #define CONFIG_SYS_LOADS_BAUD_CHANGE    /* allow baudrate change */
 229
 230 /*
 231  * USB
 232  */
 233 #define CONFIG_HAS_FSL_DR_USB
 234 #ifdef CONFIG_HAS_FSL_DR_USB
 235 #ifdef CONFIG_USB_EHCI_HCD
 236 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
 237 #define CONFIG_USB_EHCI_FSL
 238 #endif
 239 #endif
 240
 241 /*
 242  * Miscellaneous configurable options
 243  */
 244 #define CONFIG_SYS_LOAD_ADDR    0x2000000       /* default load address */
 245
 246 /*
 247  * For booting Linux, the board info and command line data
 248  * have to be in the first 64 MB of memory, since this is
 249  * the maximum mapped by the Linux kernel during initialization.
 250  */
 251 #define CONFIG_SYS_BOOTMAPSZ    (64 << 20)   /* Initial Memory map for Linux*/
 252 #define CONFIG_SYS_BOOTM_LEN    (64 << 20)   /* Increase max gunzip size */
 253
 254 /*
 255  * Environment Configuration
 256  */
 257 #define CONFIG_BOOTFILE         "uImage"
 258 #define CONFIG_UBOOTPATH        (u-boot.bin) /* U-Boot image on TFTP server */
 259
 260 /* default location for tftp and bootm */
 261 #define CONFIG_LOADADDR         1000000
 262
 263 /* Qman/Bman */
 264 #define CONFIG_SYS_QMAN_MEM_BASE        0xff000000
 265 #define CONFIG_SYS_QMAN_MEM_PHYS        CONFIG_SYS_QMAN_MEM_BASE
 266 #define CONFIG_SYS_QMAN_MEM_SIZE        0x00200000
 267 #define CONFIG_SYS_QMAN_SP_CENA_SIZE    0x4000
 268 #define CONFIG_SYS_QMAN_SP_CINH_SIZE    0x1000
 269 #define CONFIG_SYS_QMAN_CENA_BASE       CONFIG_SYS_QMAN_MEM_BASE
 270 #define CONFIG_SYS_QMAN_CENA_SIZE       (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
 271 #define CONFIG_SYS_QMAN_CINH_BASE       (CONFIG_SYS_QMAN_MEM_BASE + \
 272                                         CONFIG_SYS_QMAN_CENA_SIZE)
 273 #define CONFIG_SYS_QMAN_CINH_SIZE       (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
 274 #define CONFIG_SYS_QMAN_SWP_ISDR_REG    0xE08
 275 #define CONFIG_SYS_BMAN_MEM_BASE        0xff200000
 276 #define CONFIG_SYS_BMAN_MEM_PHYS        CONFIG_SYS_BMAN_MEM_BASE
 277 #define CONFIG_SYS_BMAN_MEM_SIZE        0x00200000
 278 #define CONFIG_SYS_BMAN_SP_CENA_SIZE    0x4000
 279 #define CONFIG_SYS_BMAN_SP_CINH_SIZE    0x1000
 280 #define CONFIG_SYS_BMAN_CENA_BASE       CONFIG_SYS_BMAN_MEM_BASE
 281 #define CONFIG_SYS_BMAN_CENA_SIZE       (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
 282 #define CONFIG_SYS_BMAN_CINH_BASE       (CONFIG_SYS_BMAN_MEM_BASE + \
 283                                         CONFIG_SYS_BMAN_CENA_SIZE)
 284 #define CONFIG_SYS_BMAN_CINH_SIZE       (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
 285 #define CONFIG_SYS_BMAN_SWP_ISDR_REG    0xE08
 286
 287 /* For FM */
 288 #define CONFIG_SYS_DPAA_FMAN
 289
 290 #ifdef CONFIG_SYS_DPAA_FMAN
 291 #define CONFIG_FMAN_ENET
 292 #define CONFIG_PHY_ATHEROS
 293 #endif
 294
 295 /* Default address of microcode for the Linux Fman driver */
 296 /* QE microcode/firmware address */
 297 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR
 298 #define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000
 299 #define CONFIG_SYS_QE_FMAN_FW_LENGTH    0x10000
 300 #define CONFIG_SYS_FDT_PAD              (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
 301
 302 #ifdef CONFIG_FMAN_ENET
 303 #define CONFIG_SYS_FM1_DTSEC1_PHY_ADDR  0x1
 304 #define CONFIG_SYS_FM1_DTSEC2_PHY_ADDR  0x2
 305
 306 #define CONFIG_SYS_TBIPA_VALUE  8
 307 #define CONFIG_MII              /* MII PHY management */
 308 #define CONFIG_ETHPRIME         "FM1@DTSEC1"
 309 #endif
 310
 311 #define CONFIG_EXTRA_ENV_SETTINGS       \
 312         "netdev=eth0\0"                                         \
 313         "uboot=" __stringify(CONFIG_UBOOTPATH) "\0"             \
 314         "loadaddr=1000000\0"                                    \
 315         "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0"     \
 316         "tftpflash=tftpboot $loadaddr $uboot; "                 \
 317                 "protect off $ubootaddr +$filesize; "           \
 318                 "erase $ubootaddr +$filesize; "                 \
 319                 "cp.b $loadaddr $ubootaddr $filesize; "         \
 320                 "protect on $ubootaddr +$filesize; "            \
 321                 "cmp.b $loadaddr $ubootaddr $filesize\0"        \
 322         "consoledev=ttyS0\0"                                    \
 323         "ramdiskaddr=2000000\0"                                 \
 324         "ramdiskfile=rootfs.ext2.gz.uboot\0"                    \
 325         "fdtaddr=1e00000\0"                                     \
 326         "fdtfile=p1023rdb.dtb\0"                                \
 327         "othbootargs=ramdisk_size=600000\0"                     \
 328         "bdev=sda1\0"                                           \
 329         "hwconfig=usb1:dr_mode=host,phy_type=ulpi\0"
 330
 331 #define CONFIG_HDBOOT                                   \
 332         "setenv bootargs root=/dev/$bdev rw "           \
 333         "console=$consoledev,$baudrate $othbootargs;"   \
 334         "tftp $loadaddr $bootfile;"                     \
 335         "tftp $fdtaddr $fdtfile;"                       \
 336         "bootm $loadaddr - $fdtaddr"
 337
 338 #define CONFIG_NFSBOOTCOMMAND                                           \
 339         "setenv bootargs root=/dev/nfs rw "                             \
 340         "nfsroot=$serverip:$rootpath "                                  \
 341         "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
 342         "console=$consoledev,$baudrate $othbootargs;"                   \
 343         "tftp $loadaddr $bootfile;"                                     \
 344         "tftp $fdtaddr $fdtfile;"                                       \
 345         "bootm $loadaddr - $fdtaddr"
 346
 347 #define CONFIG_RAMBOOTCOMMAND                                           \
 348         "setenv bootargs root=/dev/ram rw "                             \
 349         "console=$consoledev,$baudrate $othbootargs;"                   \
 350         "tftp $ramdiskaddr $ramdiskfile;"                               \
 351         "tftp $loadaddr $bootfile;"                                     \
 352         "tftp $fdtaddr $fdtfile;"                                       \
 353         "bootm $loadaddr $ramdiskaddr $fdtaddr"
 354
 355 #define CONFIG_BOOTCOMMAND              CONFIG_RAMBOOTCOMMAND
 356
 357 #endif  /* __CONFIG_H */