2 * Copyright 2009-2011 Freescale Semiconductor, Inc.
4 * SPDX-License-Identifier: GPL-2.0+
8 * P1 P2 RDB board configuration file
9 * This file is intended to address a set of Low End and Ultra Low End
10 * Freescale SOCs of QorIQ series(RDB platforms).
11 * Currently only P2020RDB
18 #define CONFIG_PHYS_64BIT
21 #ifdef CONFIG_P1011RDB
24 #ifdef CONFIG_P1020RDB
27 #ifdef CONFIG_P2010RDB
30 #ifdef CONFIG_P2020RDB
35 #define CONFIG_NAND_U_BOOT 1
36 #define CONFIG_RAMBOOT_NAND 1
37 #ifdef CONFIG_NAND_SPL
38 #define CONFIG_SYS_TEXT_BASE_SPL 0xfff00000
39 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE_SPL /* start of monitor */
41 #define CONFIG_SYS_LDSCRIPT $(TOPDIR)/$(CPUDIR)/u-boot-nand.lds
42 #define CONFIG_SYS_TEXT_BASE 0xf8f82000
43 #endif /* CONFIG_NAND_SPL */
47 #define CONFIG_RAMBOOT_SDCARD 1
48 #define CONFIG_SYS_TEXT_BASE 0x11000000
49 #define CONFIG_RESET_VECTOR_ADDRESS 0x1107fffc
52 #ifdef CONFIG_SPIFLASH
53 #define CONFIG_RAMBOOT_SPIFLASH 1
54 #define CONFIG_SYS_TEXT_BASE 0x11000000
55 #define CONFIG_RESET_VECTOR_ADDRESS 0x1107fffc
58 #ifndef CONFIG_SYS_TEXT_BASE
59 #define CONFIG_SYS_TEXT_BASE 0xeff80000
62 #ifndef CONFIG_RESET_VECTOR_ADDRESS
63 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
66 #ifndef CONFIG_SYS_MONITOR_BASE
67 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
70 /* High Level Configuration Options */
71 #define CONFIG_BOOKE 1 /* BOOKE */
72 #define CONFIG_E500 1 /* BOOKE e500 family */
73 #define CONFIG_MPC85xx 1 /* MPC8540/60/55/41/48/P1020/P2020,etc*/
74 #define CONFIG_FSL_ELBC 1 /* Enable eLBC Support */
76 #define CONFIG_PCI 1 /* Enable PCI/PCIE */
77 #if defined(CONFIG_PCI)
78 #define CONFIG_PCIE1 1 /* PCIE controler 1 (slot 1) */
79 #define CONFIG_PCIE2 1 /* PCIE controler 2 (slot 2) */
80 #define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */
81 #define CONFIG_PCI_INDIRECT_BRIDGE 1 /* indirect PCI bridge support */
82 #define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */
83 #define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */
84 #endif /* #if defined(CONFIG_PCI) */
85 #define CONFIG_FSL_LAW 1 /* Use common FSL init code */
86 #define CONFIG_TSEC_ENET /* tsec ethernet support */
87 #define CONFIG_ENV_OVERWRITE
89 #if defined(CONFIG_PCI)
90 #define CONFIG_E1000 1 /* E1000 pci Ethernet card*/
94 extern unsigned long get_board_sys_clk(unsigned long dummy);
96 #define CONFIG_DDR_CLK_FREQ 66666666 /* DDRCLK on P1_P2 RDB */
97 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk(0) /*sysclk for P1_P2 RDB */
99 #if defined(CONFIG_P2020) || defined(CONFIG_P1020)
103 #define CONFIG_HWCONFIG
106 * These can be toggled for performance analysis, otherwise use default.
108 #define CONFIG_L2_CACHE /* toggle L2 cache */
109 #define CONFIG_BTB /* toggle branch predition */
111 #define CONFIG_ADDR_STREAMING /* toggle addr streaming */
113 #define CONFIG_ENABLE_36BIT_PHYS 1
115 #ifdef CONFIG_PHYS_64BIT
116 #define CONFIG_ADDR_MAP 1
117 #define CONFIG_SYS_NUM_ADDR_MAP 16 /* number of TLB1 entries */
120 #define CONFIG_SYS_MEMTEST_START 0x00000000 /* memtest works on */
121 #define CONFIG_SYS_MEMTEST_END 0x1fffffff
122 #define CONFIG_PANIC_HANG /* do not reset board on panic */
125 * Config the L2 Cache as L2 SRAM
127 #define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000
128 #ifdef CONFIG_PHYS_64BIT
129 #define CONFIG_SYS_INIT_L2_ADDR_PHYS 0xff8f80000ull
131 #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR
133 #define CONFIG_SYS_L2_SIZE (512 << 10)
134 #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
136 #define CONFIG_SYS_CCSRBAR 0xffe00000
137 #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
139 #if defined(CONFIG_NAND_SPL)
140 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
144 #define CONFIG_FSL_DDR2
145 #undef CONFIG_FSL_DDR_INTERACTIVE
146 #undef CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */
148 #define CONFIG_MEM_INIT_VALUE 0xDeadBeef
150 #define CONFIG_SYS_SDRAM_SIZE 1024 /* DDR size on P1_P2 RDBs */
151 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
152 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
154 #define CONFIG_NUM_DDR_CONTROLLERS 1
155 #define CONFIG_DIMM_SLOTS_PER_CTLR 1
156 #define CONFIG_CHIP_SELECTS_PER_CTRL 1
158 #define CONFIG_SYS_DDR_ERR_INT_EN 0x0000000d
159 #define CONFIG_SYS_DDR_ERR_DIS 0x00000000
160 #define CONFIG_SYS_DDR_SBE 0x00FF0000
165 * 0x0000_0000 0x3fff_ffff DDR 1G cacheablen
166 * 0x8000_0000 0xbfff_ffff PCI Express Mem 1G non-cacheable
167 * 0xffc0_0000 0xffc3_ffff PCI IO range 256k non-cacheable
169 * Localbus cacheable (TBD)
170 * 0xXXXX_XXXX 0xXXXX_XXXX SRAM YZ M Cacheable
172 * Localbus non-cacheable
173 * 0xef00_0000 0xefff_ffff FLASH 16M non-cacheable
174 * 0xffa0_0000 0xffaf_ffff NAND 1M non-cacheable
175 * 0xffb0_0000 0xffbf_ffff VSC7385 switch 1M non-cacheable
176 * 0xffd0_0000 0xffd0_3fff L1 for stack 16K Cacheable TLB0
177 * 0xffe0_0000 0xffef_ffff CCSR 1M non-cacheable
181 * Local Bus Definitions
183 #define CONFIG_SYS_FLASH_BASE 0xef000000 /* start of FLASH 16M */
185 #ifdef CONFIG_PHYS_64BIT
186 #define CONFIG_SYS_FLASH_BASE_PHYS 0xfef000000ull
188 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
191 #define CONFIG_FLASH_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
193 #define CONFIG_FLASH_OR_PRELIM 0xff000ff7
195 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS}
196 #define CONFIG_SYS_FLASH_QUIET_TEST
197 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
199 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
200 #define CONFIG_SYS_MAX_FLASH_SECT 128 /* sectors per device */
201 #undef CONFIG_SYS_FLASH_CHECKSUM
202 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
203 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
205 #if defined(CONFIG_RAMBOOT_NAND) || defined(CONFIG_RAMBOOT_SDCARD) || \
206 defined(CONFIG_RAMBOOT_SPIFLASH)
207 #define CONFIG_SYS_RAMBOOT
208 #define CONFIG_SYS_EXTRA_ENV_RELOC
210 #undef CONFIG_SYS_RAMBOOT
213 #define CONFIG_FLASH_CFI_DRIVER
214 #define CONFIG_SYS_FLASH_CFI
215 #define CONFIG_SYS_FLASH_EMPTY_INFO
216 #define CONFIG_SYS_FLASH_AMD_CHECK_DQ7
218 #define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */
219 #define CONFIG_MISC_INIT_R
220 #define CONFIG_HWCONFIG
222 #define CONFIG_SYS_INIT_RAM_LOCK 1
223 #define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* stack in RAM */
224 #ifdef CONFIG_PHYS_64BIT
225 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
226 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR
227 /* The assembler doesn't like typecast */
228 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
229 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
230 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
232 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS CONFIG_SYS_INIT_RAM_ADDR /* Initial L1 address */
233 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0
234 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS
236 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 /* Size of used area in RAM */
238 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE \
239 - GENERATED_GBL_DATA_SIZE)
240 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
242 #define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon*/
243 #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc*/
245 #ifndef CONFIG_NAND_SPL
246 #define CONFIG_SYS_NAND_BASE 0xffa00000
247 #ifdef CONFIG_PHYS_64BIT
248 #define CONFIG_SYS_NAND_BASE_PHYS 0xfffa00000ull
250 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
253 #define CONFIG_SYS_NAND_BASE 0xfff00000
254 #ifdef CONFIG_PHYS_64BIT
255 #define CONFIG_SYS_NAND_BASE_PHYS 0xffff00000ull
257 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
261 #define CONFIG_CMD_NAND
262 #define CONFIG_SYS_NAND_BASE_LIST {CONFIG_SYS_NAND_BASE}
263 #define CONFIG_SYS_MAX_NAND_DEVICE 1
264 #define CONFIG_MTD_NAND_VERIFY_WRITE
265 #define CONFIG_NAND_FSL_ELBC 1
266 #define CONFIG_SYS_NAND_BLOCK_SIZE (16 * 1024)
268 /* NAND boot: 4K NAND loader config */
269 #define CONFIG_SYS_NAND_SPL_SIZE 0x1000
270 #define CONFIG_SYS_NAND_U_BOOT_SIZE ((512 << 10) - 0x2000)
271 #define CONFIG_SYS_NAND_U_BOOT_DST (CONFIG_SYS_INIT_L2_ADDR)
272 #define CONFIG_SYS_NAND_U_BOOT_START (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_NAND_SPL_SIZE)
273 #define CONFIG_SYS_NAND_U_BOOT_OFFS (0)
274 #define CONFIG_SYS_NAND_U_BOOT_RELOC (CONFIG_SYS_INIT_L2_END - 0x2000)
275 #define CONFIG_SYS_NAND_U_BOOT_RELOC_SP ((CONFIG_SYS_INIT_L2_END - 1) & ~0xF)
277 /* NAND flash config */
278 #define CONFIG_SYS_NAND_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
279 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
280 | BR_PS_8 /* Port Size = 8 bit */ \
281 | BR_MS_FCM /* MSEL = FCM */ \
284 #define CONFIG_SYS_NAND_OR_PRELIM (0xFFF80000 /* length 32K */ \
292 #ifdef CONFIG_RAMBOOT_NAND
293 #define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */
294 #define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
295 #define CONFIG_SYS_BR1_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */
296 #define CONFIG_SYS_OR1_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */
298 #define CONFIG_SYS_BR0_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */
299 #define CONFIG_SYS_OR0_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */
300 #define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */
301 #define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
304 #define CONFIG_SYS_VSC7385_BASE 0xffb00000
306 #ifdef CONFIG_PHYS_64BIT
307 #define CONFIG_SYS_VSC7385_BASE_PHYS 0xfffb00000ull
309 #define CONFIG_SYS_VSC7385_BASE_PHYS CONFIG_SYS_VSC7385_BASE
312 #define CONFIG_SYS_BR2_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_VSC7385_BASE) \
314 #define CONFIG_SYS_OR2_PRELIM (OR_AM_128KB | OR_GPCM_CSNT | OR_GPCM_XACS | \
315 OR_GPCM_SCY_15 | OR_GPCM_SETA | OR_GPCM_TRLX | \
316 OR_GPCM_EHTR | OR_GPCM_EAD)
318 /* Serial Port - controlled on board with jumper J8
322 #define CONFIG_CONS_INDEX 1
323 #define CONFIG_SYS_NS16550
324 #define CONFIG_SYS_NS16550_SERIAL
325 #define CONFIG_SYS_NS16550_REG_SIZE 1
326 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
327 #ifdef CONFIG_NAND_SPL
328 #define CONFIG_NS16550_MIN_FUNCTIONS
331 #define CONFIG_SYS_CONSOLE_IS_IN_ENV /* determine from environment */
333 #define CONFIG_SYS_BAUDRATE_TABLE \
334 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
336 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
337 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
339 /* Use the HUSH parser */
340 #define CONFIG_SYS_HUSH_PARSER
343 * Pass open firmware flat tree
345 #define CONFIG_OF_LIBFDT 1
346 #define CONFIG_OF_BOARD_SETUP 1
347 #define CONFIG_OF_STDOUT_VIA_ALIAS 1
349 /* new uImage format support */
351 #define CONFIG_FIT_VERBOSE 1 /* enable fit_format_{error,warning}() */
354 #define CONFIG_FSL_I2C /* Use FSL common I2C driver */
355 #define CONFIG_HARD_I2C /* I2C with hardware support */
356 #undef CONFIG_SOFT_I2C /* I2C bit-banged */
357 #define CONFIG_I2C_MULTI_BUS
358 #define CONFIG_I2C_CMD_TREE
359 #define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address*/
360 #define CONFIG_SYS_I2C_SLAVE 0x7F
361 #define CONFIG_SYS_I2C_NOPROBES {{0,0x29}} /* Don't probe these addrs */
362 #define CONFIG_SYS_I2C_OFFSET 0x3000
363 #define CONFIG_SYS_I2C2_OFFSET 0x3100
368 #define CONFIG_ID_EEPROM
369 #ifdef CONFIG_ID_EEPROM
370 #define CONFIG_SYS_I2C_EEPROM_NXID
372 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x52
373 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
374 #define CONFIG_SYS_EEPROM_BUS_NUM 1
376 #define CONFIG_SYS_I2C_PCA9557_ADDR 0x18
378 #define CONFIG_RTC_DS1337
379 #define CONFIG_SYS_RTC_DS1337_NOOSC
380 #define CONFIG_SYS_I2C_RTC_ADDR 0x68
382 /* eSPI - Enhanced SPI */
383 #define CONFIG_FSL_ESPI
384 #define CONFIG_SPI_FLASH
385 #define CONFIG_SPI_FLASH_SPANSION
386 #define CONFIG_CMD_SF
387 #define CONFIG_SF_DEFAULT_SPEED 10000000
388 #define CONFIG_SF_DEFAULT_MODE SPI_MODE_0
392 * Memory space is mapped 1-1, but I/O space must start from 0.
395 #if defined(CONFIG_PCI)
396 /* controller 2, Slot 2, tgtid 2, Base address 9000 */
397 #define CONFIG_SYS_PCIE2_NAME "Slot 1"
398 #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000
399 #ifdef CONFIG_PHYS_64BIT
400 #define CONFIG_SYS_PCIE2_MEM_BUS 0xc0000000
401 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull
403 #define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000
404 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000
406 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */
407 #define CONFIG_SYS_PCIE2_IO_VIRT 0xffc10000
408 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
409 #ifdef CONFIG_PHYS_64BIT
410 #define CONFIG_SYS_PCIE2_IO_PHYS 0xfffc10000ull
412 #define CONFIG_SYS_PCIE2_IO_PHYS 0xffc10000
414 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */
416 /* controller 1, Slot 1, tgtid 1, Base address a000 */
417 #define CONFIG_SYS_PCIE1_NAME "Slot 2"
418 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000
419 #ifdef CONFIG_PHYS_64BIT
420 #define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000
421 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull
423 #define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000
424 #define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000
426 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */
427 #define CONFIG_SYS_PCIE1_IO_VIRT 0xffc00000
428 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
429 #ifdef CONFIG_PHYS_64BIT
430 #define CONFIG_SYS_PCIE1_IO_PHYS 0xfffc00000ull
432 #define CONFIG_SYS_PCIE1_IO_PHYS 0xffc00000
434 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
436 #define CONFIG_PCI_PNP /* do pci plug-and-play */
438 #undef CONFIG_EEPRO100
440 #undef CONFIG_RTL8139
442 #ifdef CONFIG_RTL8139
443 /* This macro is used by RTL8139 but not defined in PPC architecture */
444 #define KSEG1ADDR(x) (x)
445 #define _IO_BASE 0x00000000
449 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
450 #define CONFIG_DOS_PARTITION
452 #endif /* CONFIG_PCI */
455 #if defined(CONFIG_TSEC_ENET)
456 #define CONFIG_MII 1 /* MII PHY management */
457 #define CONFIG_MII_DEFAULT_TSEC 1 /* Allow unregistered phys */
458 #define CONFIG_TSEC1 1
459 #define CONFIG_TSEC1_NAME "eTSEC1"
460 #define CONFIG_TSEC2 1
461 #define CONFIG_TSEC2_NAME "eTSEC2"
462 #define CONFIG_TSEC3 1
463 #define CONFIG_TSEC3_NAME "eTSEC3"
465 #define TSEC1_PHY_ADDR 2
466 #define TSEC2_PHY_ADDR 0
467 #define TSEC3_PHY_ADDR 1
469 #define CONFIG_VSC7385_ENET
471 #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
472 #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
473 #define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
475 #define TSEC1_PHYIDX 0
476 #define TSEC2_PHYIDX 0
477 #define TSEC3_PHYIDX 0
481 #ifdef CONFIG_VSC7385_ENET
482 /* The size of the VSC7385 firmware image */
483 #define CONFIG_VSC7385_IMAGE_SIZE 8192
486 #define CONFIG_ETHPRIME "eTSEC1"
488 #define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */
490 #endif /* CONFIG_TSEC_ENET */
495 #if defined(CONFIG_SYS_RAMBOOT)
496 #if defined(CONFIG_RAMBOOT_NAND)
497 #define CONFIG_ENV_IS_IN_NAND 1
498 #define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE
499 #define CONFIG_ENV_OFFSET ((512 * 1024) + CONFIG_SYS_NAND_BLOCK_SIZE)
500 #elif defined(CONFIG_RAMBOOT_SDCARD)
501 #define CONFIG_ENV_IS_IN_MMC
502 #define CONFIG_FSL_FIXED_MMC_LOCATION
503 #define CONFIG_ENV_SIZE 0x2000
504 #define CONFIG_SYS_MMC_ENV_DEV 0
505 #elif defined(CONFIG_RAMBOOT_SPIFLASH)
506 #define CONFIG_ENV_IS_IN_SPI_FLASH
507 #define CONFIG_ENV_SPI_BUS 0
508 #define CONFIG_ENV_SPI_CS 0
509 #define CONFIG_ENV_SPI_MAX_HZ 10000000
510 #define CONFIG_ENV_SPI_MODE 0
511 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */
512 #define CONFIG_ENV_SECT_SIZE 0x10000
513 #define CONFIG_ENV_SIZE 0x2000
516 #define CONFIG_ENV_IS_IN_FLASH 1
517 #if CONFIG_SYS_MONITOR_BASE > 0xfff80000
518 #define CONFIG_ENV_ADDR 0xfff80000
520 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
522 #define CONFIG_ENV_SIZE 0x2000
523 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */
526 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
527 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
530 * Command line configuration.
532 #include <config_cmd_default.h>
534 #define CONFIG_CMD_DATE
535 #define CONFIG_CMD_ELF
536 #define CONFIG_CMD_I2C
537 #define CONFIG_CMD_IRQ
538 #define CONFIG_CMD_MII
539 #define CONFIG_CMD_PING
540 #define CONFIG_CMD_SETEXPR
541 #define CONFIG_CMD_REGINFO
543 #if defined(CONFIG_PCI)
544 #define CONFIG_CMD_NET
545 #define CONFIG_CMD_PCI
548 #undef CONFIG_WATCHDOG /* watchdog disabled */
553 #define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */
554 #define CONFIG_CMD_MMC
555 #define CONFIG_DOS_PARTITION
556 #define CONFIG_FSL_ESDHC
557 #define CONFIG_GENERIC_MMC
558 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
560 #define CONFIG_SYS_FSL_ESDHC_USE_PIO /* P2020 eSDHC DMA is not functional*/
564 #define CONFIG_HAS_FSL_DR_USB
566 #if defined(CONFIG_HAS_FSL_DR_USB)
567 #define CONFIG_USB_EHCI
569 #ifdef CONFIG_USB_EHCI
570 #define CONFIG_CMD_USB
571 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
572 #define CONFIG_USB_EHCI_FSL
573 #define CONFIG_USB_STORAGE
577 #if defined(CONFIG_MMC) || defined(CONFIG_USB_EHCI)
578 #define CONFIG_CMD_EXT2
579 #define CONFIG_CMD_FAT
580 #define CONFIG_DOS_PARTITION
584 * Miscellaneous configurable options
586 #define CONFIG_SYS_LONGHELP /* undef to save memory */
587 #define CONFIG_CMDLINE_EDITING /* Command-line editing */
588 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */
589 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
590 #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
591 #if defined(CONFIG_CMD_KGDB)
592 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
594 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
596 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
597 /* Print Buffer Size */
598 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */
599 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */
600 #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */
603 * For booting Linux, the board info and command line data
604 * have to be in the first 64 MB of memory, since this is
605 * the maximum mapped by the Linux kernel during initialization.
607 #define CONFIG_SYS_BOOTMAPSZ (64 << 20)/* Initial Memory map for Linux*/
608 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
610 #if defined(CONFIG_CMD_KGDB)
611 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
612 #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
616 * Environment Configuration
619 #if defined(CONFIG_TSEC_ENET)
620 #define CONFIG_HAS_ETH0
621 #define CONFIG_HAS_ETH1
622 #define CONFIG_HAS_ETH2
625 #define CONFIG_HOSTNAME P2020RDB
626 #define CONFIG_ROOTPATH "/opt/nfsroot"
627 #define CONFIG_BOOTFILE "uImage"
628 #define CONFIG_UBOOTPATH u-boot.bin/* U-Boot image on TFTP server */
630 /* default location for tftp and bootm */
631 #define CONFIG_LOADADDR 1000000
633 #define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */
634 #undef CONFIG_BOOTARGS /* the boot command will set bootargs */
636 #define CONFIG_BAUDRATE 115200
638 #define CONFIG_EXTRA_ENV_SETTINGS \
640 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
641 "loadaddr=1000000\0" \
642 "tftpflash=tftpboot $loadaddr $uboot; " \
643 "protect off " __stringify(CONFIG_SYS_TEXT_BASE) \
645 "erase " __stringify(CONFIG_SYS_TEXT_BASE) \
647 "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \
649 "protect on " __stringify(CONFIG_SYS_TEXT_BASE) \
651 "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \
653 "consoledev=ttyS0\0" \
654 "ramdiskaddr=2000000\0" \
655 "ramdiskfile=rootfs.ext2.gz.uboot\0" \
657 "fdtfile=p2020rdb.dtb\0" \
659 "jffs2nor=mtdblock3\0" \
660 "norbootaddr=ef080000\0" \
661 "norfdtaddr=ef040000\0" \
662 "jffs2nand=mtdblock9\0" \
663 "nandbootaddr=100000\0" \
664 "nandfdtaddr=80000\0" \
665 "nandimgsize=400000\0" \
666 "nandfdtsize=80000\0" \
667 "hwconfig=usb1:dr_mode=host,phy_type=ulpi\0" \
668 "vscfw_addr=ef000000\0" \
669 "othbootargs=ramdisk_size=600000\0" \
670 "usbfatboot=setenv bootargs root=/dev/ram rw " \
671 "console=$consoledev,$baudrate $othbootargs; " \
673 "fatload usb 0:2 $loadaddr $bootfile;" \
674 "fatload usb 0:2 $fdtaddr $fdtfile;" \
675 "fatload usb 0:2 $ramdiskaddr $ramdiskfile;" \
676 "bootm $loadaddr $ramdiskaddr $fdtaddr\0" \
677 "usbext2boot=setenv bootargs root=/dev/ram rw " \
678 "console=$consoledev,$baudrate $othbootargs; " \
680 "ext2load usb 0:4 $loadaddr $bootfile;" \
681 "ext2load usb 0:4 $fdtaddr $fdtfile;" \
682 "ext2load usb 0:4 $ramdiskaddr $ramdiskfile;" \
683 "bootm $loadaddr $ramdiskaddr $fdtaddr\0" \
684 "norboot=setenv bootargs root=/dev/$jffs2nor rw " \
685 "console=$consoledev,$baudrate rootfstype=jffs2 $othbootargs;" \
686 "bootm $norbootaddr - $norfdtaddr\0" \
687 "nandboot=setenv bootargs root=/dev/$jffs2nand rw rootfstype=jffs2 " \
688 "console=$consoledev,$baudrate $othbootargs;" \
689 "nand read 2000000 $nandbootaddr $nandimgsize;" \
690 "nand read 3000000 $nandfdtaddr $nandfdtsize;" \
691 "bootm 2000000 - 3000000;\0"
693 #define CONFIG_NFSBOOTCOMMAND \
694 "setenv bootargs root=/dev/nfs rw " \
695 "nfsroot=$serverip:$rootpath " \
696 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
697 "console=$consoledev,$baudrate $othbootargs;" \
698 "tftp $loadaddr $bootfile;" \
699 "tftp $fdtaddr $fdtfile;" \
700 "bootm $loadaddr - $fdtaddr"
702 #define CONFIG_HDBOOT \
703 "setenv bootargs root=/dev/$bdev rw rootdelay=30 " \
704 "console=$consoledev,$baudrate $othbootargs;" \
706 "ext2load usb 0:1 $loadaddr /boot/$bootfile;" \
707 "ext2load usb 0:1 $fdtaddr /boot/$fdtfile;" \
708 "bootm $loadaddr - $fdtaddr"
710 #define CONFIG_RAMBOOTCOMMAND \
711 "setenv bootargs root=/dev/ram rw " \
712 "console=$consoledev,$baudrate $othbootargs; " \
713 "tftp $ramdiskaddr $ramdiskfile;" \
714 "tftp $loadaddr $bootfile;" \
715 "tftp $fdtaddr $fdtfile;" \
716 "bootm $loadaddr $ramdiskaddr $fdtaddr"
718 #define CONFIG_BOOTCOMMAND CONFIG_HDBOOT
720 #endif /* __CONFIG_H */