2 * Copyright 2009-2010 Freescale Semiconductor, Inc.
4 * See file CREDITS for list of people who contributed to this
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of
10 * the License, or (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
26 /* The P2020COME board is only booted via the Freescale On-Chip ROM */
27 #define CONFIG_SYS_RAMBOOT
28 #define CONFIG_SYS_EXTRA_ENV_RELOC
30 #define CONFIG_SYS_TEXT_BASE 0xf8f80000
31 #define CONFIG_RESET_VECTOR_ADDRESS 0xf8fffffc
34 #define CONFIG_RAMBOOT_SDCARD 1
37 #ifdef CONFIG_SPIFLASH
38 #define CONFIG_RAMBOOT_SPIFLASH 1
41 #ifndef CONFIG_SYS_MONITOR_BASE
42 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
45 /* High Level Configuration Options */
46 #define CONFIG_BOOKE 1 /* BOOKE */
47 #define CONFIG_E500 1 /* BOOKE e500 family */
48 #define CONFIG_MPC85xx 1 /* MPC8540/60/55/41/48/P1020/P2020,etc*/
49 #define CONFIG_P2020 1
50 #define CONFIG_P2020COME 1
51 #define CONFIG_FSL_ELBC 1 /* Enable eLBC Support */
54 #define CONFIG_PCI 1 /* Enable PCI/PCIE */
55 #if defined(CONFIG_PCI)
56 #define CONFIG_PCIE1 1 /* PCIE controller 1 (slot 1) */
57 #define CONFIG_PCIE2 1 /* PCIE controller 2 (slot 2) */
58 #define CONFIG_PCIE3 1 /* PCIE controller 3 (slot 3) */
60 #define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */
61 #define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */
62 #define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */
63 #endif /* #if defined(CONFIG_PCI) */
64 #define CONFIG_FSL_LAW 1 /* Use common FSL init code */
65 #define CONFIG_TSEC_ENET /* tsec ethernet support */
66 #define CONFIG_ENV_OVERWRITE
68 #if defined(CONFIG_PCI)
69 #define CONFIG_E1000 1 /* E1000 pci Ethernet card */
73 extern unsigned long get_board_ddr_clk(unsigned long dummy);
74 extern unsigned long get_board_sys_clk(unsigned long dummy);
78 * For P2020COME DDRCLK and SYSCLK are from the same oscillator
79 * For DA phase the SYSCLK is 66MHz
80 * For EA phase the SYSCLK is 100MHz
82 #define CONFIG_DDR_CLK_FREQ get_board_ddr_clk(0)
83 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk(0)
85 #define CONFIG_HWCONFIG
88 * These can be toggled for performance analysis, otherwise use default.
90 #define CONFIG_L2_CACHE /* toggle L2 cache */
91 #define CONFIG_BTB /* toggle branch prediction */
93 #define CONFIG_ADDR_STREAMING /* toggle addr streaming */
95 #define CONFIG_ENABLE_36BIT_PHYS 1
97 #ifdef CONFIG_PHYS_64BIT
98 #define CONFIG_ADDR_MAP 1
99 #define CONFIG_SYS_NUM_ADDR_MAP 16 /* number of TLB1 entries */
102 #define CONFIG_SYS_MEMTEST_START 0x00000000 /* memtest works on */
103 #define CONFIG_SYS_MEMTEST_END 0x1fffffff
104 #define CONFIG_PANIC_HANG /* do not reset board on panic */
113 * Config the L2 Cache as L2 SRAM
115 #define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000
116 #ifdef CONFIG_PHYS_64BIT
117 #define CONFIG_SYS_INIT_L2_ADDR_PHYS 0xff8f80000ull
119 #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR
121 #define CONFIG_SYS_L2_SIZE (512 << 10)
122 #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR \
123 + CONFIG_SYS_L2_SIZE)
125 #define CONFIG_SYS_CCSRBAR 0xffe00000
126 #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
129 #define CONFIG_FSL_DDR3
130 #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */
131 #define CONFIG_DDR_SPD
133 #define CONFIG_DDR_ECC
134 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
135 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef
137 #define CONFIG_SYS_SDRAM_SIZE 2048ULL /* DDR size on P2020COME */
138 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
139 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
141 #define CONFIG_NUM_DDR_CONTROLLERS 1
142 #define CONFIG_DIMM_SLOTS_PER_CTLR 1
143 #define CONFIG_CHIP_SELECTS_PER_CTRL 2
145 #define CONFIG_SYS_DDR_ERR_INT_EN 0x0000000d
146 #define CONFIG_SYS_DDR_ERR_DIS 0x00000000
147 #define CONFIG_SYS_DDR_SBE 0x00ff0000
149 #define CONFIG_SYS_SPD_BUS_NUM 1
150 #define SPD_EEPROM_ADDRESS 0x53
155 * 0x0000_0000 0x7fff_ffff DDR3 2G Cacheable
156 * 0x8000_0000 0x9fff_ffff PCI Express 3 Mem 1G non-cacheable
157 * 0xa000_0000 0xbfff_ffff PCI Express 2 Mem 1G non-cacheable
158 * 0xc000_0000 0xdfff_ffff PCI Express 1 Mem 1G non-cacheable
159 * 0xffc1_0000 0xffc1_ffff PCI Express 3 IO 64K non-cacheable
160 * 0xffc2_0000 0xffc2_ffff PCI Express 2 IO 64K non-cacheable
161 * 0xffc3_0000 0xffc3_ffff PCI Express 1 IO 64K non-cacheable
163 * 0xffd0_0000 0xffd0_3fff L1 for stack 16K Cacheable TLB0
164 * 0xffe0_0000 0xffef_ffff CCSR 1M non-cacheable
168 * Local Bus Definitions
171 /* There is no NOR Flash on P2020COME */
172 #define CONFIG_SYS_NO_FLASH
174 #define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */
175 #define CONFIG_HWCONFIG
177 #define CONFIG_SYS_INIT_RAM_LOCK 1
178 #define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* stack in RAM */
179 #ifdef CONFIG_PHYS_64BIT
180 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
181 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR
182 /* the assembler doesn't like typecast */
183 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
184 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
185 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
187 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS CONFIG_SYS_INIT_RAM_ADDR
188 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0
189 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS
191 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000
193 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE \
194 - GENERATED_GBL_DATA_SIZE)
195 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
197 #define CONFIG_SYS_MONITOR_LEN (256 * 1024)
198 #define CONFIG_SYS_MALLOC_LEN (1024 * 1024)
200 /* Serial Port - controlled on board with jumper J8
204 #define CONFIG_CONS_INDEX 1
205 #define CONFIG_SYS_NS16550
206 #define CONFIG_SYS_NS16550_SERIAL
207 #define CONFIG_SYS_NS16550_REG_SIZE 1
208 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
210 #define CONFIG_SERIAL_MULTI 1 /* Enable both serial ports */
211 #define CONFIG_SYS_CONSOLE_IS_IN_ENV /* determine from environment */
213 #define CONFIG_SYS_BAUDRATE_TABLE \
214 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
216 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
217 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
219 /* Use the HUSH parser */
220 #define CONFIG_SYS_HUSH_PARSER
221 #ifdef CONFIG_SYS_HUSH_PARSER
222 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
226 * Pass open firmware flat tree
228 #define CONFIG_OF_LIBFDT 1
229 #define CONFIG_OF_BOARD_SETUP 1
230 #define CONFIG_OF_STDOUT_VIA_ALIAS 1
232 /* new uImage format support */
234 #define CONFIG_FIT_VERBOSE 1
237 #define CONFIG_FSL_I2C /* Use FSL common I2C driver */
238 #define CONFIG_HARD_I2C /* I2C with hardware support */
239 #undef CONFIG_SOFT_I2C /* I2C bit-banged */
240 #define CONFIG_I2C_MULTI_BUS
241 #define CONFIG_I2C_CMD_TREE
242 #define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address*/
243 #define CONFIG_SYS_I2C_SLAVE 0x7F
244 #define CONFIG_SYS_I2C_NOPROBES { {0, 0x29} }
245 #define CONFIG_SYS_I2C_OFFSET 0x3000
246 #define CONFIG_SYS_I2C2_OFFSET 0x3100
251 #define CONFIG_ID_EEPROM
252 #ifdef CONFIG_ID_EEPROM
253 #define CONFIG_SYS_I2C_EEPROM_NXID
255 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50
256 #define CONFIG_SYS_I2C_EEPROM_ADDR2 0x18
257 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
258 #define CONFIG_SYS_EEPROM_BUS_NUM 0
259 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */
262 * eSPI - Enhanced SPI
264 #define CONFIG_FSL_ESPI
265 #define CONFIG_SPI_FLASH
266 #define CONFIG_SPI_FLASH_STMICRO
267 #define CONFIG_CMD_SF
268 #define CONFIG_SF_DEFAULT_SPEED 10000000
269 #define CONFIG_SF_DEFAULT_MODE SPI_MODE_0
273 * Memory space is mapped 1-1, but I/O space must start from 0.
275 #if defined(CONFIG_PCI)
277 /* controller 3, Slot 3, tgtid 3, Base address 8000 */
278 #define CONFIG_SYS_PCIE3_MEM_VIRT 0x80000000
279 #define CONFIG_SYS_PCIE3_MEM_BUS 0x80000000
280 #define CONFIG_SYS_PCIE3_MEM_PHYS 0x80000000
281 #define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */
282 #define CONFIG_SYS_PCIE3_IO_VIRT 0xffc10000
283 #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000
284 #define CONFIG_SYS_PCIE3_IO_PHYS 0xffc10000
285 #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */
287 /* controller 2, Slot 2, tgtid 2, Base address 9000 */
288 #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000
289 #define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000
290 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000
291 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */
292 #define CONFIG_SYS_PCIE2_IO_VIRT 0xffc20000
293 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
294 #define CONFIG_SYS_PCIE2_IO_PHYS 0xffc20000
295 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */
297 /* controller 1, Slot 1, tgtid 1, Base address a000 */
298 #define CONFIG_SYS_PCIE1_MEM_VIRT 0xc0000000
299 #define CONFIG_SYS_PCIE1_MEM_BUS 0xc0000000
300 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc0000000
301 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */
302 #define CONFIG_SYS_PCIE1_IO_VIRT 0xffc30000
303 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
304 #define CONFIG_SYS_PCIE1_IO_PHYS 0xffc30000
305 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
307 #define CONFIG_PCI_PNP /* do pci plug-and-play */
309 #undef CONFIG_EEPRO100
311 #undef CONFIG_RTL8139
313 #ifdef CONFIG_RTL8139
314 /* This macro is used by RTL8139 but not defined in PPC architecture */
315 #define KSEG1ADDR(x) (x)
316 #define _IO_BASE 0x00000000
320 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
321 #define CONFIG_DOS_PARTITION
323 #endif /* CONFIG_PCI */
325 #if defined(CONFIG_TSEC_ENET)
326 #define CONFIG_MII 1 /* MII PHY management */
327 #define CONFIG_MII_DEFAULT_TSEC 1 /* Allow unregistered phys */
328 #define CONFIG_TSEC1 1
329 #define CONFIG_TSEC1_NAME "eTSEC1"
330 #define CONFIG_TSEC2 1
331 #define CONFIG_TSEC2_NAME "eTSEC2"
332 #define CONFIG_TSEC3 1
333 #define CONFIG_TSEC3_NAME "eTSEC3"
335 #define TSEC1_PHY_ADDR 0
336 #define TSEC2_PHY_ADDR 2
337 #define TSEC3_PHY_ADDR 1
339 #undef CONFIG_VSC7385_ENET
341 #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
342 #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
343 #define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
345 #define TSEC1_PHYIDX 0
346 #define TSEC2_PHYIDX 0
347 #define TSEC3_PHYIDX 0
349 #define CONFIG_ETHPRIME "eTSEC1"
351 #define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */
353 #endif /* CONFIG_TSEC_ENET */
358 #if defined(CONFIG_RAMBOOT_SDCARD)
359 #define CONFIG_ENV_IS_IN_MMC 1
360 #define CONFIG_ENV_SIZE 0x2000
361 #define CONFIG_SYS_MMC_ENV_DEV 0
362 #elif defined(CONFIG_RAMBOOT_SPIFLASH)
363 #define CONFIG_ENV_IS_IN_SPI_FLASH
364 #define CONFIG_ENV_SPI_BUS 0
365 #define CONFIG_ENV_SPI_CS 0
366 #define CONFIG_ENV_SPI_MAX_HZ 10000000
367 #define CONFIG_ENV_SPI_MODE 0
368 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */
369 #define CONFIG_ENV_SECT_SIZE 0x10000
370 #define CONFIG_ENV_SIZE 0x2000
373 #define CONFIG_LOADS_ECHO 1
374 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1
377 * Command line configuration.
379 #include <config_cmd_default.h>
381 #define CONFIG_CMD_ELF
382 #define CONFIG_CMD_I2C
383 #define CONFIG_CMD_IRQ
384 #define CONFIG_CMD_MII
385 #define CONFIG_CMD_PING
386 #define CONFIG_CMD_SETEXPR
387 #define CONFIG_CMD_REGINFO
389 #if defined(CONFIG_PCI)
390 #define CONFIG_CMD_NET
391 #define CONFIG_CMD_PCI
394 #undef CONFIG_WATCHDOG /* watchdog disabled */
399 #define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */
400 #define CONFIG_CMD_MMC
401 #define CONFIG_DOS_PARTITION
402 #define CONFIG_FSL_ESDHC
403 #define CONFIG_GENERIC_MMC
404 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
405 #define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT
406 #endif /* CONFIG_MMC */
408 #define CONFIG_USB_EHCI
410 #ifdef CONFIG_USB_EHCI
411 #define CONFIG_CMD_USB
412 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
413 #define CONFIG_USB_EHCI_FSL
414 #define CONFIG_USB_STORAGE
415 #define CONFIG_HAS_FSL_DR_USB
418 #if defined(CONFIG_MMC) || defined(CONFIG_USB_EHCI)
419 #define CONFIG_CMD_EXT2
420 #define CONFIG_CMD_FAT
421 #define CONFIG_DOS_PARTITION
424 /* Misc Extra Settings */
425 #define CONFIG_SYS_64BIT_VSPRINTF 1
426 #define CONFIG_SYS_64BIT_STRTOUL 1
427 #define CONFIG_CMD_DHCP 1
429 #define CONFIG_CMD_DATE 1
430 #define CONFIG_RTC_M41T62 1
431 #define CONFIG_SYS_RTC_BUS_NUM 1
432 #define CONFIG_SYS_I2C_RTC_ADDR 0x68
435 * Miscellaneous configurable options
437 #define CONFIG_SYS_LONGHELP /* undef to save memory */
438 #define CONFIG_CMDLINE_EDITING /* Command-line editing */
439 #define CONFIG_AUTO_COMPLETE 1 /* add autocompletion support */
440 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
441 #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
442 #if defined(CONFIG_CMD_KGDB)
443 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
445 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
447 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
448 /* Print Buffer Size */
449 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */
450 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */
451 #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms tick */
454 * For booting Linux, the board info and command line data
455 * have to be in the first 64 MB of memory, since this is
456 * the maximum mapped by the Linux kernel during initialization.
458 #define CONFIG_SYS_BOOTMAPSZ (64 << 20)
459 #define CONFIG_SYS_BOOTM_LEN (64 << 20)
461 #if defined(CONFIG_CMD_KGDB)
462 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
463 #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
467 * Environment Configuration
470 /* The mac addresses for all ethernet interface */
471 #if defined(CONFIG_TSEC_ENET)
472 #define CONFIG_HAS_ETH0
473 #define CONFIG_HAS_ETH1
474 #define CONFIG_HAS_ETH2
475 #define CONFIG_HAS_ETH3
478 #define CONFIG_HOSTNAME unknown
479 #define CONFIG_ROOTPATH "/opt/nfsroot"
480 #define CONFIG_BOOTFILE "uImage"
481 #define CONFIG_UBOOTPATH u-boot.bin
483 /* default location for tftp and bootm */
484 #define CONFIG_LOADADDR 1000000
486 #define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */
487 #undef CONFIG_BOOTARGS /* the boot command will set bootargs */
489 #define CONFIG_BAUDRATE 115200
491 #define CONFIG_EXTRA_ENV_SETTINGS \
492 "hwconfig=fsl_ddr:ecc=on\0" \
493 "bootcmd=run sdboot\0" \
494 "sdboot=setenv bootargs root=/dev/mmcblk0p2 rw " \
495 "rootdelay=$rootdelaysecond console=$consoledev,$baudrate "\
496 "$othbootargs; mmcinfo; " \
497 "ext2load mmc 0:2 $loadaddr /boot/$bootfile; " \
498 "ext2load mmc 0:2 $fdtaddr /boot/$fdtfile; " \
499 "bootm $loadaddr - $fdtaddr\0" \
500 "sdfatboot=setenv bootargs root=/dev/ram rw " \
501 "rootdelay=$rootdelaysecond console=$consoledev,$baudrate "\
502 "$othbootargs; mmcinfo; " \
503 "fatload mmc 0:1 $loadaddr $bootfile; " \
504 "fatload mmc 0:1 $fdtaddr $fdtfile; " \
505 "fatload mmc 0:1 $ramdiskaddr $ramdiskfile; " \
506 "bootm $loadaddr $ramdiskaddr $fdtaddr\0" \
507 "usbboot=setenv bootargs root=/dev/sda1 rw " \
508 "rootdelay=$rootdelaysecond console=$consoledev,$baudrate "\
511 "ext2load usb 0:1 $loadaddr /boot/$bootfile; " \
512 "ext2load usb 0:1 $fdtaddr /boot/$fdtfile; " \
513 "bootm $loadaddr - $fdtaddr\0" \
514 "usbfatboot=setenv bootargs root=/dev/ram rw " \
515 "console=$consoledev,$baudrate $othbootargs; " \
517 "fatload usb 0:2 $loadaddr $bootfile; " \
518 "fatload usb 0:2 $fdtaddr $fdtfile; " \
519 "fatload usb 0:2 $ramdiskaddr $ramdiskfile; " \
520 "bootm $loadaddr $ramdiskaddr $fdtaddr\0" \
521 "usbext2boot=setenv bootargs root=/dev/ram rw " \
522 "console=$consoledev,$baudrate $othbootargs; " \
524 "ext2load usb 0:4 $loadaddr $bootfile; " \
525 "ext2load usb 0:4 $fdtaddr $fdtfile; " \
526 "ext2load usb 0:4 $ramdiskaddr $ramdiskfile; " \
527 "bootm $loadaddr $ramdiskaddr $fdtaddr\0" \
528 "upgradespi=sf probe 0; " \
529 "setenv startaddr 0; " \
530 "setenv erasesize a0000; " \
531 "tftp 1000000 $tftppath/$uboot_spi; " \
532 "sf erase $startaddr $erasesize; " \
533 "sf write 1000000 $startaddr $filesize; " \
534 "sf erase 100000 120000\0" \
535 "clearspienv=sf probe 0;sf erase 100000 20000\0" \
536 "othbootargs=ramdisk_size=700000 cache-sram-size=0x10000\0" \
538 "rootdelaysecond=15\0" \
539 "uboot_nor=u-boot-nor.bin\0" \
540 "uboot_spi=u-boot-p2020.spi\0" \
541 "uboot_sd=u-boot-p2020.bin\0" \
542 "consoledev=ttyS0\0" \
543 "ramdiskaddr=2000000\0" \
544 "ramdiskfile=rootfs-dev.ext2.img\0" \
546 "fdtfile=uImage-2.6.32-p2020.dtb\0" \
549 #define CONFIG_HDBOOT \
550 "setenv bootargs root=/dev/$bdev rw rootdelay=30 " \
551 "console=$consoledev,$baudrate $othbootargs;" \
553 "ext2load usb 0:1 $loadaddr /boot/$bootfile;" \
554 "ext2load usb 0:1 $fdtaddr /boot/$fdtfile;" \
555 "bootm $loadaddr - $fdtaddr"
557 #define CONFIG_NFSBOOTCOMMAND \
558 "setenv bootargs root=/dev/nfs rw " \
559 "nfsroot=$serverip:$rootpath " \
560 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off "\
561 "console=$consoledev,$baudrate $othbootargs;" \
562 "tftp $loadaddr $tftppath/$bootfile;" \
563 "tftp $fdtaddr $tftppath/$fdtfile;" \
564 "bootm $loadaddr - $fdtaddr"
566 #define CONFIG_RAMBOOTCOMMAND \
567 "setenv bootargs root=/dev/ram rw " \
568 "console=$consoledev,$baudrate $othbootargs;" \
569 "tftp $ramdiskaddr $tftppath/$ramdiskfile;" \
570 "tftp $loadaddr $tftppath/$bootfile;" \
571 "tftp $fdtaddr $tftppath/$fdtfile;" \
572 "bootm $loadaddr $ramdiskaddr $fdtaddr"
574 #define CONFIG_BOOTCOMMAND CONFIG_HDBOOT
576 #endif /* __CONFIG_H */