2 * Copyright 2007-2011 Freescale Semiconductor, Inc.
4 * See file CREDITS for list of people who contributed to this
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of
10 * the License, or (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
24 * p2020ds board configuration file
30 #include "../board/freescale/common/ics307_clk.h"
33 #define CONFIG_PHYS_64BIT
36 /* High Level Configuration Options */
37 #define CONFIG_BOOKE 1 /* BOOKE */
38 #define CONFIG_E500 1 /* BOOKE e500 family */
39 #define CONFIG_MPC85xx 1 /* MPC8540/60/55/41/48 */
40 #define CONFIG_P2020 1
41 #define CONFIG_P2020DS 1
42 #define CONFIG_MP 1 /* support multiple processors */
44 #ifndef CONFIG_SYS_TEXT_BASE
45 #define CONFIG_SYS_TEXT_BASE 0xeff80000
48 #define CONFIG_SYS_SRIO
49 #define CONFIG_SRIO1 /* SRIO port 1 */
50 #define CONFIG_SRIO2 /* SRIO port 2 */
52 #define CONFIG_FSL_ELBC 1 /* Has Enhanced localbus controller */
53 #define CONFIG_PCI 1 /* Enable PCI/PCIE */
54 #define CONFIG_PCIE1 1 /* PCIE controler 1 (slot 1) */
55 #define CONFIG_PCIE2 1 /* PCIE controler 2 (slot 2) */
56 #define CONFIG_PCIE3 1 /* PCIE controler 3 (ULI bridge) */
57 #define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */
58 #define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */
59 #define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */
61 #define CONFIG_FSL_LAW 1 /* Use common FSL init code */
62 #define CONFIG_E1000 1 /* Defind e1000 pci Ethernet card*/
64 #define CONFIG_TSEC_ENET /* tsec ethernet support */
65 #define CONFIG_ENV_OVERWRITE
67 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk() /* sysclk for MPC85xx */
68 #define CONFIG_DDR_CLK_FREQ get_board_ddr_clk() /* ddrclk for MPC85xx */
69 #define CONFIG_ICS307_REFCLK_HZ 33333000 /* ICS307 clock chip ref freq */
72 * These can be toggled for performance analysis, otherwise use default.
74 #define CONFIG_L2_CACHE /* toggle L2 cache */
75 #define CONFIG_BTB /* toggle branch predition */
77 #define CONFIG_ENABLE_36BIT_PHYS 1
79 #ifdef CONFIG_PHYS_64BIT
80 #define CONFIG_ADDR_MAP 1
81 #define CONFIG_SYS_NUM_ADDR_MAP 16 /* number of TLB1 entries */
84 #define CONFIG_POST CONFIG_SYS_POST_MEMORY /* test POST memory test */
85 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */
86 #define CONFIG_SYS_MEMTEST_END 0x00400000
87 #define CONFIG_PANIC_HANG /* do not reset board on panic */
90 * Base addresses -- Note these are effective addresses where the
91 * actual resources get mapped (not physical addresses)
93 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */
94 #define CONFIG_SYS_CCSRBAR 0xffe00000 /* relocated CCSRBAR */
95 #ifdef CONFIG_PHYS_64BIT
96 #define CONFIG_SYS_CCSRBAR_PHYS 0xfffe00000ull /* physical addr of CCSRBAR */
98 #define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR /* physical addr of CCSRBAR */
100 #define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR /* PQII uses CONFIG_SYS_IMMR */
103 #define CONFIG_VERY_BIG_RAM
105 #define CONFIG_FSL_DDR2
107 #define CONFIG_FSL_DDR3 1
109 #undef CONFIG_FSL_DDR_INTERACTIVE
111 /* ECC will be enabled based on perf_mode environment variable */
112 /* #define CONFIG_DDR_ECC */
114 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
115 #define CONFIG_MEM_INIT_VALUE 0xDeadBeef
117 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
118 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
120 #define CONFIG_NUM_DDR_CONTROLLERS 1
121 #define CONFIG_DIMM_SLOTS_PER_CTLR 1
122 #define CONFIG_CHIP_SELECTS_PER_CTRL 2
124 /* I2C addresses of SPD EEPROMs */
125 #define CONFIG_DDR_SPD
126 #define CONFIG_SYS_SPD_BUS_NUM 0 /* SPD EEPROM located on I2C bus 0 */
127 #define SPD_EEPROM_ADDRESS1 0x51 /* CTLR 0 DIMM 0 */
129 /* These are used when DDR doesn't use SPD. */
130 #define CONFIG_SYS_SDRAM_SIZE 1024 /* DDR is 1GB */
132 /* Default settings for "stable" mode */
133 #define CONFIG_SYS_DDR_CS0_BNDS 0x0000003F
134 #define CONFIG_SYS_DDR_CS1_BNDS 0x00000000
135 #define CONFIG_SYS_DDR_CS0_CONFIG 0x80014202
136 #define CONFIG_SYS_DDR_CS1_CONFIG 0x00000000
137 #define CONFIG_SYS_DDR_TIMING_3 0x00020000
138 #define CONFIG_SYS_DDR_TIMING_0 0x00330804
139 #define CONFIG_SYS_DDR_TIMING_1 0x6f6b4846
140 #define CONFIG_SYS_DDR_TIMING_2 0x0fa890d4
141 #define CONFIG_SYS_DDR_MODE_1 0x00421422
142 #define CONFIG_SYS_DDR_MODE_2 0x00000000
143 #define CONFIG_SYS_DDR_MODE_CTRL 0x00000000
144 #define CONFIG_SYS_DDR_INTERVAL 0x61800100
145 #define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef
146 #define CONFIG_SYS_DDR_CLK_CTRL 0x02000000
147 #define CONFIG_SYS_DDR_TIMING_4 0x00220001
148 #define CONFIG_SYS_DDR_TIMING_5 0x03402400
149 #define CONFIG_SYS_DDR_ZQ_CNTL 0x89080600
150 #define CONFIG_SYS_DDR_WRLVL_CNTL 0x8655A608
151 #define CONFIG_SYS_DDR_CONTROL 0xE7000000 /* Type = DDR3: ECC enabled, No Interleaving */
152 #define CONFIG_SYS_DDR_CONTROL2 0x24400011
153 #define CONFIG_SYS_DDR_CDR1 0x00040000
154 #define CONFIG_SYS_DDR_CDR2 0x00000000
156 #define CONFIG_SYS_DDR_ERR_INT_EN 0x0000000d
157 #define CONFIG_SYS_DDR_ERR_DIS 0x00000000
158 #define CONFIG_SYS_DDR_SBE 0x00010000
160 /* Settings that differ for "performance" mode */
161 #define CONFIG_SYS_DDR_CS0_BNDS_PERF 0x0000007F /* Interleaving Enabled */
162 #define CONFIG_SYS_DDR_CS1_BNDS_PERF 0x00000000 /* Interleaving Enabled */
163 #define CONFIG_SYS_DDR_CS1_CONFIG_PERF 0x80014202
164 #define CONFIG_SYS_DDR_TIMING_1_PERF 0x5d5b4543
165 #define CONFIG_SYS_DDR_TIMING_2_PERF 0x0fa890ce
166 #define CONFIG_SYS_DDR_CONTROL_PERF 0xC7004000 /* Type = DDR3: ECC disabled, cs0-cs1 interleaving */
169 * The following set of values were tested for DDR2
170 * with a DDR3 to DDR2 interposer
172 #define CONFIG_SYS_DDR_TIMING_3 0x00000000
173 #define CONFIG_SYS_DDR_TIMING_0 0x00260802
174 #define CONFIG_SYS_DDR_TIMING_1 0x3935d322
175 #define CONFIG_SYS_DDR_TIMING_2 0x14904cc8
176 #define CONFIG_SYS_DDR_MODE_1 0x00480432
177 #define CONFIG_SYS_DDR_MODE_2 0x00000000
178 #define CONFIG_SYS_DDR_INTERVAL 0x06180100
179 #define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef
180 #define CONFIG_SYS_DDR_CLK_CTRL 0x03800000
181 #define CONFIG_SYS_DDR_OCD_CTRL 0x00000000
182 #define CONFIG_SYS_DDR_OCD_STATUS 0x00000000
183 #define CONFIG_SYS_DDR_CONTROL 0xC3008000
184 #define CONFIG_SYS_DDR_CONTROL2 0x04400010
188 #undef CONFIG_CLOCKS_IN_MHZ
193 * 0x0000_0000 0x7fff_ffff DDR 2G Cacheable
194 * 0x8000_0000 0xbfff_ffff PCI Express Mem 1G non-cacheable
195 * 0xc000_0000 0xdfff_ffff PCI 512M non-cacheable
196 * 0xe100_0000 0xe3ff_ffff PCI IO range 4M non-cacheable
198 * Localbus cacheable (TBD)
199 * 0xXXXX_XXXX 0xXXXX_XXXX SRAM YZ M Cacheable
201 * Localbus non-cacheable
202 * 0xe000_0000 0xe80f_ffff Promjet/free 128M non-cacheable
203 * 0xe800_0000 0xefff_ffff FLASH 128M non-cacheable
204 * 0xffa0_0000 0xffaf_ffff NAND 1M non-cacheable
205 * 0xffdf_0000 0xffdf_7fff PIXIS 32K non-cacheable TLB0
206 * 0xffd0_0000 0xffd0_3fff L1 for stack 16K Cacheable TLB0
207 * 0xffe0_0000 0xffef_ffff CCSR 1M non-cacheable
211 * Local Bus Definitions
213 #define CONFIG_SYS_FLASH_BASE 0xe0000000 /* start of FLASH 128M */
214 #ifdef CONFIG_PHYS_64BIT
215 #define CONFIG_SYS_FLASH_BASE_PHYS 0xfe0000000ull
217 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
220 #define CONFIG_FLASH_BR_PRELIM (BR_PHYS_ADDR((CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000)) | BR_PS_16 | BR_V)
221 #define CONFIG_FLASH_OR_PRELIM 0xf8000ff7
223 #define CONFIG_SYS_BR1_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | BR_PS_16 | BR_V)
224 #define CONFIG_SYS_OR1_PRELIM 0xf8000ff7
226 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS}
227 #define CONFIG_SYS_FLASH_QUIET_TEST
228 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
230 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */
231 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
232 #undef CONFIG_SYS_FLASH_CHECKSUM
233 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
234 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
236 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
238 #define CONFIG_FLASH_CFI_DRIVER
239 #define CONFIG_SYS_FLASH_CFI
240 #define CONFIG_SYS_FLASH_EMPTY_INFO
241 #define CONFIG_SYS_FLASH_AMD_CHECK_DQ7
243 #define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */
245 #define CONFIG_HWCONFIG /* enable hwconfig */
246 #define CONFIG_FSL_NGPIXIS /* use common ngPIXIS code */
248 #ifdef CONFIG_FSL_NGPIXIS
249 #define PIXIS_BASE 0xffdf0000 /* PIXIS registers */
250 #ifdef CONFIG_PHYS_64BIT
251 #define PIXIS_BASE_PHYS 0xfffdf0000ull
253 #define PIXIS_BASE_PHYS PIXIS_BASE
256 #define CONFIG_SYS_BR3_PRELIM (BR_PHYS_ADDR(PIXIS_BASE_PHYS) | BR_PS_8 | BR_V)
257 #define CONFIG_SYS_OR3_PRELIM 0xffffeff7 /* 32KB but only 4k mapped */
259 #define PIXIS_LBMAP_SWITCH 7
260 #define PIXIS_LBMAP_MASK 0xf0
261 #define PIXIS_LBMAP_SHIFT 4
262 #define PIXIS_LBMAP_ALTBANK 0x20
265 #define CONFIG_SYS_INIT_RAM_LOCK 1
266 #define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* Initial L1 address */
267 #ifdef CONFIG_PHYS_64BIT
268 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
269 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR
270 /* The assembler doesn't like typecast */
271 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
272 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
273 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
275 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS CONFIG_SYS_INIT_RAM_ADDR /* Initial L1 address */
276 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0
277 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS
279 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 /* Size of used area in RAM */
281 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
282 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
284 #define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */
285 #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */
287 #define CONFIG_SYS_NAND_BASE 0xffa00000
288 #ifdef CONFIG_PHYS_64BIT
289 #define CONFIG_SYS_NAND_BASE_PHYS 0xfffa00000ull
291 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
293 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE,\
294 CONFIG_SYS_NAND_BASE + 0x40000, \
295 CONFIG_SYS_NAND_BASE + 0x80000,\
296 CONFIG_SYS_NAND_BASE + 0xC0000}
297 #define CONFIG_SYS_MAX_NAND_DEVICE 4
298 #define CONFIG_MTD_NAND_VERIFY_WRITE
299 #define CONFIG_CMD_NAND 1
300 #define CONFIG_NAND_FSL_ELBC 1
301 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
303 /* NAND flash config */
304 #define CONFIG_NAND_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
305 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
306 | BR_PS_8 /* Port Size = 8bit */ \
307 | BR_MS_FCM /* MSEL = FCM */ \
309 #define CONFIG_NAND_OR_PRELIM (0xFFFC0000 /* length 256K */ \
310 | OR_FCM_PGS /* Large Page*/ \
318 #define CONFIG_SYS_BR0_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */
319 #define CONFIG_SYS_OR0_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */
320 #define CONFIG_SYS_BR2_PRELIM CONFIG_NAND_BR_PRELIM /* NAND Base Address */
321 #define CONFIG_SYS_OR2_PRELIM CONFIG_NAND_OR_PRELIM /* NAND Options */
323 #define CONFIG_SYS_BR4_PRELIM (BR_PHYS_ADDR((CONFIG_SYS_NAND_BASE_PHYS + 0x40000))\
324 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
325 | BR_PS_8 /* Port Size = 8bit */ \
326 | BR_MS_FCM /* MSEL = FCM */ \
328 #define CONFIG_SYS_OR4_PRELIM CONFIG_NAND_OR_PRELIM /* NAND Options */
329 #define CONFIG_SYS_BR5_PRELIM (BR_PHYS_ADDR((CONFIG_SYS_NAND_BASE_PHYS + 0x80000))\
330 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
331 | BR_PS_8 /* Port Size = 8bit */ \
332 | BR_MS_FCM /* MSEL = FCM */ \
334 #define CONFIG_SYS_OR5_PRELIM CONFIG_NAND_OR_PRELIM /* NAND Options */
336 #define CONFIG_SYS_BR6_PRELIM (BR_PHYS_ADDR((CONFIG_SYS_NAND_BASE_PHYS + 0xc0000))\
337 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
338 | BR_PS_8 /* Port Size = 8bit */ \
339 | BR_MS_FCM /* MSEL = FCM */ \
341 #define CONFIG_SYS_OR6_PRELIM CONFIG_NAND_OR_PRELIM /* NAND Options */
343 /* Serial Port - controlled on board with jumper J8
347 #define CONFIG_CONS_INDEX 1
348 #define CONFIG_SYS_NS16550
349 #define CONFIG_SYS_NS16550_SERIAL
350 #define CONFIG_SYS_NS16550_REG_SIZE 1
351 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
353 #define CONFIG_SYS_BAUDRATE_TABLE \
354 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
356 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
357 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
359 /* Use the HUSH parser */
360 #define CONFIG_SYS_HUSH_PARSER
361 #ifdef CONFIG_SYS_HUSH_PARSER
362 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
366 * Pass open firmware flat tree
368 #define CONFIG_OF_LIBFDT 1
369 #define CONFIG_OF_BOARD_SETUP 1
370 #define CONFIG_OF_STDOUT_VIA_ALIAS 1
373 #define CONFIG_FSL_I2C /* Use FSL common I2C driver */
374 #define CONFIG_HARD_I2C /* I2C with hardware support */
375 #undef CONFIG_SOFT_I2C /* I2C bit-banged */
376 #define CONFIG_I2C_MULTI_BUS
377 #define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */
378 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
379 #define CONFIG_SYS_I2C_SLAVE 0x7F
380 #define CONFIG_SYS_I2C_NOPROBES {{0,0x29}}/* Don't probe these addrs */
381 #define CONFIG_SYS_I2C_OFFSET 0x3000
382 #define CONFIG_SYS_I2C2_OFFSET 0x3100
387 #define CONFIG_ID_EEPROM
388 #ifdef CONFIG_ID_EEPROM
389 #define CONFIG_SYS_I2C_EEPROM_NXID
391 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
392 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
393 #define CONFIG_SYS_EEPROM_BUS_NUM 0
397 * Memory space is mapped 1-1, but I/O space must start from 0.
400 /* controller 3, Slot 1, tgtid 3, Base address b000 */
401 #define CONFIG_SYS_PCIE3_NAME "Slot 1"
402 #define CONFIG_SYS_PCIE3_MEM_VIRT 0x80000000
403 #ifdef CONFIG_PHYS_64BIT
404 #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000
405 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc00000000ull
407 #define CONFIG_SYS_PCIE3_MEM_BUS 0x80000000
408 #define CONFIG_SYS_PCIE3_MEM_PHYS 0x80000000
410 #define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */
411 #define CONFIG_SYS_PCIE3_IO_VIRT 0xffc00000
412 #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000
413 #ifdef CONFIG_PHYS_64BIT
414 #define CONFIG_SYS_PCIE3_IO_PHYS 0xfffc00000ull
416 #define CONFIG_SYS_PCIE3_IO_PHYS 0xffc00000
418 #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */
420 /* controller 2, direct to uli, tgtid 2, Base address 9000 */
421 #define CONFIG_SYS_PCIE2_NAME "ULI"
422 #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000
423 #ifdef CONFIG_PHYS_64BIT
424 #define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000
425 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull
427 #define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000
428 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000
430 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */
431 #define CONFIG_SYS_PCIE2_IO_VIRT 0xffc10000
432 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
433 #ifdef CONFIG_PHYS_64BIT
434 #define CONFIG_SYS_PCIE2_IO_PHYS 0xfffc10000ull
436 #define CONFIG_SYS_PCIE2_IO_PHYS 0xffc10000
438 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */
440 /* controller 1, Slot 2, tgtid 1, Base address a000 */
441 #define CONFIG_SYS_PCIE1_NAME "Slot 2"
442 #define CONFIG_SYS_PCIE1_MEM_VIRT 0xc0000000
443 #ifdef CONFIG_PHYS_64BIT
444 #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000
445 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc40000000ull
447 #define CONFIG_SYS_PCIE1_MEM_BUS 0xc0000000
448 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc0000000
450 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */
451 #define CONFIG_SYS_PCIE1_IO_VIRT 0xffc20000
452 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
453 #ifdef CONFIG_PHYS_64BIT
454 #define CONFIG_SYS_PCIE1_IO_PHYS 0xfffc20000ull
456 #define CONFIG_SYS_PCIE1_IO_PHYS 0xffc20000
458 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
460 #if defined(CONFIG_PCI)
462 /*PCIE video card used*/
463 #define VIDEO_IO_OFFSET CONFIG_SYS_PCIE1_IO_VIRT
468 #if defined(CONFIG_VIDEO)
469 #define CONFIG_BIOSEMU
470 #define CONFIG_CFB_CONSOLE
471 #define CONFIG_VIDEO_SW_CURSOR
472 #define CONFIG_VGA_AS_SINGLE_DEVICE
473 #define CONFIG_ATI_RADEON_FB
474 #define CONFIG_VIDEO_LOGO
475 /*#define CONFIG_CONSOLE_CURSOR*/
476 #define CONFIG_SYS_ISA_IO_BASE_ADDRESS VIDEO_IO_OFFSET
479 /* SRIO1 uses the same window as PCIE2 mem window */
480 #define CONFIG_SYS_SRIO1_MEM_VIRT 0xa0000000
481 #ifdef CONFIG_PHYS_64BIT
482 #define CONFIG_SYS_SRIO1_MEM_PHYS 0xc20000000ull
484 #define CONFIG_SYS_SRIO1_MEM_PHYS 0xa0000000
486 #define CONFIG_SYS_SRIO1_MEM_SIZE 0x20000000 /* 512M */
488 /* SRIO2 uses the same window as PCIE1 mem window */
489 #define CONFIG_SYS_SRIO2_MEM_VIRT 0xc0000000
490 #ifdef CONFIG_PHYS_64BIT
491 #define CONFIG_SYS_SRIO2_MEM_PHYS 0xc40000000ull
493 #define CONFIG_SYS_SRIO2_MEM_PHYS 0xc0000000
495 #define CONFIG_SYS_SRIO2_MEM_SIZE 0x20000000 /* 512M */
497 #define CONFIG_NET_MULTI
498 #define CONFIG_PCI_PNP /* do pci plug-and-play */
500 #undef CONFIG_EEPRO100
502 #define CONFIG_RTL8139
504 #ifndef CONFIG_PCI_PNP
505 #define PCI_ENET0_IOADDR CONFIG_SYS_PCIE3_IO_BUS
506 #define PCI_ENET0_MEMADDR CONFIG_SYS_PCIE3_IO_BUS
507 #define PCI_IDSEL_NUMBER 0x11 /* IDSEL = AD11 */
510 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
511 #define CONFIG_DOS_PARTITION
512 #define CONFIG_SCSI_AHCI
514 #ifdef CONFIG_SCSI_AHCI
515 #define CONFIG_SATA_ULI5288
516 #define CONFIG_SYS_SCSI_MAX_SCSI_ID 4
517 #define CONFIG_SYS_SCSI_MAX_LUN 1
518 #define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * CONFIG_SYS_SCSI_MAX_LUN)
519 #define CONFIG_SYS_SCSI_MAXDEVICE CONFIG_SYS_SCSI_MAX_DEVICE
522 #endif /* CONFIG_PCI */
525 #if defined(CONFIG_TSEC_ENET)
527 #ifndef CONFIG_NET_MULTI
528 #define CONFIG_NET_MULTI 1
531 #define CONFIG_MII 1 /* MII PHY management */
532 #define CONFIG_MII_DEFAULT_TSEC 1 /* Allow unregistered phys */
533 #define CONFIG_TSEC1 1
534 #define CONFIG_TSEC1_NAME "eTSEC1"
535 #define CONFIG_TSEC2 1
536 #define CONFIG_TSEC2_NAME "eTSEC2"
537 #define CONFIG_TSEC3 1
538 #define CONFIG_TSEC3_NAME "eTSEC3"
540 #define CONFIG_PIXIS_SGMII_CMD
541 #define CONFIG_FSL_SGMII_RISER 1
542 #define SGMII_RISER_PHY_OFFSET 0x1b
544 #ifdef CONFIG_FSL_SGMII_RISER
545 #define CONFIG_SYS_TBIPA_VALUE 0x10 /* avoid conflict with eTSEC4 paddr */
548 #define TSEC1_PHY_ADDR 0
549 #define TSEC2_PHY_ADDR 1
550 #define TSEC3_PHY_ADDR 2
552 #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
553 #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
554 #define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
556 #define TSEC1_PHYIDX 0
557 #define TSEC2_PHYIDX 0
558 #define TSEC3_PHYIDX 0
560 #define CONFIG_ETHPRIME "eTSEC1"
562 #define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */
563 #endif /* CONFIG_TSEC_ENET */
568 #define CONFIG_ENV_IS_IN_FLASH 1
569 #if CONFIG_SYS_MONITOR_BASE > 0xfff80000
570 #define CONFIG_ENV_ADDR 0xfff80000
572 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
574 #define CONFIG_ENV_SIZE 0x2000
575 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */
577 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
578 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
581 * Command line configuration.
583 #include <config_cmd_default.h>
585 #define CONFIG_CMD_IRQ
586 #define CONFIG_CMD_PING
587 #define CONFIG_CMD_I2C
588 #define CONFIG_CMD_MII
589 #define CONFIG_CMD_ELF
590 #define CONFIG_CMD_IRQ
591 #define CONFIG_CMD_SETEXPR
592 #define CONFIG_CMD_REGINFO
594 #if defined(CONFIG_PCI)
595 #define CONFIG_CMD_PCI
596 #define CONFIG_CMD_NET
597 #define CONFIG_CMD_SCSI
598 #define CONFIG_CMD_EXT2
604 #define CONFIG_CMD_USB
605 #define CONFIG_USB_STORAGE
606 #define CONFIG_USB_EHCI
607 #define CONFIG_USB_EHCI_FSL
608 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
610 #undef CONFIG_WATCHDOG /* watchdog disabled */
613 * Miscellaneous configurable options
615 #define CONFIG_SYS_LONGHELP /* undef to save memory */
616 #define CONFIG_CMDLINE_EDITING /* Command-line editing */
617 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */
618 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
619 #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
620 #if defined(CONFIG_CMD_KGDB)
621 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
623 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
625 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
626 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */
627 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
628 #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */
631 * For booting Linux, the board info and command line data
632 * have to be in the first 16 MB of memory, since this is
633 * the maximum mapped by the Linux kernel during initialization.
635 #define CONFIG_SYS_BOOTMAPSZ (16 << 20) /* Initial Memory map for Linux*/
637 #if defined(CONFIG_CMD_KGDB)
638 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
639 #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
643 * Environment Configuration
646 /* The mac addresses for all ethernet interface */
647 #if defined(CONFIG_TSEC_ENET)
648 #define CONFIG_HAS_ETH0
649 #define CONFIG_ETHADDR 00:E0:0C:02:00:FD
650 #define CONFIG_HAS_ETH1
651 #define CONFIG_ETH1ADDR 00:E0:0C:02:01:FD
652 #define CONFIG_HAS_ETH2
653 #define CONFIG_ETH2ADDR 00:E0:0C:02:02:FD
654 #define CONFIG_HAS_ETH3
655 #define CONFIG_ETH3ADDR 00:E0:0C:02:03:FD
658 #define CONFIG_IPADDR 192.168.1.254
660 #define CONFIG_HOSTNAME unknown
661 #define CONFIG_ROOTPATH /opt/nfsroot
662 #define CONFIG_BOOTFILE uImage
663 #define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */
665 #define CONFIG_SERVERIP 192.168.1.1
666 #define CONFIG_GATEWAYIP 192.168.1.1
667 #define CONFIG_NETMASK 255.255.255.0
669 /* default location for tftp and bootm */
670 #define CONFIG_LOADADDR 1000000
672 #define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */
673 #undef CONFIG_BOOTARGS /* the boot command will set bootargs */
675 #define CONFIG_BAUDRATE 115200
677 #define CONFIG_EXTRA_ENV_SETTINGS \
678 "perf_mode=stable\0" \
679 "memctl_intlv_ctl=2\0" \
681 "uboot=" MK_STR(CONFIG_UBOOTPATH) "\0" \
682 "tftpflash=tftpboot $loadaddr $uboot; " \
683 "protect off " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
684 "erase " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
685 "cp.b $loadaddr " MK_STR(CONFIG_SYS_TEXT_BASE) " $filesize; " \
686 "protect on " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
687 "cmp.b $loadaddr " MK_STR(CONFIG_SYS_TEXT_BASE) " $filesize\0" \
688 "consoledev=ttyS0\0" \
689 "ramdiskaddr=2000000\0" \
690 "ramdiskfile=p2020ds/ramdisk.uboot\0" \
692 "fdtfile=p2020ds/p2020ds.dtb\0" \
695 #define CONFIG_HDBOOT \
696 "setenv bootargs root=/dev/$bdev rw " \
697 "console=$consoledev,$baudrate $othbootargs;" \
698 "tftp $loadaddr $bootfile;" \
699 "tftp $fdtaddr $fdtfile;" \
700 "bootm $loadaddr - $fdtaddr"
702 #define CONFIG_NFSBOOTCOMMAND \
703 "setenv bootargs root=/dev/nfs rw " \
704 "nfsroot=$serverip:$rootpath " \
705 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
706 "console=$consoledev,$baudrate $othbootargs;" \
707 "tftp $loadaddr $bootfile;" \
708 "tftp $fdtaddr $fdtfile;" \
709 "bootm $loadaddr - $fdtaddr"
711 #define CONFIG_RAMBOOTCOMMAND \
712 "setenv bootargs root=/dev/ram rw " \
713 "console=$consoledev,$baudrate $othbootargs;" \
714 "tftp $ramdiskaddr $ramdiskfile;" \
715 "tftp $loadaddr $bootfile;" \
716 "tftp $fdtaddr $fdtfile;" \
717 "bootm $loadaddr $ramdiskaddr $fdtaddr"
719 #define CONFIG_BOOTCOMMAND CONFIG_HDBOOT
721 #endif /* __CONFIG_H */