2 * Copyright 2007-2010 Freescale Semiconductor, Inc.
4 * See file CREDITS for list of people who contributed to this
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of
10 * the License, or (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
24 * p2020ds board configuration file
30 #include "../board/freescale/common/ics307_clk.h"
33 #define CONFIG_PHYS_64BIT
36 /* High Level Configuration Options */
37 #define CONFIG_BOOKE 1 /* BOOKE */
38 #define CONFIG_E500 1 /* BOOKE e500 family */
39 #define CONFIG_MPC85xx 1 /* MPC8540/60/55/41/48 */
40 #define CONFIG_P2020 1
41 #define CONFIG_P2020DS 1
42 #define CONFIG_MP 1 /* support multiple processors */
44 #ifndef CONFIG_SYS_TEXT_BASE
45 #define CONFIG_SYS_TEXT_BASE 0xeff80000
48 #define CONFIG_FSL_ELBC 1 /* Has Enhanced localbus controller */
49 #define CONFIG_PCI 1 /* Enable PCI/PCIE */
50 #define CONFIG_PCIE1 1 /* PCIE controler 1 (slot 1) */
51 #define CONFIG_PCIE2 1 /* PCIE controler 2 (slot 2) */
52 #define CONFIG_PCIE3 1 /* PCIE controler 3 (ULI bridge) */
53 #define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */
54 #define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */
55 #define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */
57 #define CONFIG_FSL_LAW 1 /* Use common FSL init code */
58 #define CONFIG_E1000 1 /* Defind e1000 pci Ethernet card*/
60 #define CONFIG_TSEC_ENET /* tsec ethernet support */
61 #define CONFIG_ENV_OVERWRITE
63 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk() /* sysclk for MPC85xx */
64 #define CONFIG_DDR_CLK_FREQ get_board_ddr_clk() /* ddrclk for MPC85xx */
65 #define CONFIG_ICS307_REFCLK_HZ 33333000 /* ICS307 clock chip ref freq */
68 * These can be toggled for performance analysis, otherwise use default.
70 #define CONFIG_L2_CACHE /* toggle L2 cache */
71 #define CONFIG_BTB /* toggle branch predition */
73 #define CONFIG_ENABLE_36BIT_PHYS 1
75 #ifdef CONFIG_PHYS_64BIT
76 #define CONFIG_ADDR_MAP 1
77 #define CONFIG_SYS_NUM_ADDR_MAP 16 /* number of TLB1 entries */
80 #define CONFIG_SYS_MEMTEST_START 0x00000000 /* memtest works on */
81 #define CONFIG_SYS_MEMTEST_END 0x7fffffff
82 #define CONFIG_PANIC_HANG /* do not reset board on panic */
85 * Base addresses -- Note these are effective addresses where the
86 * actual resources get mapped (not physical addresses)
88 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */
89 #define CONFIG_SYS_CCSRBAR 0xffe00000 /* relocated CCSRBAR */
90 #ifdef CONFIG_PHYS_64BIT
91 #define CONFIG_SYS_CCSRBAR_PHYS 0xfffe00000ull /* physical addr of CCSRBAR */
93 #define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR /* physical addr of CCSRBAR */
95 #define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR /* PQII uses CONFIG_SYS_IMMR */
98 #define CONFIG_VERY_BIG_RAM
100 #define CONFIG_FSL_DDR2
102 #define CONFIG_FSL_DDR3 1
104 #undef CONFIG_FSL_DDR_INTERACTIVE
106 /* ECC will be enabled based on perf_mode environment variable */
107 /* #define CONFIG_DDR_ECC */
109 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
110 #define CONFIG_MEM_INIT_VALUE 0xDeadBeef
112 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
113 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
115 #define CONFIG_NUM_DDR_CONTROLLERS 1
116 #define CONFIG_DIMM_SLOTS_PER_CTLR 1
117 #define CONFIG_CHIP_SELECTS_PER_CTRL 2
119 /* I2C addresses of SPD EEPROMs */
120 #define CONFIG_DDR_SPD
121 #define CONFIG_SYS_SPD_BUS_NUM 0 /* SPD EEPROM located on I2C bus 0 */
122 #define SPD_EEPROM_ADDRESS1 0x51 /* CTLR 0 DIMM 0 */
124 /* These are used when DDR doesn't use SPD. */
125 #define CONFIG_SYS_SDRAM_SIZE 1024 /* DDR is 1GB */
127 /* Default settings for "stable" mode */
128 #define CONFIG_SYS_DDR_CS0_BNDS 0x0000003F
129 #define CONFIG_SYS_DDR_CS1_BNDS 0x00000000
130 #define CONFIG_SYS_DDR_CS0_CONFIG 0x80014202
131 #define CONFIG_SYS_DDR_CS1_CONFIG 0x00000000
132 #define CONFIG_SYS_DDR_TIMING_3 0x00020000
133 #define CONFIG_SYS_DDR_TIMING_0 0x00330804
134 #define CONFIG_SYS_DDR_TIMING_1 0x6f6b4846
135 #define CONFIG_SYS_DDR_TIMING_2 0x0fa890d4
136 #define CONFIG_SYS_DDR_MODE_1 0x00421422
137 #define CONFIG_SYS_DDR_MODE_2 0x00000000
138 #define CONFIG_SYS_DDR_MODE_CTRL 0x00000000
139 #define CONFIG_SYS_DDR_INTERVAL 0x61800100
140 #define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef
141 #define CONFIG_SYS_DDR_CLK_CTRL 0x02000000
142 #define CONFIG_SYS_DDR_TIMING_4 0x00220001
143 #define CONFIG_SYS_DDR_TIMING_5 0x03402400
144 #define CONFIG_SYS_DDR_ZQ_CNTL 0x89080600
145 #define CONFIG_SYS_DDR_WRLVL_CNTL 0x8655A608
146 #define CONFIG_SYS_DDR_CONTROL 0xE7000000 /* Type = DDR3: ECC enabled, No Interleaving */
147 #define CONFIG_SYS_DDR_CONTROL2 0x24400011
148 #define CONFIG_SYS_DDR_CDR1 0x00040000
149 #define CONFIG_SYS_DDR_CDR2 0x00000000
151 #define CONFIG_SYS_DDR_ERR_INT_EN 0x0000000d
152 #define CONFIG_SYS_DDR_ERR_DIS 0x00000000
153 #define CONFIG_SYS_DDR_SBE 0x00010000
155 /* Settings that differ for "performance" mode */
156 #define CONFIG_SYS_DDR_CS0_BNDS_PERF 0x0000007F /* Interleaving Enabled */
157 #define CONFIG_SYS_DDR_CS1_BNDS_PERF 0x00000000 /* Interleaving Enabled */
158 #define CONFIG_SYS_DDR_CS1_CONFIG_PERF 0x80014202
159 #define CONFIG_SYS_DDR_TIMING_1_PERF 0x5d5b4543
160 #define CONFIG_SYS_DDR_TIMING_2_PERF 0x0fa890ce
161 #define CONFIG_SYS_DDR_CONTROL_PERF 0xC7004000 /* Type = DDR3: ECC disabled, cs0-cs1 interleaving */
164 * The following set of values were tested for DDR2
165 * with a DDR3 to DDR2 interposer
167 #define CONFIG_SYS_DDR_TIMING_3 0x00000000
168 #define CONFIG_SYS_DDR_TIMING_0 0x00260802
169 #define CONFIG_SYS_DDR_TIMING_1 0x3935d322
170 #define CONFIG_SYS_DDR_TIMING_2 0x14904cc8
171 #define CONFIG_SYS_DDR_MODE_1 0x00480432
172 #define CONFIG_SYS_DDR_MODE_2 0x00000000
173 #define CONFIG_SYS_DDR_INTERVAL 0x06180100
174 #define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef
175 #define CONFIG_SYS_DDR_CLK_CTRL 0x03800000
176 #define CONFIG_SYS_DDR_OCD_CTRL 0x00000000
177 #define CONFIG_SYS_DDR_OCD_STATUS 0x00000000
178 #define CONFIG_SYS_DDR_CONTROL 0xC3008000
179 #define CONFIG_SYS_DDR_CONTROL2 0x04400010
183 #undef CONFIG_CLOCKS_IN_MHZ
188 * 0x0000_0000 0x7fff_ffff DDR 2G Cacheable
189 * 0x8000_0000 0xbfff_ffff PCI Express Mem 1G non-cacheable
190 * 0xc000_0000 0xdfff_ffff PCI 512M non-cacheable
191 * 0xe100_0000 0xe3ff_ffff PCI IO range 4M non-cacheable
193 * Localbus cacheable (TBD)
194 * 0xXXXX_XXXX 0xXXXX_XXXX SRAM YZ M Cacheable
196 * Localbus non-cacheable
197 * 0xe000_0000 0xe80f_ffff Promjet/free 128M non-cacheable
198 * 0xe800_0000 0xefff_ffff FLASH 128M non-cacheable
199 * 0xffa0_0000 0xffaf_ffff NAND 1M non-cacheable
200 * 0xffdf_0000 0xffdf_7fff PIXIS 32K non-cacheable TLB0
201 * 0xffd0_0000 0xffd0_3fff L1 for stack 16K Cacheable TLB0
202 * 0xffe0_0000 0xffef_ffff CCSR 1M non-cacheable
206 * Local Bus Definitions
208 #define CONFIG_SYS_FLASH_BASE 0xe0000000 /* start of FLASH 128M */
209 #ifdef CONFIG_PHYS_64BIT
210 #define CONFIG_SYS_FLASH_BASE_PHYS 0xfe0000000ull
212 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
215 #define CONFIG_FLASH_BR_PRELIM (BR_PHYS_ADDR((CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000)) | BR_PS_16 | BR_V)
216 #define CONFIG_FLASH_OR_PRELIM 0xf8000ff7
218 #define CONFIG_SYS_BR1_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | BR_PS_16 | BR_V)
219 #define CONFIG_SYS_OR1_PRELIM 0xf8000ff7
221 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS}
222 #define CONFIG_SYS_FLASH_QUIET_TEST
223 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
225 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */
226 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
227 #undef CONFIG_SYS_FLASH_CHECKSUM
228 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
229 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
231 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
233 #define CONFIG_FLASH_CFI_DRIVER
234 #define CONFIG_SYS_FLASH_CFI
235 #define CONFIG_SYS_FLASH_EMPTY_INFO
236 #define CONFIG_SYS_FLASH_AMD_CHECK_DQ7
238 #define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */
240 #define CONFIG_HWCONFIG /* enable hwconfig */
241 #define CONFIG_FSL_NGPIXIS /* use common ngPIXIS code */
243 #ifdef CONFIG_FSL_NGPIXIS
244 #define PIXIS_BASE 0xffdf0000 /* PIXIS registers */
245 #ifdef CONFIG_PHYS_64BIT
246 #define PIXIS_BASE_PHYS 0xfffdf0000ull
248 #define PIXIS_BASE_PHYS PIXIS_BASE
251 #define CONFIG_SYS_BR3_PRELIM (BR_PHYS_ADDR(PIXIS_BASE_PHYS) | BR_PS_8 | BR_V)
252 #define CONFIG_SYS_OR3_PRELIM 0xffffeff7 /* 32KB but only 4k mapped */
254 #define PIXIS_LBMAP_SWITCH 7
255 #define PIXIS_LBMAP_MASK 0xf0
256 #define PIXIS_LBMAP_SHIFT 4
257 #define PIXIS_LBMAP_ALTBANK 0x20
260 #define CONFIG_SYS_INIT_RAM_LOCK 1
261 #define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* Initial L1 address */
262 #ifdef CONFIG_PHYS_64BIT
263 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
264 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR
265 /* The assembler doesn't like typecast */
266 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
267 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
268 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
270 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS CONFIG_SYS_INIT_RAM_ADDR /* Initial L1 address */
271 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0
272 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS
274 #define CONFIG_SYS_INIT_RAM_END 0x00004000 /* End of used area in RAM */
276 #define CONFIG_SYS_GBL_DATA_SIZE 128 /* num bytes initial data */
277 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
278 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
280 #define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */
281 #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */
283 #define CONFIG_SYS_NAND_BASE 0xffa00000
284 #ifdef CONFIG_PHYS_64BIT
285 #define CONFIG_SYS_NAND_BASE_PHYS 0xfffa00000ull
287 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
289 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE,\
290 CONFIG_SYS_NAND_BASE + 0x40000, \
291 CONFIG_SYS_NAND_BASE + 0x80000,\
292 CONFIG_SYS_NAND_BASE + 0xC0000}
293 #define CONFIG_SYS_MAX_NAND_DEVICE 4
294 #define CONFIG_MTD_NAND_VERIFY_WRITE
295 #define CONFIG_CMD_NAND 1
296 #define CONFIG_NAND_FSL_ELBC 1
297 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
299 /* NAND flash config */
300 #define CONFIG_NAND_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
301 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
302 | BR_PS_8 /* Port Size = 8bit */ \
303 | BR_MS_FCM /* MSEL = FCM */ \
305 #define CONFIG_NAND_OR_PRELIM (0xFFFC0000 /* length 256K */ \
306 | OR_FCM_PGS /* Large Page*/ \
314 #define CONFIG_SYS_BR0_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */
315 #define CONFIG_SYS_OR0_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */
316 #define CONFIG_SYS_BR2_PRELIM CONFIG_NAND_BR_PRELIM /* NAND Base Address */
317 #define CONFIG_SYS_OR2_PRELIM CONFIG_NAND_OR_PRELIM /* NAND Options */
319 #define CONFIG_SYS_BR4_PRELIM (BR_PHYS_ADDR((CONFIG_SYS_NAND_BASE_PHYS + 0x40000))\
320 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
321 | BR_PS_8 /* Port Size = 8bit */ \
322 | BR_MS_FCM /* MSEL = FCM */ \
324 #define CONFIG_SYS_OR4_PRELIM CONFIG_NAND_OR_PRELIM /* NAND Options */
325 #define CONFIG_SYS_BR5_PRELIM (BR_PHYS_ADDR((CONFIG_SYS_NAND_BASE_PHYS + 0x80000))\
326 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
327 | BR_PS_8 /* Port Size = 8bit */ \
328 | BR_MS_FCM /* MSEL = FCM */ \
330 #define CONFIG_SYS_OR5_PRELIM CONFIG_NAND_OR_PRELIM /* NAND Options */
332 #define CONFIG_SYS_BR6_PRELIM (BR_PHYS_ADDR((CONFIG_SYS_NAND_BASE_PHYS + 0xc0000))\
333 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
334 | BR_PS_8 /* Port Size = 8bit */ \
335 | BR_MS_FCM /* MSEL = FCM */ \
337 #define CONFIG_SYS_OR6_PRELIM CONFIG_NAND_OR_PRELIM /* NAND Options */
339 /* Serial Port - controlled on board with jumper J8
343 #define CONFIG_CONS_INDEX 1
344 #define CONFIG_SYS_NS16550
345 #define CONFIG_SYS_NS16550_SERIAL
346 #define CONFIG_SYS_NS16550_REG_SIZE 1
347 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
349 #define CONFIG_SYS_BAUDRATE_TABLE \
350 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
352 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
353 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
355 /* Use the HUSH parser */
356 #define CONFIG_SYS_HUSH_PARSER
357 #ifdef CONFIG_SYS_HUSH_PARSER
358 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
362 * Pass open firmware flat tree
364 #define CONFIG_OF_LIBFDT 1
365 #define CONFIG_OF_BOARD_SETUP 1
366 #define CONFIG_OF_STDOUT_VIA_ALIAS 1
369 #define CONFIG_FSL_I2C /* Use FSL common I2C driver */
370 #define CONFIG_HARD_I2C /* I2C with hardware support */
371 #undef CONFIG_SOFT_I2C /* I2C bit-banged */
372 #define CONFIG_I2C_MULTI_BUS
373 #define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */
374 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
375 #define CONFIG_SYS_I2C_SLAVE 0x7F
376 #define CONFIG_SYS_I2C_NOPROBES {{0,0x29}}/* Don't probe these addrs */
377 #define CONFIG_SYS_I2C_OFFSET 0x3000
378 #define CONFIG_SYS_I2C2_OFFSET 0x3100
383 #define CONFIG_ID_EEPROM
384 #ifdef CONFIG_ID_EEPROM
385 #define CONFIG_SYS_I2C_EEPROM_NXID
387 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
388 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
389 #define CONFIG_SYS_EEPROM_BUS_NUM 0
393 * Memory space is mapped 1-1, but I/O space must start from 0.
396 /* controller 3, Slot 1, tgtid 3, Base address b000 */
397 #define CONFIG_SYS_PCIE3_MEM_VIRT 0x80000000
398 #ifdef CONFIG_PHYS_64BIT
399 #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000
400 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc00000000ull
402 #define CONFIG_SYS_PCIE3_MEM_BUS 0x80000000
403 #define CONFIG_SYS_PCIE3_MEM_PHYS 0x80000000
405 #define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */
406 #define CONFIG_SYS_PCIE3_IO_VIRT 0xffc00000
407 #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000
408 #ifdef CONFIG_PHYS_64BIT
409 #define CONFIG_SYS_PCIE3_IO_PHYS 0xfffc00000ull
411 #define CONFIG_SYS_PCIE3_IO_PHYS 0xffc00000
413 #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */
415 /* controller 2, direct to uli, tgtid 2, Base address 9000 */
416 #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000
417 #ifdef CONFIG_PHYS_64BIT
418 #define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000
419 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull
421 #define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000
422 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000
424 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */
425 #define CONFIG_SYS_PCIE2_IO_VIRT 0xffc10000
426 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
427 #ifdef CONFIG_PHYS_64BIT
428 #define CONFIG_SYS_PCIE2_IO_PHYS 0xfffc10000ull
430 #define CONFIG_SYS_PCIE2_IO_PHYS 0xffc10000
432 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */
434 /* controller 1, Slot 2, tgtid 1, Base address a000 */
435 #define CONFIG_SYS_PCIE1_MEM_VIRT 0xc0000000
436 #ifdef CONFIG_PHYS_64BIT
437 #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000
438 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc40000000ull
440 #define CONFIG_SYS_PCIE1_MEM_BUS 0xc0000000
441 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc0000000
443 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */
444 #define CONFIG_SYS_PCIE1_IO_VIRT 0xffc20000
445 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
446 #ifdef CONFIG_PHYS_64BIT
447 #define CONFIG_SYS_PCIE1_IO_PHYS 0xfffc20000ull
449 #define CONFIG_SYS_PCIE1_IO_PHYS 0xffc20000
451 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
453 #if defined(CONFIG_PCI)
455 /*PCIE video card used*/
456 #define VIDEO_IO_OFFSET CONFIG_SYS_PCIE1_IO_VIRT
461 #if defined(CONFIG_VIDEO)
462 #define CONFIG_BIOSEMU
463 #define CONFIG_CFB_CONSOLE
464 #define CONFIG_VIDEO_SW_CURSOR
465 #define CONFIG_VGA_AS_SINGLE_DEVICE
466 #define CONFIG_ATI_RADEON_FB
467 #define CONFIG_VIDEO_LOGO
468 /*#define CONFIG_CONSOLE_CURSOR*/
469 #define CONFIG_SYS_ISA_IO_BASE_ADDRESS VIDEO_IO_OFFSET
472 #define CONFIG_NET_MULTI
473 #define CONFIG_PCI_PNP /* do pci plug-and-play */
475 #undef CONFIG_EEPRO100
477 #define CONFIG_RTL8139
479 #ifndef CONFIG_PCI_PNP
480 #define PCI_ENET0_IOADDR CONFIG_SYS_PCIE3_IO_BUS
481 #define PCI_ENET0_MEMADDR CONFIG_SYS_PCIE3_IO_BUS
482 #define PCI_IDSEL_NUMBER 0x11 /* IDSEL = AD11 */
485 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
486 #define CONFIG_DOS_PARTITION
487 #define CONFIG_SCSI_AHCI
489 #ifdef CONFIG_SCSI_AHCI
490 #define CONFIG_SATA_ULI5288
491 #define CONFIG_SYS_SCSI_MAX_SCSI_ID 4
492 #define CONFIG_SYS_SCSI_MAX_LUN 1
493 #define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * CONFIG_SYS_SCSI_MAX_LUN)
494 #define CONFIG_SYS_SCSI_MAXDEVICE CONFIG_SYS_SCSI_MAX_DEVICE
497 #endif /* CONFIG_PCI */
500 #if defined(CONFIG_TSEC_ENET)
502 #ifndef CONFIG_NET_MULTI
503 #define CONFIG_NET_MULTI 1
506 #define CONFIG_MII 1 /* MII PHY management */
507 #define CONFIG_MII_DEFAULT_TSEC 1 /* Allow unregistered phys */
508 #define CONFIG_TSEC1 1
509 #define CONFIG_TSEC1_NAME "eTSEC1"
510 #define CONFIG_TSEC2 1
511 #define CONFIG_TSEC2_NAME "eTSEC2"
512 #define CONFIG_TSEC3 1
513 #define CONFIG_TSEC3_NAME "eTSEC3"
515 #define CONFIG_PIXIS_SGMII_CMD
516 #define CONFIG_FSL_SGMII_RISER 1
517 #define SGMII_RISER_PHY_OFFSET 0x1b
519 #ifdef CONFIG_FSL_SGMII_RISER
520 #define CONFIG_SYS_TBIPA_VALUE 0x10 /* avoid conflict with eTSEC4 paddr */
523 #define TSEC1_PHY_ADDR 0
524 #define TSEC2_PHY_ADDR 1
525 #define TSEC3_PHY_ADDR 2
527 #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
528 #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
529 #define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
531 #define TSEC1_PHYIDX 0
532 #define TSEC2_PHYIDX 0
533 #define TSEC3_PHYIDX 0
535 #define CONFIG_ETHPRIME "eTSEC1"
537 #define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */
538 #endif /* CONFIG_TSEC_ENET */
543 #define CONFIG_ENV_IS_IN_FLASH 1
544 #if CONFIG_SYS_MONITOR_BASE > 0xfff80000
545 #define CONFIG_ENV_ADDR 0xfff80000
547 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
549 #define CONFIG_ENV_SIZE 0x2000
550 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */
552 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
553 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
556 * Command line configuration.
558 #include <config_cmd_default.h>
560 #define CONFIG_CMD_IRQ
561 #define CONFIG_CMD_PING
562 #define CONFIG_CMD_I2C
563 #define CONFIG_CMD_MII
564 #define CONFIG_CMD_ELF
565 #define CONFIG_CMD_IRQ
566 #define CONFIG_CMD_SETEXPR
567 #define CONFIG_CMD_REGINFO
569 #if defined(CONFIG_PCI)
570 #define CONFIG_CMD_PCI
571 #define CONFIG_CMD_NET
572 #define CONFIG_CMD_SCSI
573 #define CONFIG_CMD_EXT2
579 #define CONFIG_CMD_USB
580 #define CONFIG_USB_STORAGE
581 #define CONFIG_USB_EHCI
582 #define CONFIG_USB_EHCI_FSL
583 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
585 #undef CONFIG_WATCHDOG /* watchdog disabled */
588 * Miscellaneous configurable options
590 #define CONFIG_SYS_LONGHELP /* undef to save memory */
591 #define CONFIG_CMDLINE_EDITING /* Command-line editing */
592 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */
593 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
594 #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
595 #if defined(CONFIG_CMD_KGDB)
596 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
598 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
600 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
601 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */
602 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
603 #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */
606 * For booting Linux, the board info and command line data
607 * have to be in the first 16 MB of memory, since this is
608 * the maximum mapped by the Linux kernel during initialization.
610 #define CONFIG_SYS_BOOTMAPSZ (16 << 20) /* Initial Memory map for Linux*/
613 * Internal Definitions
617 #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
618 #define BOOTFLAG_WARM 0x02 /* Software reboot */
620 #if defined(CONFIG_CMD_KGDB)
621 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
622 #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
626 * Environment Configuration
629 /* The mac addresses for all ethernet interface */
630 #if defined(CONFIG_TSEC_ENET)
631 #define CONFIG_HAS_ETH0
632 #define CONFIG_ETHADDR 00:E0:0C:02:00:FD
633 #define CONFIG_HAS_ETH1
634 #define CONFIG_ETH1ADDR 00:E0:0C:02:01:FD
635 #define CONFIG_HAS_ETH2
636 #define CONFIG_ETH2ADDR 00:E0:0C:02:02:FD
637 #define CONFIG_HAS_ETH3
638 #define CONFIG_ETH3ADDR 00:E0:0C:02:03:FD
641 #define CONFIG_IPADDR 192.168.1.254
643 #define CONFIG_HOSTNAME unknown
644 #define CONFIG_ROOTPATH /opt/nfsroot
645 #define CONFIG_BOOTFILE uImage
646 #define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */
648 #define CONFIG_SERVERIP 192.168.1.1
649 #define CONFIG_GATEWAYIP 192.168.1.1
650 #define CONFIG_NETMASK 255.255.255.0
652 /* default location for tftp and bootm */
653 #define CONFIG_LOADADDR 1000000
655 #define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */
656 #undef CONFIG_BOOTARGS /* the boot command will set bootargs */
658 #define CONFIG_BAUDRATE 115200
660 #define CONFIG_EXTRA_ENV_SETTINGS \
661 "perf_mode=stable\0" \
662 "memctl_intlv_ctl=2\0" \
664 "uboot=" MK_STR(CONFIG_UBOOTPATH) "\0" \
665 "tftpflash=tftpboot $loadaddr $uboot; " \
666 "protect off " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
667 "erase " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
668 "cp.b $loadaddr " MK_STR(CONFIG_SYS_TEXT_BASE) " $filesize; " \
669 "protect on " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
670 "cmp.b $loadaddr " MK_STR(CONFIG_SYS_TEXT_BASE) " $filesize\0" \
671 "consoledev=ttyS0\0" \
672 "ramdiskaddr=2000000\0" \
673 "ramdiskfile=p2020ds/ramdisk.uboot\0" \
675 "fdtfile=p2020ds/p2020ds.dtb\0" \
678 #define CONFIG_HDBOOT \
679 "setenv bootargs root=/dev/$bdev rw " \
680 "console=$consoledev,$baudrate $othbootargs;" \
681 "tftp $loadaddr $bootfile;" \
682 "tftp $fdtaddr $fdtfile;" \
683 "bootm $loadaddr - $fdtaddr"
685 #define CONFIG_NFSBOOTCOMMAND \
686 "setenv bootargs root=/dev/nfs rw " \
687 "nfsroot=$serverip:$rootpath " \
688 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
689 "console=$consoledev,$baudrate $othbootargs;" \
690 "tftp $loadaddr $bootfile;" \
691 "tftp $fdtaddr $fdtfile;" \
692 "bootm $loadaddr - $fdtaddr"
694 #define CONFIG_RAMBOOTCOMMAND \
695 "setenv bootargs root=/dev/ram rw " \
696 "console=$consoledev,$baudrate $othbootargs;" \
697 "tftp $ramdiskaddr $ramdiskfile;" \
698 "tftp $loadaddr $bootfile;" \
699 "tftp $fdtaddr $fdtfile;" \
700 "bootm $loadaddr $ramdiskaddr $fdtaddr"
702 #define CONFIG_BOOTCOMMAND CONFIG_HDBOOT
704 #endif /* __CONFIG_H */