2 * Copyright 2007-2012 Freescale Semiconductor, Inc.
4 * See file CREDITS for list of people who contributed to this
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of
10 * the License, or (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
24 * p2020ds board configuration file
30 #include "../board/freescale/common/ics307_clk.h"
33 #define CONFIG_PHYS_64BIT
37 #define CONFIG_SYS_RAMBOOT
38 #define CONFIG_SYS_EXTRA_ENV_RELOC
39 #define CONFIG_SYS_TEXT_BASE 0xf8f80000
40 #define CONFIG_RESET_VECTOR_ADDRESS 0xf8fffffc
43 #ifdef CONFIG_SPIFLASH
44 #define CONFIG_SYS_RAMBOOT
45 #define CONFIG_SYS_EXTRA_ENV_RELOC
46 #define CONFIG_SYS_TEXT_BASE 0xf8f80000
47 #define CONFIG_RESET_VECTOR_ADDRESS 0xf8fffffc
50 /* High Level Configuration Options */
51 #define CONFIG_BOOKE 1 /* BOOKE */
52 #define CONFIG_E500 1 /* BOOKE e500 family */
53 #define CONFIG_MPC85xx 1 /* MPC8540/60/55/41/48 */
54 #define CONFIG_P2020 1
55 #define CONFIG_P2020DS 1
56 #define CONFIG_MP 1 /* support multiple processors */
58 #ifndef CONFIG_SYS_TEXT_BASE
59 #define CONFIG_SYS_TEXT_BASE 0xeff80000
62 #ifndef CONFIG_RESET_VECTOR_ADDRESS
63 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
66 #define CONFIG_SYS_SRIO
67 #define CONFIG_SRIO1 /* SRIO port 1 */
68 #define CONFIG_SRIO2 /* SRIO port 2 */
70 #define CONFIG_FSL_ELBC 1 /* Has Enhanced localbus controller */
71 #define CONFIG_PCI 1 /* Enable PCI/PCIE */
72 #define CONFIG_PCIE1 1 /* PCIE controler 1 (slot 1) */
73 #define CONFIG_PCIE2 1 /* PCIE controler 2 (slot 2) */
74 #define CONFIG_PCIE3 1 /* PCIE controler 3 (ULI bridge) */
75 #define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */
76 #define CONFIG_PCI_INDIRECT_BRIDGE 1 /* indirect PCI bridge support */
77 #define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */
78 #define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */
80 #define CONFIG_FSL_LAW 1 /* Use common FSL init code */
81 #define CONFIG_E1000 1 /* Defind e1000 pci Ethernet card*/
83 #define CONFIG_TSEC_ENET /* tsec ethernet support */
84 #define CONFIG_ENV_OVERWRITE
86 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk() /* sysclk for MPC85xx */
87 #define CONFIG_DDR_CLK_FREQ get_board_ddr_clk() /* ddrclk for MPC85xx */
88 #define CONFIG_ICS307_REFCLK_HZ 33333000 /* ICS307 clock chip ref freq */
91 * These can be toggled for performance analysis, otherwise use default.
93 #define CONFIG_L2_CACHE /* toggle L2 cache */
94 #define CONFIG_BTB /* toggle branch predition */
96 #define CONFIG_BOARD_EARLY_INIT_F /* Call board_pre_init */
98 #define CONFIG_ENABLE_36BIT_PHYS 1
100 #ifdef CONFIG_PHYS_64BIT
101 #define CONFIG_ADDR_MAP 1
102 #define CONFIG_SYS_NUM_ADDR_MAP 16 /* number of TLB1 entries */
105 #define CONFIG_POST CONFIG_SYS_POST_MEMORY /* test POST memory test */
106 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */
107 #define CONFIG_SYS_MEMTEST_END 0x00400000
108 #define CONFIG_PANIC_HANG /* do not reset board on panic */
111 * Config the L2 Cache
113 #define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000
114 #ifdef CONFIG_PHYS_64BIT
115 #define CONFIG_SYS_INIT_L2_ADDR_PHYS 0xff8f80000ull
117 #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR
119 #define CONFIG_SYS_L2_SIZE (512 << 10)
120 #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
122 #define CONFIG_SYS_CCSRBAR 0xffe00000
123 #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
126 #define CONFIG_VERY_BIG_RAM
128 #define CONFIG_FSL_DDR2
130 #define CONFIG_FSL_DDR3 1
133 /* ECC will be enabled based on perf_mode environment variable */
134 /* #define CONFIG_DDR_ECC */
136 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
137 #define CONFIG_MEM_INIT_VALUE 0xDeadBeef
139 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
140 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
142 #define CONFIG_NUM_DDR_CONTROLLERS 1
143 #define CONFIG_DIMM_SLOTS_PER_CTLR 1
144 #define CONFIG_CHIP_SELECTS_PER_CTRL 2
146 /* I2C addresses of SPD EEPROMs */
147 #define CONFIG_DDR_SPD
148 #define CONFIG_SYS_SPD_BUS_NUM 0 /* SPD EEPROM located on I2C bus 0 */
149 #define SPD_EEPROM_ADDRESS 0x51 /* CTLR 0 DIMM 0 */
151 /* These are used when DDR doesn't use SPD. */
152 #define CONFIG_SYS_SDRAM_SIZE 1024 /* DDR is 1GB */
154 /* Default settings for "stable" mode */
155 #define CONFIG_SYS_DDR_CS0_BNDS 0x0000003F
156 #define CONFIG_SYS_DDR_CS1_BNDS 0x00000000
157 #define CONFIG_SYS_DDR_CS0_CONFIG 0x80014202
158 #define CONFIG_SYS_DDR_CS1_CONFIG 0x00000000
159 #define CONFIG_SYS_DDR_TIMING_3 0x00020000
160 #define CONFIG_SYS_DDR_TIMING_0 0x00330804
161 #define CONFIG_SYS_DDR_TIMING_1 0x6f6b4846
162 #define CONFIG_SYS_DDR_TIMING_2 0x0fa890d4
163 #define CONFIG_SYS_DDR_MODE_1 0x00421422
164 #define CONFIG_SYS_DDR_MODE_2 0x00000000
165 #define CONFIG_SYS_DDR_MODE_CTRL 0x00000000
166 #define CONFIG_SYS_DDR_INTERVAL 0x61800100
167 #define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef
168 #define CONFIG_SYS_DDR_CLK_CTRL 0x02000000
169 #define CONFIG_SYS_DDR_TIMING_4 0x00220001
170 #define CONFIG_SYS_DDR_TIMING_5 0x03402400
171 #define CONFIG_SYS_DDR_ZQ_CNTL 0x89080600
172 #define CONFIG_SYS_DDR_WRLVL_CNTL 0x8655A608
173 #define CONFIG_SYS_DDR_CONTROL 0xE7000000 /* Type = DDR3: ECC enabled, No Interleaving */
174 #define CONFIG_SYS_DDR_CONTROL2 0x24400011
175 #define CONFIG_SYS_DDR_CDR1 0x00040000
176 #define CONFIG_SYS_DDR_CDR2 0x00000000
178 #define CONFIG_SYS_DDR_ERR_INT_EN 0x0000000d
179 #define CONFIG_SYS_DDR_ERR_DIS 0x00000000
180 #define CONFIG_SYS_DDR_SBE 0x00010000
182 /* Settings that differ for "performance" mode */
183 #define CONFIG_SYS_DDR_CS0_BNDS_PERF 0x0000007F /* Interleaving Enabled */
184 #define CONFIG_SYS_DDR_CS1_BNDS_PERF 0x00000000 /* Interleaving Enabled */
185 #define CONFIG_SYS_DDR_CS1_CONFIG_PERF 0x80014202
186 #define CONFIG_SYS_DDR_TIMING_1_PERF 0x5d5b4543
187 #define CONFIG_SYS_DDR_TIMING_2_PERF 0x0fa890ce
188 #define CONFIG_SYS_DDR_CONTROL_PERF 0xC7004000 /* Type = DDR3: ECC disabled, cs0-cs1 interleaving */
191 * The following set of values were tested for DDR2
192 * with a DDR3 to DDR2 interposer
194 #define CONFIG_SYS_DDR_TIMING_3 0x00000000
195 #define CONFIG_SYS_DDR_TIMING_0 0x00260802
196 #define CONFIG_SYS_DDR_TIMING_1 0x3935d322
197 #define CONFIG_SYS_DDR_TIMING_2 0x14904cc8
198 #define CONFIG_SYS_DDR_MODE_1 0x00480432
199 #define CONFIG_SYS_DDR_MODE_2 0x00000000
200 #define CONFIG_SYS_DDR_INTERVAL 0x06180100
201 #define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef
202 #define CONFIG_SYS_DDR_CLK_CTRL 0x03800000
203 #define CONFIG_SYS_DDR_OCD_CTRL 0x00000000
204 #define CONFIG_SYS_DDR_OCD_STATUS 0x00000000
205 #define CONFIG_SYS_DDR_CONTROL 0xC3008000
206 #define CONFIG_SYS_DDR_CONTROL2 0x04400010
213 * 0x0000_0000 0x7fff_ffff DDR 2G Cacheable
214 * 0x8000_0000 0xbfff_ffff PCI Express Mem 1G non-cacheable
215 * 0xc000_0000 0xdfff_ffff PCI 512M non-cacheable
216 * 0xe100_0000 0xe3ff_ffff PCI IO range 4M non-cacheable
218 * Localbus cacheable (TBD)
219 * 0xXXXX_XXXX 0xXXXX_XXXX SRAM YZ M Cacheable
221 * Localbus non-cacheable
222 * 0xe000_0000 0xe80f_ffff Promjet/free 128M non-cacheable
223 * 0xe800_0000 0xefff_ffff FLASH 128M non-cacheable
224 * 0xffa0_0000 0xffaf_ffff NAND 1M non-cacheable
225 * 0xffdf_0000 0xffdf_7fff PIXIS 32K non-cacheable TLB0
226 * 0xffd0_0000 0xffd0_3fff L1 for stack 16K Cacheable TLB0
227 * 0xffe0_0000 0xffef_ffff CCSR 1M non-cacheable
231 * Local Bus Definitions
233 #define CONFIG_SYS_FLASH_BASE 0xe0000000 /* start of FLASH 128M */
234 #ifdef CONFIG_PHYS_64BIT
235 #define CONFIG_SYS_FLASH_BASE_PHYS 0xfe0000000ull
237 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
240 #define CONFIG_FLASH_BR_PRELIM \
241 (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000) | BR_PS_16 | BR_V)
242 #define CONFIG_FLASH_OR_PRELIM 0xf8000ff7
244 #define CONFIG_SYS_BR1_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | BR_PS_16 | BR_V)
245 #define CONFIG_SYS_OR1_PRELIM 0xf8000ff7
247 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS}
248 #define CONFIG_SYS_FLASH_QUIET_TEST
249 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
251 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */
252 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
253 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
254 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
256 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
258 #define CONFIG_FLASH_CFI_DRIVER
259 #define CONFIG_SYS_FLASH_CFI
260 #define CONFIG_SYS_FLASH_EMPTY_INFO
261 #define CONFIG_SYS_FLASH_AMD_CHECK_DQ7
263 #define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */
265 #define CONFIG_HWCONFIG /* enable hwconfig */
266 #define CONFIG_FSL_NGPIXIS /* use common ngPIXIS code */
268 #ifdef CONFIG_FSL_NGPIXIS
269 #define PIXIS_BASE 0xffdf0000 /* PIXIS registers */
270 #ifdef CONFIG_PHYS_64BIT
271 #define PIXIS_BASE_PHYS 0xfffdf0000ull
273 #define PIXIS_BASE_PHYS PIXIS_BASE
276 #define CONFIG_SYS_BR3_PRELIM (BR_PHYS_ADDR(PIXIS_BASE_PHYS) | BR_PS_8 | BR_V)
277 #define CONFIG_SYS_OR3_PRELIM 0xffffeff7 /* 32KB but only 4k mapped */
279 #define PIXIS_LBMAP_SWITCH 7
280 #define PIXIS_LBMAP_MASK 0xf0
281 #define PIXIS_LBMAP_SHIFT 4
282 #define PIXIS_LBMAP_ALTBANK 0x20
285 #define CONFIG_SYS_INIT_RAM_LOCK 1
286 #define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* Initial L1 address */
287 #ifdef CONFIG_PHYS_64BIT
288 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
289 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR
290 /* The assembler doesn't like typecast */
291 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
292 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
293 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
295 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS CONFIG_SYS_INIT_RAM_ADDR /* Initial L1 address */
296 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0
297 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS
299 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 /* Size of used area in RAM */
301 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
302 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
304 #define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */
305 #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */
307 #define CONFIG_SYS_NAND_BASE 0xffa00000
308 #ifdef CONFIG_PHYS_64BIT
309 #define CONFIG_SYS_NAND_BASE_PHYS 0xfffa00000ull
311 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
313 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE,\
314 CONFIG_SYS_NAND_BASE + 0x40000, \
315 CONFIG_SYS_NAND_BASE + 0x80000,\
316 CONFIG_SYS_NAND_BASE + 0xC0000}
317 #define CONFIG_SYS_MAX_NAND_DEVICE 4
318 #define CONFIG_MTD_NAND_VERIFY_WRITE
319 #define CONFIG_CMD_NAND 1
320 #define CONFIG_NAND_FSL_ELBC 1
321 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
323 /* NAND flash config */
324 #define CONFIG_SYS_NAND_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
325 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
326 | BR_PS_8 /* Port Size = 8bit */ \
327 | BR_MS_FCM /* MSEL = FCM */ \
329 #define CONFIG_SYS_NAND_OR_PRELIM (0xFFFC0000 /* length 256K */ \
330 | OR_FCM_PGS /* Large Page*/ \
338 #define CONFIG_SYS_BR0_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */
339 #define CONFIG_SYS_OR0_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */
340 #define CONFIG_SYS_BR2_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */
341 #define CONFIG_SYS_OR2_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
343 #define CONFIG_SYS_BR4_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS + 0x40000) \
344 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
345 | BR_PS_8 /* Port Size = 8bit */ \
346 | BR_MS_FCM /* MSEL = FCM */ \
348 #define CONFIG_SYS_OR4_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
349 #define CONFIG_SYS_BR5_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS + 0x80000) \
350 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
351 | BR_PS_8 /* Port Size = 8bit */ \
352 | BR_MS_FCM /* MSEL = FCM */ \
354 #define CONFIG_SYS_OR5_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
356 #define CONFIG_SYS_BR6_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS + 0xc0000) \
357 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
358 | BR_PS_8 /* Port Size = 8bit */ \
359 | BR_MS_FCM /* MSEL = FCM */ \
361 #define CONFIG_SYS_OR6_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
363 /* Serial Port - controlled on board with jumper J8
367 #define CONFIG_CONS_INDEX 1
368 #define CONFIG_SYS_NS16550
369 #define CONFIG_SYS_NS16550_SERIAL
370 #define CONFIG_SYS_NS16550_REG_SIZE 1
371 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
373 #define CONFIG_SYS_BAUDRATE_TABLE \
374 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
376 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
377 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
379 /* Use the HUSH parser */
380 #define CONFIG_SYS_HUSH_PARSER
383 * Pass open firmware flat tree
385 #define CONFIG_OF_LIBFDT 1
386 #define CONFIG_OF_BOARD_SETUP 1
387 #define CONFIG_OF_STDOUT_VIA_ALIAS 1
390 #define CONFIG_FSL_I2C /* Use FSL common I2C driver */
391 #define CONFIG_HARD_I2C /* I2C with hardware support */
392 #define CONFIG_I2C_MULTI_BUS
393 #define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */
394 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
395 #define CONFIG_SYS_I2C_SLAVE 0x7F
396 #define CONFIG_SYS_I2C_NOPROBES {{0,0x29}}/* Don't probe these addrs */
397 #define CONFIG_SYS_I2C_OFFSET 0x3000
398 #define CONFIG_SYS_I2C2_OFFSET 0x3100
403 #define CONFIG_ID_EEPROM
404 #ifdef CONFIG_ID_EEPROM
405 #define CONFIG_SYS_I2C_EEPROM_NXID
407 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
408 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
409 #define CONFIG_SYS_EEPROM_BUS_NUM 0
412 * eSPI - Enhanced SPI
414 #define CONFIG_FSL_ESPI
416 #define CONFIG_SPI_FLASH
417 #define CONFIG_SPI_FLASH_SPANSION
419 #define CONFIG_CMD_SF
420 #define CONFIG_SF_DEFAULT_SPEED 10000000
421 #define CONFIG_SF_DEFAULT_MODE SPI_MODE_0
425 * Memory space is mapped 1-1, but I/O space must start from 0.
428 /* controller 3, Slot 1, tgtid 3, Base address b000 */
429 #define CONFIG_SYS_PCIE3_NAME "Slot 1"
430 #define CONFIG_SYS_PCIE3_MEM_VIRT 0x80000000
431 #ifdef CONFIG_PHYS_64BIT
432 #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000
433 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc00000000ull
435 #define CONFIG_SYS_PCIE3_MEM_BUS 0x80000000
436 #define CONFIG_SYS_PCIE3_MEM_PHYS 0x80000000
438 #define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */
439 #define CONFIG_SYS_PCIE3_IO_VIRT 0xffc00000
440 #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000
441 #ifdef CONFIG_PHYS_64BIT
442 #define CONFIG_SYS_PCIE3_IO_PHYS 0xfffc00000ull
444 #define CONFIG_SYS_PCIE3_IO_PHYS 0xffc00000
446 #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */
448 /* controller 2, direct to uli, tgtid 2, Base address 9000 */
449 #define CONFIG_SYS_PCIE2_NAME "ULI"
450 #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000
451 #ifdef CONFIG_PHYS_64BIT
452 #define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000
453 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull
455 #define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000
456 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000
458 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */
459 #define CONFIG_SYS_PCIE2_IO_VIRT 0xffc10000
460 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
461 #ifdef CONFIG_PHYS_64BIT
462 #define CONFIG_SYS_PCIE2_IO_PHYS 0xfffc10000ull
464 #define CONFIG_SYS_PCIE2_IO_PHYS 0xffc10000
466 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */
468 /* controller 1, Slot 2, tgtid 1, Base address a000 */
469 #define CONFIG_SYS_PCIE1_NAME "Slot 2"
470 #define CONFIG_SYS_PCIE1_MEM_VIRT 0xc0000000
471 #ifdef CONFIG_PHYS_64BIT
472 #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000
473 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc40000000ull
475 #define CONFIG_SYS_PCIE1_MEM_BUS 0xc0000000
476 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc0000000
478 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */
479 #define CONFIG_SYS_PCIE1_IO_VIRT 0xffc20000
480 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
481 #ifdef CONFIG_PHYS_64BIT
482 #define CONFIG_SYS_PCIE1_IO_PHYS 0xfffc20000ull
484 #define CONFIG_SYS_PCIE1_IO_PHYS 0xffc20000
486 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
488 #if defined(CONFIG_PCI)
490 /*PCIE video card used*/
491 #define VIDEO_IO_OFFSET CONFIG_SYS_PCIE1_IO_VIRT
496 #if defined(CONFIG_VIDEO)
497 #define CONFIG_BIOSEMU
498 #define CONFIG_CFB_CONSOLE
499 #define CONFIG_VIDEO_SW_CURSOR
500 #define CONFIG_VGA_AS_SINGLE_DEVICE
501 #define CONFIG_ATI_RADEON_FB
502 #define CONFIG_VIDEO_LOGO
503 /*#define CONFIG_CONSOLE_CURSOR*/
504 #define CONFIG_SYS_ISA_IO_BASE_ADDRESS VIDEO_IO_OFFSET
507 /* SRIO1 uses the same window as PCIE2 mem window */
508 #define CONFIG_SYS_SRIO1_MEM_VIRT 0xa0000000
509 #ifdef CONFIG_PHYS_64BIT
510 #define CONFIG_SYS_SRIO1_MEM_PHYS 0xc20000000ull
512 #define CONFIG_SYS_SRIO1_MEM_PHYS 0xa0000000
514 #define CONFIG_SYS_SRIO1_MEM_SIZE 0x20000000 /* 512M */
516 /* SRIO2 uses the same window as PCIE1 mem window */
517 #define CONFIG_SYS_SRIO2_MEM_VIRT 0xc0000000
518 #ifdef CONFIG_PHYS_64BIT
519 #define CONFIG_SYS_SRIO2_MEM_PHYS 0xc40000000ull
521 #define CONFIG_SYS_SRIO2_MEM_PHYS 0xc0000000
523 #define CONFIG_SYS_SRIO2_MEM_SIZE 0x20000000 /* 512M */
525 #define CONFIG_PCI_PNP /* do pci plug-and-play */
526 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
527 #define CONFIG_DOS_PARTITION
528 #define CONFIG_SCSI_AHCI
530 #ifdef CONFIG_SCSI_AHCI
531 #define CONFIG_SATA_ULI5288
532 #define CONFIG_SYS_SCSI_MAX_SCSI_ID 4
533 #define CONFIG_SYS_SCSI_MAX_LUN 1
534 #define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * CONFIG_SYS_SCSI_MAX_LUN)
535 #define CONFIG_SYS_SCSI_MAXDEVICE CONFIG_SYS_SCSI_MAX_DEVICE
538 #endif /* CONFIG_PCI */
541 #if defined(CONFIG_TSEC_ENET)
543 #define CONFIG_MII 1 /* MII PHY management */
544 #define CONFIG_MII_DEFAULT_TSEC 1 /* Allow unregistered phys */
545 #define CONFIG_TSEC1 1
546 #define CONFIG_TSEC1_NAME "eTSEC1"
547 #define CONFIG_TSEC2 1
548 #define CONFIG_TSEC2_NAME "eTSEC2"
549 #define CONFIG_TSEC3 1
550 #define CONFIG_TSEC3_NAME "eTSEC3"
552 #define CONFIG_FSL_SGMII_RISER 1
553 #define SGMII_RISER_PHY_OFFSET 0x1b
555 #ifdef CONFIG_FSL_SGMII_RISER
556 #define CONFIG_SYS_TBIPA_VALUE 0x10 /* avoid conflict with eTSEC4 paddr */
559 #define TSEC1_PHY_ADDR 0
560 #define TSEC2_PHY_ADDR 1
561 #define TSEC3_PHY_ADDR 2
563 #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
564 #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
565 #define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
567 #define TSEC1_PHYIDX 0
568 #define TSEC2_PHYIDX 0
569 #define TSEC3_PHYIDX 0
571 #define CONFIG_ETHPRIME "eTSEC1"
573 #define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */
574 #endif /* CONFIG_TSEC_ENET */
579 #if defined(CONFIG_SDCARD)
580 #define CONFIG_ENV_IS_IN_MMC
581 #define CONFIG_FSL_FIXED_MMC_LOCATION
582 #define CONFIG_ENV_SIZE 0x2000
583 #define CONFIG_SYS_MMC_ENV_DEV 0
584 #elif defined(CONFIG_SPIFLASH)
585 #define CONFIG_ENV_IS_IN_SPI_FLASH
586 #define CONFIG_ENV_SPI_BUS 0
587 #define CONFIG_ENV_SPI_CS 0
588 #define CONFIG_ENV_SPI_MAX_HZ 10000000
589 #define CONFIG_ENV_SPI_MODE 0
590 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */
591 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */
592 #define CONFIG_ENV_SECT_SIZE 0x10000
594 #define CONFIG_ENV_IS_IN_FLASH 1
595 #if CONFIG_SYS_MONITOR_BASE > 0xfff80000
596 #define CONFIG_ENV_ADDR 0xfff80000
598 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
600 #define CONFIG_ENV_SIZE 0x2000
601 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */
604 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
605 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
608 * Command line configuration.
610 #include <config_cmd_default.h>
612 #define CONFIG_CMD_IRQ
613 #define CONFIG_CMD_PING
614 #define CONFIG_CMD_I2C
615 #define CONFIG_CMD_MII
616 #define CONFIG_CMD_ELF
617 #define CONFIG_CMD_IRQ
618 #define CONFIG_CMD_SETEXPR
619 #define CONFIG_CMD_REGINFO
621 #if defined(CONFIG_PCI)
622 #define CONFIG_CMD_PCI
623 #define CONFIG_CMD_NET
624 #define CONFIG_CMD_SCSI
625 #define CONFIG_CMD_EXT2
631 #define CONFIG_HAS_FSL_DR_USB
632 #ifdef CONFIG_HAS_FSL_DR_USB
633 #define CONFIG_USB_EHCI
635 #ifdef CONFIG_USB_EHCI
636 #define CONFIG_CMD_USB
637 #define CONFIG_USB_STORAGE
638 #define CONFIG_USB_EHCI_FSL
639 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
649 #define CONFIG_FSL_ESDHC
650 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
651 #define CONFIG_CMD_MMC
652 #define CONFIG_GENERIC_MMC
655 #if defined(CONFIG_MMC) || defined(CONFIG_USB_EHCI)
656 #define CONFIG_CMD_EXT2
657 #define CONFIG_CMD_FAT
658 #define CONFIG_DOS_PARTITION
662 * Miscellaneous configurable options
664 #define CONFIG_SYS_LONGHELP /* undef to save memory */
665 #define CONFIG_CMDLINE_EDITING /* Command-line editing */
666 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */
667 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
668 #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
669 #if defined(CONFIG_CMD_KGDB)
670 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
672 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
674 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
675 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */
676 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
677 #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */
680 * For booting Linux, the board info and command line data
681 * have to be in the first 64 MB of memory, since this is
682 * the maximum mapped by the Linux kernel during initialization.
684 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux*/
685 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
687 #if defined(CONFIG_CMD_KGDB)
688 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
689 #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
693 * Environment Configuration
696 /* The mac addresses for all ethernet interface */
697 #if defined(CONFIG_TSEC_ENET)
698 #define CONFIG_HAS_ETH0
699 #define CONFIG_HAS_ETH1
700 #define CONFIG_HAS_ETH2
703 #define CONFIG_IPADDR 192.168.1.254
705 #define CONFIG_HOSTNAME unknown
706 #define CONFIG_ROOTPATH "/opt/nfsroot"
707 #define CONFIG_BOOTFILE "uImage"
708 #define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */
710 #define CONFIG_SERVERIP 192.168.1.1
711 #define CONFIG_GATEWAYIP 192.168.1.1
712 #define CONFIG_NETMASK 255.255.255.0
714 /* default location for tftp and bootm */
715 #define CONFIG_LOADADDR 1000000
717 #define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */
719 #define CONFIG_BAUDRATE 115200
721 #define CONFIG_EXTRA_ENV_SETTINGS \
722 "perf_mode=performance\0" \
723 "hwconfig=fsl_ddr:ctlr_intlv=bank,bank_intlv=cs0_cs1;" \
724 "usb1:dr_mode=host,phy_type=ulpi\0" \
726 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
727 "tftpflash=tftpboot $loadaddr $uboot; " \
728 "protect off " __stringify(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
729 "erase " __stringify(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
730 "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) " $filesize; " \
731 "protect on " __stringify(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
732 "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) " $filesize\0" \
733 "satabootcmd=setenv bootargs root=/dev/$bdev rw " \
734 "console=$consoledev,$baudrate $othbootargs;" \
735 "tftp $loadaddr $bootfile;" \
736 "tftp $fdtaddr $fdtfile;" \
737 "bootm $loadaddr - $fdtaddr" \
738 "consoledev=ttyS0\0" \
739 "ramdiskaddr=2000000\0" \
740 "ramdiskfile=p2020ds/ramdisk.uboot\0" \
742 "othbootargs=cache-sram-size=0x10000\0" \
743 "fdtfile=p2020ds/p2020ds.dtb\0" \
745 "partition=scsi 0:0\0"
747 #define CONFIG_HDBOOT \
748 "setenv bootargs root=/dev/$bdev rw " \
749 "console=$consoledev,$baudrate $othbootargs;" \
750 "ext2load $partition $loadaddr $bootfile;" \
751 "ext2load $partition $fdtaddr $fdtfile;" \
752 "bootm $loadaddr - $fdtaddr"
754 #define CONFIG_NFSBOOTCOMMAND \
755 "setenv bootargs root=/dev/nfs rw " \
756 "nfsroot=$serverip:$rootpath " \
757 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
758 "console=$consoledev,$baudrate $othbootargs;" \
759 "tftp $loadaddr $bootfile;" \
760 "tftp $fdtaddr $fdtfile;" \
761 "bootm $loadaddr - $fdtaddr"
763 #define CONFIG_RAMBOOTCOMMAND \
764 "setenv bootargs root=/dev/ram rw " \
765 "console=$consoledev,$baudrate $othbootargs;" \
766 "tftp $ramdiskaddr $ramdiskfile;" \
767 "tftp $loadaddr $bootfile;" \
768 "tftp $fdtaddr $fdtfile;" \
769 "bootm $loadaddr $ramdiskaddr $fdtaddr"
771 #define CONFIG_BOOTCOMMAND CONFIG_HDBOOT
773 #endif /* __CONFIG_H */