2 * Copyright 2011-2012 Freescale Semiconductor, Inc.
4 * SPDX-License-Identifier: GPL-2.0+
8 * P2041 RDB board configuration file
9 * Also supports P2040 RDB
14 #ifdef CONFIG_RAMBOOT_PBL
15 #define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE
16 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
17 #define CONFIG_SYS_FSL_PBL_PBI board/freescale/corenet_ds/pbi.cfg
18 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/corenet_ds/rcw_p2041rdb.cfg
21 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
22 /* Set 1M boot space */
23 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000)
24 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \
25 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR)
26 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
27 #define CONFIG_SYS_NO_FLASH
30 /* High Level Configuration Options */
31 #define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */
32 #define CONFIG_MP /* support multiple processors */
34 #ifndef CONFIG_SYS_TEXT_BASE
35 #define CONFIG_SYS_TEXT_BASE 0xeff40000
38 #ifndef CONFIG_RESET_VECTOR_ADDRESS
39 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
42 #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */
43 #define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS
44 #define CONFIG_FSL_ELBC /* Has Enhanced localbus controller */
45 #define CONFIG_FSL_CAAM /* Enable SEC/CAAM */
46 #define CONFIG_PCIE1 /* PCIE controller 1 */
47 #define CONFIG_PCIE2 /* PCIE controller 2 */
48 #define CONFIG_PCIE3 /* PCIE controller 3 */
49 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */
50 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
52 #define CONFIG_SYS_SRIO
53 #define CONFIG_SRIO1 /* SRIO port 1 */
54 #define CONFIG_SRIO2 /* SRIO port 2 */
55 #define CONFIG_SRIO_PCIE_BOOT_MASTER
56 #define CONFIG_SYS_DPAA_RMAN /* RMan */
58 #define CONFIG_ENV_OVERWRITE
60 #ifdef CONFIG_SYS_NO_FLASH
61 #if !defined(CONFIG_RAMBOOT_PBL) && !defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
62 #define CONFIG_ENV_IS_NOWHERE
65 #define CONFIG_FLASH_CFI_DRIVER
66 #define CONFIG_SYS_FLASH_CFI
67 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
70 #if defined(CONFIG_SPIFLASH)
71 #define CONFIG_SYS_EXTRA_ENV_RELOC
72 #define CONFIG_ENV_IS_IN_SPI_FLASH
73 #define CONFIG_ENV_SPI_BUS 0
74 #define CONFIG_ENV_SPI_CS 0
75 #define CONFIG_ENV_SPI_MAX_HZ 10000000
76 #define CONFIG_ENV_SPI_MODE 0
77 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */
78 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */
79 #define CONFIG_ENV_SECT_SIZE 0x10000
80 #elif defined(CONFIG_SDCARD)
81 #define CONFIG_SYS_EXTRA_ENV_RELOC
82 #define CONFIG_ENV_IS_IN_MMC
83 #define CONFIG_FSL_FIXED_MMC_LOCATION
84 #define CONFIG_SYS_MMC_ENV_DEV 0
85 #define CONFIG_ENV_SIZE 0x2000
86 #define CONFIG_ENV_OFFSET (512 * 1658)
87 #elif defined(CONFIG_NAND)
88 #define CONFIG_SYS_EXTRA_ENV_RELOC
89 #define CONFIG_ENV_IS_IN_NAND
90 #define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE
91 #define CONFIG_ENV_OFFSET (7 * CONFIG_SYS_NAND_BLOCK_SIZE)
92 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
93 #define CONFIG_ENV_IS_IN_REMOTE
94 #define CONFIG_ENV_ADDR 0xffe20000
95 #define CONFIG_ENV_SIZE 0x2000
96 #elif defined(CONFIG_ENV_IS_NOWHERE)
97 #define CONFIG_ENV_SIZE 0x2000
99 #define CONFIG_ENV_IS_IN_FLASH
100 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE \
101 - CONFIG_ENV_SECT_SIZE)
102 #define CONFIG_ENV_SIZE 0x2000
103 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */
107 unsigned long get_board_sys_clk(unsigned long dummy);
109 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk(0)
112 * These can be toggled for performance analysis, otherwise use default.
114 #define CONFIG_SYS_CACHE_STASHING
115 #define CONFIG_BACKSIDE_L2_CACHE
116 #define CONFIG_SYS_INIT_L2CSR0 L2CSR0_L2E
117 #define CONFIG_BTB /* toggle branch predition */
119 #define CONFIG_ENABLE_36BIT_PHYS
121 #ifdef CONFIG_PHYS_64BIT
122 #define CONFIG_ADDR_MAP
123 #define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */
126 #define CONFIG_POST CONFIG_SYS_POST_MEMORY /* test POST memory test */
127 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */
128 #define CONFIG_SYS_MEMTEST_END 0x00400000
129 #define CONFIG_SYS_ALT_MEMTEST
130 #define CONFIG_PANIC_HANG /* do not reset board on panic */
133 * Config the L3 Cache as L3 SRAM
135 #define CONFIG_SYS_INIT_L3_ADDR CONFIG_RAMBOOT_TEXT_BASE
136 #ifdef CONFIG_PHYS_64BIT
137 #define CONFIG_SYS_INIT_L3_ADDR_PHYS (0xf00000000ull | \
138 CONFIG_RAMBOOT_TEXT_BASE)
140 #define CONFIG_SYS_INIT_L3_ADDR_PHYS CONFIG_SYS_INIT_L3_ADDR
142 #define CONFIG_SYS_L3_SIZE (1024 << 10)
143 #define CONFIG_SYS_INIT_L3_END (CONFIG_SYS_INIT_L3_ADDR + CONFIG_SYS_L3_SIZE)
145 #ifdef CONFIG_PHYS_64BIT
146 #define CONFIG_SYS_DCSRBAR 0xf0000000
147 #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull
151 #define CONFIG_ID_EEPROM
152 #define CONFIG_SYS_I2C_EEPROM_NXID
153 #define CONFIG_SYS_EEPROM_BUS_NUM 0
154 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50
155 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
160 #define CONFIG_VERY_BIG_RAM
161 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
162 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
164 #define CONFIG_DIMM_SLOTS_PER_CTLR 1
165 #define CONFIG_CHIP_SELECTS_PER_CTRL (4 * CONFIG_DIMM_SLOTS_PER_CTLR)
167 #define CONFIG_DDR_SPD
169 #define CONFIG_SYS_SPD_BUS_NUM 0
170 #define SPD_EEPROM_ADDRESS 0x52
171 #define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */
174 * Local Bus Definitions
177 /* Set the local bus clock 1/8 of platform clock */
178 #define CONFIG_SYS_LBC_LCRR LCRR_CLKDIV_8
181 * This board doesn't have a promjet connector.
182 * However, it uses commone corenet board LAW and TLB.
183 * It is necessary to use the same start address with proper offset.
185 #define CONFIG_SYS_FLASH_BASE 0xe0000000
186 #ifdef CONFIG_PHYS_64BIT
187 #define CONFIG_SYS_FLASH_BASE_PHYS 0xfe0000000ull
189 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
192 #define CONFIG_SYS_FLASH_BR_PRELIM \
193 (BR_PHYS_ADDR((CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000)) | \
195 #define CONFIG_SYS_FLASH_OR_PRELIM \
196 ((0xf8000ff7 & ~OR_GPCM_SCY & ~OR_GPCM_EHTR) \
197 | OR_GPCM_SCY_8 | OR_GPCM_EHTR_CLEAR)
199 #define CONFIG_FSL_CPLD
200 #define CPLD_BASE 0xffdf0000 /* CPLD registers */
201 #ifdef CONFIG_PHYS_64BIT
202 #define CPLD_BASE_PHYS 0xfffdf0000ull
204 #define CPLD_BASE_PHYS CPLD_BASE
207 #define CONFIG_SYS_BR3_PRELIM (BR_PHYS_ADDR(CPLD_BASE_PHYS) | BR_PS_8 | BR_V)
208 #define CONFIG_SYS_OR3_PRELIM 0xffffeff7 /* 32KB but only 4k mapped */
210 #define PIXIS_LBMAP_SWITCH 7
211 #define PIXIS_LBMAP_MASK 0xf0
212 #define PIXIS_LBMAP_SHIFT 4
213 #define PIXIS_LBMAP_ALTBANK 0x40
215 #define CONFIG_SYS_FLASH_QUIET_TEST
216 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
218 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
219 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
220 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Erase Timeout (ms) */
221 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Write Timeout (ms) */
223 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
225 #if defined(CONFIG_RAMBOOT_PBL)
226 #define CONFIG_SYS_RAMBOOT
229 #define CONFIG_NAND_FSL_ELBC
231 #ifdef CONFIG_NAND_FSL_ELBC
232 #define CONFIG_SYS_NAND_BASE 0xffa00000
233 #ifdef CONFIG_PHYS_64BIT
234 #define CONFIG_SYS_NAND_BASE_PHYS 0xfffa00000ull
236 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
239 #define CONFIG_SYS_NAND_BASE_LIST {CONFIG_SYS_NAND_BASE}
240 #define CONFIG_SYS_MAX_NAND_DEVICE 1
241 #define CONFIG_CMD_NAND
242 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
244 /* NAND flash config */
245 #define CONFIG_SYS_NAND_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
246 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
247 | BR_PS_8 /* Port Size = 8 bit */ \
248 | BR_MS_FCM /* MSEL = FCM */ \
250 #define CONFIG_SYS_NAND_OR_PRELIM (0xFFFC0000 /* length 256K */ \
251 | OR_FCM_PGS /* Large Page*/ \
260 #define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */
261 #define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
262 #define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_FLASH_BR_PRELIM /* NOR Base Address */
263 #define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_FLASH_OR_PRELIM /* NOR Options */
265 #define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_FLASH_BR_PRELIM /* NOR Base Address */
266 #define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_FLASH_OR_PRELIM /* NOR Options */
267 #define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */
268 #define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
271 #define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_FLASH_BR_PRELIM /* NOR Base Address */
272 #define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_FLASH_OR_PRELIM /* NOR Options */
273 #endif /* CONFIG_NAND_FSL_ELBC */
275 #define CONFIG_SYS_FLASH_EMPTY_INFO
276 #define CONFIG_SYS_FLASH_AMD_CHECK_DQ7
277 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000}
279 #define CONFIG_BOARD_EARLY_INIT_F
280 #define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */
281 #define CONFIG_MISC_INIT_R
283 #define CONFIG_HWCONFIG
285 /* define to use L1 as initial stack */
286 #define CONFIG_L1_INIT_RAM
287 #define CONFIG_SYS_INIT_RAM_LOCK
288 #define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* Initial L1 address */
289 #ifdef CONFIG_PHYS_64BIT
290 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
291 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR
292 /* The assembler doesn't like typecast */
293 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
294 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
295 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
297 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS CONFIG_SYS_INIT_RAM_ADDR
298 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0
299 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS
301 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000
303 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
304 GENERATED_GBL_DATA_SIZE)
305 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
307 #define CONFIG_SYS_MONITOR_LEN (768 * 1024)
308 #define CONFIG_SYS_MALLOC_LEN (1024 * 1024)
310 /* Serial Port - controlled on board with jumper J8
314 #define CONFIG_CONS_INDEX 1
315 #define CONFIG_SYS_NS16550_SERIAL
316 #define CONFIG_SYS_NS16550_REG_SIZE 1
317 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2)
319 #define CONFIG_SYS_BAUDRATE_TABLE \
320 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
322 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
323 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
324 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
325 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
328 #define CONFIG_SYS_I2C
329 #define CONFIG_SYS_I2C_FSL
330 #define CONFIG_SYS_FSL_I2C_SPEED 400000
331 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
332 #define CONFIG_SYS_FSL_I2C_OFFSET 0x118000
333 #define CONFIG_SYS_FSL_I2C2_SPEED 400000
334 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
335 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100
340 #define CONFIG_SYS_SRIO1_MEM_VIRT 0xa0000000
341 #ifdef CONFIG_PHYS_64BIT
342 #define CONFIG_SYS_SRIO1_MEM_PHYS 0xc20000000ull
344 #define CONFIG_SYS_SRIO1_MEM_PHYS 0xa0000000
346 #define CONFIG_SYS_SRIO1_MEM_SIZE 0x10000000 /* 256M */
348 #define CONFIG_SYS_SRIO2_MEM_VIRT 0xb0000000
349 #ifdef CONFIG_PHYS_64BIT
350 #define CONFIG_SYS_SRIO2_MEM_PHYS 0xc30000000ull
352 #define CONFIG_SYS_SRIO2_MEM_PHYS 0xb0000000
354 #define CONFIG_SYS_SRIO2_MEM_SIZE 0x10000000 /* 256M */
357 * for slave u-boot IMAGE instored in master memory space,
358 * PHYS must be aligned based on the SIZE
360 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull
361 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull
362 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x100000 /* 1M */
363 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull
365 * for slave UCODE and ENV instored in master memory space,
366 * PHYS must be aligned based on the SIZE
368 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull
369 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull
370 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000 /* 256K */
372 /* slave core release by master*/
373 #define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4
374 #define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */
377 * SRIO_PCIE_BOOT - SLAVE
379 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
380 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000
381 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \
382 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR)
386 * eSPI - Enhanced SPI
388 #define CONFIG_SF_DEFAULT_SPEED 10000000
389 #define CONFIG_SF_DEFAULT_MODE 0
393 * Memory space is mapped 1-1, but I/O space must start from 0.
396 /* controller 1, direct to uli, tgtid 3, Base address 20000 */
397 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000
398 #ifdef CONFIG_PHYS_64BIT
399 #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000
400 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull
402 #define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000
403 #define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000
405 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */
406 #define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000
407 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
408 #ifdef CONFIG_PHYS_64BIT
409 #define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull
411 #define CONFIG_SYS_PCIE1_IO_PHYS 0xf8000000
413 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
415 /* controller 2, Slot 2, tgtid 2, Base address 201000 */
416 #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000
417 #ifdef CONFIG_PHYS_64BIT
418 #define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000
419 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull
421 #define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000
422 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000
424 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */
425 #define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000
426 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
427 #ifdef CONFIG_PHYS_64BIT
428 #define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull
430 #define CONFIG_SYS_PCIE2_IO_PHYS 0xf8010000
432 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */
434 /* controller 3, Slot 1, tgtid 1, Base address 202000 */
435 #define CONFIG_SYS_PCIE3_MEM_VIRT 0xc0000000
436 #ifdef CONFIG_PHYS_64BIT
437 #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000
438 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc40000000ull
440 #define CONFIG_SYS_PCIE3_MEM_BUS 0xc0000000
441 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc0000000
443 #define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */
444 #define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000
445 #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000
446 #ifdef CONFIG_PHYS_64BIT
447 #define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull
449 #define CONFIG_SYS_PCIE3_IO_PHYS 0xf8020000
451 #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */
454 #define CONFIG_SYS_DPAA_QBMAN /* Support Q/Bman */
455 #define CONFIG_SYS_BMAN_NUM_PORTALS 10
456 #define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000
457 #ifdef CONFIG_PHYS_64BIT
458 #define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull
460 #define CONFIG_SYS_BMAN_MEM_PHYS CONFIG_SYS_BMAN_MEM_BASE
462 #define CONFIG_SYS_BMAN_MEM_SIZE 0x00200000
463 #define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000
464 #define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000
465 #define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE
466 #define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
467 #define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \
468 CONFIG_SYS_BMAN_CENA_SIZE)
469 #define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
470 #define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08
471 #define CONFIG_SYS_QMAN_NUM_PORTALS 10
472 #define CONFIG_SYS_QMAN_MEM_BASE 0xf4200000
473 #ifdef CONFIG_PHYS_64BIT
474 #define CONFIG_SYS_QMAN_MEM_PHYS 0xff4200000ull
476 #define CONFIG_SYS_QMAN_MEM_PHYS CONFIG_SYS_QMAN_MEM_BASE
478 #define CONFIG_SYS_QMAN_MEM_SIZE 0x00200000
479 #define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000
480 #define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000
481 #define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE
482 #define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
483 #define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \
484 CONFIG_SYS_QMAN_CENA_SIZE)
485 #define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
486 #define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08
488 #define CONFIG_SYS_DPAA_FMAN
489 #define CONFIG_SYS_DPAA_PME
490 /* Default address of microcode for the Linux Fman driver */
491 #if defined(CONFIG_SPIFLASH)
493 * env is stored at 0x100000, sector size is 0x10000, ucode is stored after
494 * env, so we got 0x110000.
496 #define CONFIG_SYS_QE_FW_IN_SPIFLASH
497 #define CONFIG_SYS_FMAN_FW_ADDR 0x110000
498 #elif defined(CONFIG_SDCARD)
500 * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
501 * about 825KB (1650 blocks), Env is stored after the image, and the env size is
502 * 0x2000 (16 blocks), 8 + 1650 + 16 = 1674, enlarge it to 1680.
504 #define CONFIG_SYS_QE_FMAN_FW_IN_MMC
505 #define CONFIG_SYS_FMAN_FW_ADDR (512 * 1680)
506 #elif defined(CONFIG_NAND)
507 #define CONFIG_SYS_QE_FMAN_FW_IN_NAND
508 #define CONFIG_SYS_FMAN_FW_ADDR (8 * CONFIG_SYS_NAND_BLOCK_SIZE)
509 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
511 * Slave has no ucode locally, it can fetch this from remote. When implementing
512 * in two corenet boards, slave's ucode could be stored in master's memory
513 * space, the address can be mapped from slave TLB->slave LAW->
514 * slave SRIO or PCIE outbound window->master inbound window->
515 * master LAW->the ucode address in master's memory space.
517 #define CONFIG_SYS_QE_FMAN_FW_IN_REMOTE
518 #define CONFIG_SYS_FMAN_FW_ADDR 0xFFE00000
520 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR
521 #define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000
523 #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000
524 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
526 #ifdef CONFIG_SYS_DPAA_FMAN
527 #define CONFIG_FMAN_ENET
528 #define CONFIG_PHYLIB_10G
529 #define CONFIG_PHY_VITESSE
530 #define CONFIG_PHY_TERANETICS
534 #define CONFIG_PCI_INDIRECT_BRIDGE
536 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
537 #define CONFIG_DOS_PARTITION
538 #endif /* CONFIG_PCI */
541 #define CONFIG_FSL_SATA_V2
543 #ifdef CONFIG_FSL_SATA_V2
544 #define CONFIG_FSL_SATA
545 #define CONFIG_LIBATA
547 #define CONFIG_SYS_SATA_MAX_DEVICE 2
549 #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR
550 #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA
552 #define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR
553 #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA
556 #define CONFIG_CMD_SATA
557 #define CONFIG_DOS_PARTITION
560 #ifdef CONFIG_FMAN_ENET
561 #define CONFIG_SYS_FM1_DTSEC1_PHY_ADDR 0x2
562 #define CONFIG_SYS_FM1_DTSEC2_PHY_ADDR 0x3
563 #define CONFIG_SYS_FM1_DTSEC3_PHY_ADDR 0x4
564 #define CONFIG_SYS_FM1_DTSEC4_PHY_ADDR 0x1
565 #define CONFIG_SYS_FM1_DTSEC5_PHY_ADDR 0x0
567 #define CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR 0x1c
568 #define CONFIG_SYS_FM1_DTSEC2_RISER_PHY_ADDR 0x1d
569 #define CONFIG_SYS_FM1_DTSEC3_RISER_PHY_ADDR 0x1e
570 #define CONFIG_SYS_FM1_DTSEC4_RISER_PHY_ADDR 0x1f
572 #define CONFIG_SYS_FM1_10GEC1_PHY_ADDR 0
574 #define CONFIG_SYS_TBIPA_VALUE 8
575 #define CONFIG_MII /* MII PHY management */
576 #define CONFIG_ETHPRIME "FM1@DTSEC1"
577 #define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */
583 #define CONFIG_LOADS_ECHO /* echo on for serial download */
584 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */
587 * Command line configuration.
589 #define CONFIG_CMD_ERRATA
590 #define CONFIG_CMD_IRQ
593 #define CONFIG_CMD_PCI
599 #define CONFIG_HAS_FSL_DR_USB
600 #define CONFIG_HAS_FSL_MPH_USB
602 #if defined(CONFIG_HAS_FSL_DR_USB) || defined(CONFIG_HAS_FSL_MPH_USB)
603 #define CONFIG_USB_EHCI
604 #define CONFIG_USB_EHCI_FSL
605 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
609 #define CONFIG_FSL_ESDHC
610 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
611 #define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT
612 #define CONFIG_GENERIC_MMC
613 #define CONFIG_DOS_PARTITION
616 /* Hash command with SHA acceleration supported in hardware */
617 #ifdef CONFIG_FSL_CAAM
618 #define CONFIG_CMD_HASH
619 #define CONFIG_SHA_HW_ACCEL
623 * Miscellaneous configurable options
625 #define CONFIG_SYS_LONGHELP /* undef to save memory */
626 #define CONFIG_CMDLINE_EDITING /* Command-line editing */
627 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */
628 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
629 #ifdef CONFIG_CMD_KGDB
630 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
632 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
634 /* Print Buffer Size */
635 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
636 sizeof(CONFIG_SYS_PROMPT)+16)
637 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */
638 /* Boot Argument Buffer Size */
639 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
642 * For booting Linux, the board info and command line data
643 * have to be in the first 64 MB of memory, since this is
644 * the maximum mapped by the Linux kernel during initialization.
646 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory for Linux */
647 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
649 #ifdef CONFIG_CMD_KGDB
650 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
654 * Environment Configuration
656 #define CONFIG_ROOTPATH "/opt/nfsroot"
657 #define CONFIG_BOOTFILE "uImage"
658 #define CONFIG_UBOOTPATH u-boot.bin
660 /* default location for tftp and bootm */
661 #define CONFIG_LOADADDR 1000000
664 #define CONFIG_BAUDRATE 115200
666 #define __USB_PHY_TYPE utmi
668 #define CONFIG_EXTRA_ENV_SETTINGS \
669 "hwconfig=fsl_ddr:ctlr_intlv=cacheline," \
670 "bank_intlv=cs0_cs1\0" \
672 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
673 "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \
674 "tftpflash=tftpboot $loadaddr $uboot && " \
675 "protect off $ubootaddr +$filesize && " \
676 "erase $ubootaddr +$filesize && " \
677 "cp.b $loadaddr $ubootaddr $filesize && " \
678 "protect on $ubootaddr +$filesize && " \
679 "cmp.b $loadaddr $ubootaddr $filesize\0" \
680 "consoledev=ttyS0\0" \
681 "usb_phy_type=" __stringify(__USB_PHY_TYPE) "\0" \
682 "usb_dr_mode=host\0" \
683 "ramdiskaddr=2000000\0" \
684 "ramdiskfile=p2041rdb/ramdisk.uboot\0" \
685 "fdtaddr=1e00000\0" \
686 "fdtfile=p2041rdb/p2041rdb.dtb\0" \
689 #define CONFIG_HDBOOT \
690 "setenv bootargs root=/dev/$bdev rw " \
691 "console=$consoledev,$baudrate $othbootargs;" \
692 "tftp $loadaddr $bootfile;" \
693 "tftp $fdtaddr $fdtfile;" \
694 "bootm $loadaddr - $fdtaddr"
696 #define CONFIG_NFSBOOTCOMMAND \
697 "setenv bootargs root=/dev/nfs rw " \
698 "nfsroot=$serverip:$rootpath " \
699 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
700 "console=$consoledev,$baudrate $othbootargs;" \
701 "tftp $loadaddr $bootfile;" \
702 "tftp $fdtaddr $fdtfile;" \
703 "bootm $loadaddr - $fdtaddr"
705 #define CONFIG_RAMBOOTCOMMAND \
706 "setenv bootargs root=/dev/ram rw " \
707 "console=$consoledev,$baudrate $othbootargs;" \
708 "tftp $ramdiskaddr $ramdiskfile;" \
709 "tftp $loadaddr $bootfile;" \
710 "tftp $fdtaddr $fdtfile;" \
711 "bootm $loadaddr $ramdiskaddr $fdtaddr"
713 #define CONFIG_BOOTCOMMAND CONFIG_HDBOOT
715 #include <asm/fsl_secure_boot.h>
717 #endif /* __CONFIG_H */