git.sur5r.net Git - u-boot/blob - include/configs/P2041RDB.h

   1 /*
   2  * Copyright 2011-2012 Freescale Semiconductor, Inc.
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+
   5  */
   6
   7 /*
   8  * P2041 RDB board configuration file
   9  * Also supports P2040 RDB
  10  */
  11 #ifndef __CONFIG_H
  12 #define __CONFIG_H
  13
  14 #ifdef CONFIG_RAMBOOT_PBL
  15 #define CONFIG_RAMBOOT_TEXT_BASE        CONFIG_SYS_TEXT_BASE
  16 #define CONFIG_RESET_VECTOR_ADDRESS     0xfffffffc
  17 #define CONFIG_SYS_FSL_PBL_PBI board/freescale/corenet_ds/pbi.cfg
  18 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/corenet_ds/rcw_p2041rdb.cfg
  19 #endif
  20
  21 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
  22 /* Set 1M boot space */
  23 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000)
  24 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \
  25                 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR)
  26 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
  27 #endif
  28
  29 /* High Level Configuration Options */
  30 #define CONFIG_SYS_BOOK3E_HV            /* Category E.HV supported */
  31 #define CONFIG_MP                       /* support multiple processors */
  32
  33 #ifndef CONFIG_SYS_TEXT_BASE
  34 #define CONFIG_SYS_TEXT_BASE    0xeff40000
  35 #endif
  36
  37 #ifndef CONFIG_RESET_VECTOR_ADDRESS
  38 #define CONFIG_RESET_VECTOR_ADDRESS     0xeffffffc
  39 #endif
  40
  41 #define CONFIG_SYS_FSL_CPC              /* Corenet Platform Cache */
  42 #define CONFIG_SYS_NUM_CPC              CONFIG_SYS_NUM_DDR_CTLRS
  43 #define CONFIG_PCIE1                    /* PCIE controller 1 */
  44 #define CONFIG_PCIE2                    /* PCIE controller 2 */
  45 #define CONFIG_PCIE3                    /* PCIE controller 3 */
  46 #define CONFIG_FSL_PCI_INIT             /* Use common FSL init code */
  47 #define CONFIG_SYS_PCI_64BIT            /* enable 64-bit PCI resources */
  48
  49 #define CONFIG_SYS_SRIO
  50 #define CONFIG_SRIO1                    /* SRIO port 1 */
  51 #define CONFIG_SRIO2                    /* SRIO port 2 */
  52 #define CONFIG_SRIO_PCIE_BOOT_MASTER
  53 #define CONFIG_SYS_DPAA_RMAN            /* RMan */
  54
  55 #define CONFIG_ENV_OVERWRITE
  56
  57 #ifndef CONFIG_MTD_NOR_FLASH
  58 #else
  59 #define CONFIG_FLASH_CFI_DRIVER
  60 #define CONFIG_SYS_FLASH_CFI
  61 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
  62 #endif
  63
  64 #if defined(CONFIG_SPIFLASH)
  65         #define CONFIG_SYS_EXTRA_ENV_RELOC
  66         #define CONFIG_ENV_SPI_BUS              0
  67         #define CONFIG_ENV_SPI_CS               0
  68         #define CONFIG_ENV_SPI_MAX_HZ           10000000
  69         #define CONFIG_ENV_SPI_MODE             0
  70         #define CONFIG_ENV_SIZE                 0x2000          /* 8KB */
  71         #define CONFIG_ENV_OFFSET               0x100000        /* 1MB */
  72         #define CONFIG_ENV_SECT_SIZE            0x10000
  73 #elif defined(CONFIG_SDCARD)
  74         #define CONFIG_SYS_EXTRA_ENV_RELOC
  75         #define CONFIG_FSL_FIXED_MMC_LOCATION
  76         #define CONFIG_SYS_MMC_ENV_DEV          0
  77         #define CONFIG_ENV_SIZE                 0x2000
  78         #define CONFIG_ENV_OFFSET               (512 * 1658)
  79 #elif defined(CONFIG_NAND)
  80 #define CONFIG_SYS_EXTRA_ENV_RELOC
  81 #define CONFIG_ENV_SIZE                 CONFIG_SYS_NAND_BLOCK_SIZE
  82 #define CONFIG_ENV_OFFSET               (7 * CONFIG_SYS_NAND_BLOCK_SIZE)
  83 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
  84 #define CONFIG_ENV_ADDR         0xffe20000
  85 #define CONFIG_ENV_SIZE         0x2000
  86 #elif defined(CONFIG_ENV_IS_NOWHERE)
  87 #define CONFIG_ENV_SIZE         0x2000
  88 #else
  89         #define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE \
  90                         - CONFIG_ENV_SECT_SIZE)
  91         #define CONFIG_ENV_SIZE         0x2000
  92         #define CONFIG_ENV_SECT_SIZE    0x20000 /* 128K (one sector) */
  93 #endif
  94
  95 #ifndef __ASSEMBLY__
  96 unsigned long get_board_sys_clk(unsigned long dummy);
  97 #endif
  98 #define CONFIG_SYS_CLK_FREQ     get_board_sys_clk(0)
  99
 100 /*
 101  * These can be toggled for performance analysis, otherwise use default.
 102  */
 103 #define CONFIG_SYS_CACHE_STASHING
 104 #define CONFIG_BACKSIDE_L2_CACHE
 105 #define CONFIG_SYS_INIT_L2CSR0          L2CSR0_L2E
 106 #define CONFIG_BTB                      /* toggle branch predition */
 107
 108 #define CONFIG_ENABLE_36BIT_PHYS
 109
 110 #ifdef CONFIG_PHYS_64BIT
 111 #define CONFIG_ADDR_MAP
 112 #define CONFIG_SYS_NUM_ADDR_MAP         64      /* number of TLB1 entries */
 113 #endif
 114
 115 #define CONFIG_POST CONFIG_SYS_POST_MEMORY      /* test POST memory test */
 116 #define CONFIG_SYS_MEMTEST_START        0x00200000      /* memtest works on */
 117 #define CONFIG_SYS_MEMTEST_END          0x00400000
 118 #define CONFIG_SYS_ALT_MEMTEST
 119 #define CONFIG_PANIC_HANG       /* do not reset board on panic */
 120
 121 /*
 122  *  Config the L3 Cache as L3 SRAM
 123  */
 124 #define CONFIG_SYS_INIT_L3_ADDR         CONFIG_RAMBOOT_TEXT_BASE
 125 #ifdef CONFIG_PHYS_64BIT
 126 #define CONFIG_SYS_INIT_L3_ADDR_PHYS    (0xf00000000ull | \
 127                 CONFIG_RAMBOOT_TEXT_BASE)
 128 #else
 129 #define CONFIG_SYS_INIT_L3_ADDR_PHYS    CONFIG_SYS_INIT_L3_ADDR
 130 #endif
 131 #define CONFIG_SYS_L3_SIZE              (1024 << 10)
 132 #define CONFIG_SYS_INIT_L3_END (CONFIG_SYS_INIT_L3_ADDR + CONFIG_SYS_L3_SIZE)
 133
 134 #ifdef CONFIG_PHYS_64BIT
 135 #define CONFIG_SYS_DCSRBAR              0xf0000000
 136 #define CONFIG_SYS_DCSRBAR_PHYS         0xf00000000ull
 137 #endif
 138
 139 /* EEPROM */
 140 #define CONFIG_ID_EEPROM
 141 #define CONFIG_SYS_I2C_EEPROM_NXID
 142 #define CONFIG_SYS_EEPROM_BUS_NUM       0
 143 #define CONFIG_SYS_I2C_EEPROM_ADDR      0x50
 144 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN  1
 145
 146 /*
 147  * DDR Setup
 148  */
 149 #define CONFIG_VERY_BIG_RAM
 150 #define CONFIG_SYS_DDR_SDRAM_BASE       0x00000000
 151 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_SDRAM_BASE
 152
 153 #define CONFIG_DIMM_SLOTS_PER_CTLR      1
 154 #define CONFIG_CHIP_SELECTS_PER_CTRL    (4 * CONFIG_DIMM_SLOTS_PER_CTLR)
 155
 156 #define CONFIG_DDR_SPD
 157
 158 #define CONFIG_SYS_SPD_BUS_NUM  0
 159 #define SPD_EEPROM_ADDRESS      0x52
 160 #define CONFIG_SYS_SDRAM_SIZE   4096    /* for fixed parameter use */
 161
 162 /*
 163  * Local Bus Definitions
 164  */
 165
 166 /* Set the local bus clock 1/8 of platform clock */
 167 #define CONFIG_SYS_LBC_LCRR             LCRR_CLKDIV_8
 168
 169 /*
 170  * This board doesn't have a promjet connector.
 171  * However, it uses commone corenet board LAW and TLB.
 172  * It is necessary to use the same start address with proper offset.
 173  */
 174 #define CONFIG_SYS_FLASH_BASE           0xe0000000
 175 #ifdef CONFIG_PHYS_64BIT
 176 #define CONFIG_SYS_FLASH_BASE_PHYS      0xfe0000000ull
 177 #else
 178 #define CONFIG_SYS_FLASH_BASE_PHYS      CONFIG_SYS_FLASH_BASE
 179 #endif
 180
 181 #define CONFIG_SYS_FLASH_BR_PRELIM \
 182                 (BR_PHYS_ADDR((CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000)) | \
 183                 BR_PS_16 | BR_V)
 184 #define CONFIG_SYS_FLASH_OR_PRELIM \
 185                 ((0xf8000ff7 & ~OR_GPCM_SCY & ~OR_GPCM_EHTR) \
 186                  | OR_GPCM_SCY_8 | OR_GPCM_EHTR_CLEAR)
 187
 188 #define CONFIG_FSL_CPLD
 189 #define CPLD_BASE               0xffdf0000      /* CPLD registers */
 190 #ifdef CONFIG_PHYS_64BIT
 191 #define CPLD_BASE_PHYS          0xfffdf0000ull
 192 #else
 193 #define CPLD_BASE_PHYS          CPLD_BASE
 194 #endif
 195
 196 #define CONFIG_SYS_BR3_PRELIM   (BR_PHYS_ADDR(CPLD_BASE_PHYS) | BR_PS_8 | BR_V)
 197 #define CONFIG_SYS_OR3_PRELIM   0xffffeff7      /* 32KB but only 4k mapped */
 198
 199 #define PIXIS_LBMAP_SWITCH      7
 200 #define PIXIS_LBMAP_MASK        0xf0
 201 #define PIXIS_LBMAP_SHIFT       4
 202 #define PIXIS_LBMAP_ALTBANK     0x40
 203
 204 #define CONFIG_SYS_FLASH_QUIET_TEST
 205 #define CONFIG_FLASH_SHOW_PROGRESS      45 /* count down from 45/5: 9..1 */
 206
 207 #define CONFIG_SYS_MAX_FLASH_BANKS      1               /* number of banks */
 208 #define CONFIG_SYS_MAX_FLASH_SECT       1024            /* sectors per device */
 209 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000           /* Erase Timeout (ms) */
 210 #define CONFIG_SYS_FLASH_WRITE_TOUT     500             /* Write Timeout (ms) */
 211
 212 #define CONFIG_SYS_MONITOR_BASE         CONFIG_SYS_TEXT_BASE
 213
 214 #if defined(CONFIG_RAMBOOT_PBL)
 215 #define CONFIG_SYS_RAMBOOT
 216 #endif
 217
 218 #define CONFIG_NAND_FSL_ELBC
 219 /* Nand Flash */
 220 #ifdef CONFIG_NAND_FSL_ELBC
 221 #define CONFIG_SYS_NAND_BASE            0xffa00000
 222 #ifdef CONFIG_PHYS_64BIT
 223 #define CONFIG_SYS_NAND_BASE_PHYS       0xfffa00000ull
 224 #else
 225 #define CONFIG_SYS_NAND_BASE_PHYS       CONFIG_SYS_NAND_BASE
 226 #endif
 227
 228 #define CONFIG_SYS_NAND_BASE_LIST     {CONFIG_SYS_NAND_BASE}
 229 #define CONFIG_SYS_MAX_NAND_DEVICE      1
 230 #define CONFIG_SYS_NAND_BLOCK_SIZE    (128 * 1024)
 231
 232 /* NAND flash config */
 233 #define CONFIG_SYS_NAND_BR_PRELIM  (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
 234                                | (2<<BR_DECC_SHIFT)    /* Use HW ECC */ \
 235                                | BR_PS_8               /* Port Size = 8 bit */ \
 236                                | BR_MS_FCM             /* MSEL = FCM */ \
 237                                | BR_V)                 /* valid */
 238 #define CONFIG_SYS_NAND_OR_PRELIM  (0xFFFC0000        /* length 256K */ \
 239                                | OR_FCM_PGS            /* Large Page*/ \
 240                                | OR_FCM_CSCT \
 241                                | OR_FCM_CST \
 242                                | OR_FCM_CHT \
 243                                | OR_FCM_SCY_1 \
 244                                | OR_FCM_TRLX \
 245                                | OR_FCM_EHTR)
 246
 247 #ifdef CONFIG_NAND
 248 #define CONFIG_SYS_BR0_PRELIM  CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */
 249 #define CONFIG_SYS_OR0_PRELIM  CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
 250 #define CONFIG_SYS_BR1_PRELIM  CONFIG_SYS_FLASH_BR_PRELIM /* NOR Base Address */
 251 #define CONFIG_SYS_OR1_PRELIM  CONFIG_SYS_FLASH_OR_PRELIM /* NOR Options */
 252 #else
 253 #define CONFIG_SYS_BR0_PRELIM  CONFIG_SYS_FLASH_BR_PRELIM /* NOR Base Address */
 254 #define CONFIG_SYS_OR0_PRELIM  CONFIG_SYS_FLASH_OR_PRELIM /* NOR Options */
 255 #define CONFIG_SYS_BR1_PRELIM  CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */
 256 #define CONFIG_SYS_OR1_PRELIM  CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
 257 #endif
 258 #else
 259 #define CONFIG_SYS_BR0_PRELIM  CONFIG_SYS_FLASH_BR_PRELIM /* NOR Base Address */
 260 #define CONFIG_SYS_OR0_PRELIM  CONFIG_SYS_FLASH_OR_PRELIM /* NOR Options */
 261 #endif /* CONFIG_NAND_FSL_ELBC */
 262
 263 #define CONFIG_SYS_FLASH_EMPTY_INFO
 264 #define CONFIG_SYS_FLASH_AMD_CHECK_DQ7
 265 #define CONFIG_SYS_FLASH_BANKS_LIST     {CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000}
 266
 267 #define CONFIG_BOARD_EARLY_INIT_R       /* call board_early_init_r function */
 268 #define CONFIG_MISC_INIT_R
 269
 270 #define CONFIG_HWCONFIG
 271
 272 /* define to use L1 as initial stack */
 273 #define CONFIG_L1_INIT_RAM
 274 #define CONFIG_SYS_INIT_RAM_LOCK
 275 #define CONFIG_SYS_INIT_RAM_ADDR        0xffd00000      /* Initial L1 address */
 276 #ifdef CONFIG_PHYS_64BIT
 277 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
 278 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR
 279 /* The assembler doesn't like typecast */
 280 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
 281         ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
 282           CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
 283 #else
 284 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS   CONFIG_SYS_INIT_RAM_ADDR
 285 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0
 286 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS
 287 #endif
 288 #define CONFIG_SYS_INIT_RAM_SIZE        0x00004000
 289
 290 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - \
 291                                         GENERATED_GBL_DATA_SIZE)
 292 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 293
 294 #define CONFIG_SYS_MONITOR_LEN          (768 * 1024)
 295 #define CONFIG_SYS_MALLOC_LEN           (1024 * 1024)
 296
 297 /* Serial Port - controlled on board with jumper J8
 298  * open - index 2
 299  * shorted - index 1
 300  */
 301 #define CONFIG_CONS_INDEX       1
 302 #define CONFIG_SYS_NS16550_SERIAL
 303 #define CONFIG_SYS_NS16550_REG_SIZE     1
 304 #define CONFIG_SYS_NS16550_CLK          (get_bus_freq(0)/2)
 305
 306 #define CONFIG_SYS_BAUDRATE_TABLE       \
 307         {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
 308
 309 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
 310 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
 311 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
 312 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
 313
 314 /* I2C */
 315 #define CONFIG_SYS_I2C
 316 #define CONFIG_SYS_I2C_FSL
 317 #define CONFIG_SYS_FSL_I2C_SPEED        400000
 318 #define CONFIG_SYS_FSL_I2C_SLAVE        0x7F
 319 #define CONFIG_SYS_FSL_I2C_OFFSET       0x118000
 320 #define CONFIG_SYS_FSL_I2C2_SPEED       400000
 321 #define CONFIG_SYS_FSL_I2C2_SLAVE       0x7F
 322 #define CONFIG_SYS_FSL_I2C2_OFFSET      0x118100
 323
 324 /*
 325  * RapidIO
 326  */
 327 #define CONFIG_SYS_SRIO1_MEM_VIRT       0xa0000000
 328 #ifdef CONFIG_PHYS_64BIT
 329 #define CONFIG_SYS_SRIO1_MEM_PHYS       0xc20000000ull
 330 #else
 331 #define CONFIG_SYS_SRIO1_MEM_PHYS       0xa0000000
 332 #endif
 333 #define CONFIG_SYS_SRIO1_MEM_SIZE       0x10000000      /* 256M */
 334
 335 #define CONFIG_SYS_SRIO2_MEM_VIRT       0xb0000000
 336 #ifdef CONFIG_PHYS_64BIT
 337 #define CONFIG_SYS_SRIO2_MEM_PHYS       0xc30000000ull
 338 #else
 339 #define CONFIG_SYS_SRIO2_MEM_PHYS       0xb0000000
 340 #endif
 341 #define CONFIG_SYS_SRIO2_MEM_SIZE       0x10000000      /* 256M */
 342
 343 /*
 344  * for slave u-boot IMAGE instored in master memory space,
 345  * PHYS must be aligned based on the SIZE
 346  */
 347 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull
 348 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull
 349 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x100000       /* 1M */
 350 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull
 351 /*
 352  * for slave UCODE and ENV instored in master memory space,
 353  * PHYS must be aligned based on the SIZE
 354  */
 355 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull
 356 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull
 357 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000    /* 256K */
 358
 359 /* slave core release by master*/
 360 #define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4
 361 #define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */
 362
 363 /*
 364  * SRIO_PCIE_BOOT - SLAVE
 365  */
 366 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
 367 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000
 368 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \
 369                 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR)
 370 #endif
 371
 372 /*
 373  * eSPI - Enhanced SPI
 374  */
 375 #define CONFIG_SF_DEFAULT_SPEED         10000000
 376 #define CONFIG_SF_DEFAULT_MODE          0
 377
 378 /*
 379  * General PCI
 380  * Memory space is mapped 1-1, but I/O space must start from 0.
 381  */
 382
 383 /* controller 1, direct to uli, tgtid 3, Base address 20000 */
 384 #define CONFIG_SYS_PCIE1_MEM_VIRT       0x80000000
 385 #ifdef CONFIG_PHYS_64BIT
 386 #define CONFIG_SYS_PCIE1_MEM_BUS        0xe0000000
 387 #define CONFIG_SYS_PCIE1_MEM_PHYS       0xc00000000ull
 388 #else
 389 #define CONFIG_SYS_PCIE1_MEM_BUS        0x80000000
 390 #define CONFIG_SYS_PCIE1_MEM_PHYS       0x80000000
 391 #endif
 392 #define CONFIG_SYS_PCIE1_MEM_SIZE       0x20000000      /* 512M */
 393 #define CONFIG_SYS_PCIE1_IO_VIRT        0xf8000000
 394 #define CONFIG_SYS_PCIE1_IO_BUS         0x00000000
 395 #ifdef CONFIG_PHYS_64BIT
 396 #define CONFIG_SYS_PCIE1_IO_PHYS        0xff8000000ull
 397 #else
 398 #define CONFIG_SYS_PCIE1_IO_PHYS        0xf8000000
 399 #endif
 400 #define CONFIG_SYS_PCIE1_IO_SIZE        0x00010000      /* 64k */
 401
 402 /* controller 2, Slot 2, tgtid 2, Base address 201000 */
 403 #define CONFIG_SYS_PCIE2_MEM_VIRT       0xa0000000
 404 #ifdef CONFIG_PHYS_64BIT
 405 #define CONFIG_SYS_PCIE2_MEM_BUS        0xe0000000
 406 #define CONFIG_SYS_PCIE2_MEM_PHYS       0xc20000000ull
 407 #else
 408 #define CONFIG_SYS_PCIE2_MEM_BUS        0xa0000000
 409 #define CONFIG_SYS_PCIE2_MEM_PHYS       0xa0000000
 410 #endif
 411 #define CONFIG_SYS_PCIE2_MEM_SIZE       0x20000000      /* 512M */
 412 #define CONFIG_SYS_PCIE2_IO_VIRT        0xf8010000
 413 #define CONFIG_SYS_PCIE2_IO_BUS         0x00000000
 414 #ifdef CONFIG_PHYS_64BIT
 415 #define CONFIG_SYS_PCIE2_IO_PHYS        0xff8010000ull
 416 #else
 417 #define CONFIG_SYS_PCIE2_IO_PHYS        0xf8010000
 418 #endif
 419 #define CONFIG_SYS_PCIE2_IO_SIZE        0x00010000      /* 64k */
 420
 421 /* controller 3, Slot 1, tgtid 1, Base address 202000 */
 422 #define CONFIG_SYS_PCIE3_MEM_VIRT       0xc0000000
 423 #ifdef CONFIG_PHYS_64BIT
 424 #define CONFIG_SYS_PCIE3_MEM_BUS        0xe0000000
 425 #define CONFIG_SYS_PCIE3_MEM_PHYS       0xc40000000ull
 426 #else
 427 #define CONFIG_SYS_PCIE3_MEM_BUS        0xc0000000
 428 #define CONFIG_SYS_PCIE3_MEM_PHYS       0xc0000000
 429 #endif
 430 #define CONFIG_SYS_PCIE3_MEM_SIZE       0x20000000      /* 512M */
 431 #define CONFIG_SYS_PCIE3_IO_VIRT        0xf8020000
 432 #define CONFIG_SYS_PCIE3_IO_BUS         0x00000000
 433 #ifdef CONFIG_PHYS_64BIT
 434 #define CONFIG_SYS_PCIE3_IO_PHYS        0xff8020000ull
 435 #else
 436 #define CONFIG_SYS_PCIE3_IO_PHYS        0xf8020000
 437 #endif
 438 #define CONFIG_SYS_PCIE3_IO_SIZE        0x00010000      /* 64k */
 439
 440 /* Qman/Bman */
 441 #define CONFIG_SYS_DPAA_QBMAN           /* Support Q/Bman */
 442 #define CONFIG_SYS_BMAN_NUM_PORTALS     10
 443 #define CONFIG_SYS_BMAN_MEM_BASE        0xf4000000
 444 #ifdef CONFIG_PHYS_64BIT
 445 #define CONFIG_SYS_BMAN_MEM_PHYS        0xff4000000ull
 446 #else
 447 #define CONFIG_SYS_BMAN_MEM_PHYS        CONFIG_SYS_BMAN_MEM_BASE
 448 #endif
 449 #define CONFIG_SYS_BMAN_MEM_SIZE        0x00200000
 450 #define CONFIG_SYS_BMAN_SP_CENA_SIZE    0x4000
 451 #define CONFIG_SYS_BMAN_SP_CINH_SIZE    0x1000
 452 #define CONFIG_SYS_BMAN_CENA_BASE       CONFIG_SYS_BMAN_MEM_BASE
 453 #define CONFIG_SYS_BMAN_CENA_SIZE       (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
 454 #define CONFIG_SYS_BMAN_CINH_BASE       (CONFIG_SYS_BMAN_MEM_BASE + \
 455                                         CONFIG_SYS_BMAN_CENA_SIZE)
 456 #define CONFIG_SYS_BMAN_CINH_SIZE       (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
 457 #define CONFIG_SYS_BMAN_SWP_ISDR_REG    0xE08
 458 #define CONFIG_SYS_QMAN_NUM_PORTALS     10
 459 #define CONFIG_SYS_QMAN_MEM_BASE        0xf4200000
 460 #ifdef CONFIG_PHYS_64BIT
 461 #define CONFIG_SYS_QMAN_MEM_PHYS        0xff4200000ull
 462 #else
 463 #define CONFIG_SYS_QMAN_MEM_PHYS        CONFIG_SYS_QMAN_MEM_BASE
 464 #endif
 465 #define CONFIG_SYS_QMAN_MEM_SIZE        0x00200000
 466 #define CONFIG_SYS_QMAN_SP_CENA_SIZE    0x4000
 467 #define CONFIG_SYS_QMAN_SP_CINH_SIZE    0x1000
 468 #define CONFIG_SYS_QMAN_CENA_BASE       CONFIG_SYS_QMAN_MEM_BASE
 469 #define CONFIG_SYS_QMAN_CENA_SIZE       (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
 470 #define CONFIG_SYS_QMAN_CINH_BASE       (CONFIG_SYS_QMAN_MEM_BASE + \
 471                                         CONFIG_SYS_QMAN_CENA_SIZE)
 472 #define CONFIG_SYS_QMAN_CINH_SIZE       (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
 473 #define CONFIG_SYS_QMAN_SWP_ISDR_REG    0xE08
 474
 475 #define CONFIG_SYS_DPAA_FMAN
 476 #define CONFIG_SYS_DPAA_PME
 477 /* Default address of microcode for the Linux Fman driver */
 478 #if defined(CONFIG_SPIFLASH)
 479 /*
 480  * env is stored at 0x100000, sector size is 0x10000, ucode is stored after
 481  * env, so we got 0x110000.
 482  */
 483 #define CONFIG_SYS_QE_FW_IN_SPIFLASH
 484 #define CONFIG_SYS_FMAN_FW_ADDR 0x110000
 485 #elif defined(CONFIG_SDCARD)
 486 /*
 487  * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
 488  * about 825KB (1650 blocks), Env is stored after the image, and the env size is
 489  * 0x2000 (16 blocks), 8 + 1650 + 16 = 1674, enlarge it to 1680.
 490  */
 491 #define CONFIG_SYS_QE_FMAN_FW_IN_MMC
 492 #define CONFIG_SYS_FMAN_FW_ADDR (512 * 1680)
 493 #elif defined(CONFIG_NAND)
 494 #define CONFIG_SYS_QE_FMAN_FW_IN_NAND
 495 #define CONFIG_SYS_FMAN_FW_ADDR (8 * CONFIG_SYS_NAND_BLOCK_SIZE)
 496 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
 497 /*
 498  * Slave has no ucode locally, it can fetch this from remote. When implementing
 499  * in two corenet boards, slave's ucode could be stored in master's memory
 500  * space, the address can be mapped from slave TLB->slave LAW->
 501  * slave SRIO or PCIE outbound window->master inbound window->
 502  * master LAW->the ucode address in master's memory space.
 503  */
 504 #define CONFIG_SYS_QE_FMAN_FW_IN_REMOTE
 505 #define CONFIG_SYS_FMAN_FW_ADDR 0xFFE00000
 506 #else
 507 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR
 508 #define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000
 509 #endif
 510 #define CONFIG_SYS_QE_FMAN_FW_LENGTH    0x10000
 511 #define CONFIG_SYS_FDT_PAD              (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
 512
 513 #ifdef CONFIG_SYS_DPAA_FMAN
 514 #define CONFIG_FMAN_ENET
 515 #define CONFIG_PHYLIB_10G
 516 #define CONFIG_PHY_VITESSE
 517 #define CONFIG_PHY_TERANETICS
 518 #endif
 519
 520 #ifdef CONFIG_PCI
 521 #define CONFIG_PCI_INDIRECT_BRIDGE
 522
 523 #define CONFIG_PCI_SCAN_SHOW            /* show pci devices on startup */
 524 #endif  /* CONFIG_PCI */
 525
 526 /* SATA */
 527 #define CONFIG_FSL_SATA_V2
 528
 529 #ifdef CONFIG_FSL_SATA_V2
 530 #define CONFIG_FSL_SATA
 531 #define CONFIG_LIBATA
 532
 533 #define CONFIG_SYS_SATA_MAX_DEVICE      2
 534 #define CONFIG_SATA1
 535 #define CONFIG_SYS_SATA1                CONFIG_SYS_MPC85xx_SATA1_ADDR
 536 #define CONFIG_SYS_SATA1_FLAGS          FLAGS_DMA
 537 #define CONFIG_SATA2
 538 #define CONFIG_SYS_SATA2                CONFIG_SYS_MPC85xx_SATA2_ADDR
 539 #define CONFIG_SYS_SATA2_FLAGS          FLAGS_DMA
 540
 541 #define CONFIG_LBA48
 542 #endif
 543
 544 #ifdef CONFIG_FMAN_ENET
 545 #define CONFIG_SYS_FM1_DTSEC1_PHY_ADDR  0x2
 546 #define CONFIG_SYS_FM1_DTSEC2_PHY_ADDR  0x3
 547 #define CONFIG_SYS_FM1_DTSEC3_PHY_ADDR  0x4
 548 #define CONFIG_SYS_FM1_DTSEC4_PHY_ADDR  0x1
 549 #define CONFIG_SYS_FM1_DTSEC5_PHY_ADDR  0x0
 550
 551 #define CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR    0x1c
 552 #define CONFIG_SYS_FM1_DTSEC2_RISER_PHY_ADDR    0x1d
 553 #define CONFIG_SYS_FM1_DTSEC3_RISER_PHY_ADDR    0x1e
 554 #define CONFIG_SYS_FM1_DTSEC4_RISER_PHY_ADDR    0x1f
 555
 556 #define CONFIG_SYS_FM1_10GEC1_PHY_ADDR  0
 557
 558 #define CONFIG_SYS_TBIPA_VALUE  8
 559 #define CONFIG_MII              /* MII PHY management */
 560 #define CONFIG_ETHPRIME         "FM1@DTSEC1"
 561 #endif
 562
 563 /*
 564  * Environment
 565  */
 566 #define CONFIG_LOADS_ECHO               /* echo on for serial download */
 567 #define CONFIG_SYS_LOADS_BAUD_CHANGE    /* allow baudrate change */
 568
 569 /*
 570  * Command line configuration.
 571  */
 572
 573 /*
 574 * USB
 575 */
 576 #define CONFIG_HAS_FSL_DR_USB
 577 #define CONFIG_HAS_FSL_MPH_USB
 578
 579 #if defined(CONFIG_HAS_FSL_DR_USB) || defined(CONFIG_HAS_FSL_MPH_USB)
 580 #define CONFIG_USB_EHCI_FSL
 581 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
 582 #endif
 583
 584 #ifdef CONFIG_MMC
 585 #define CONFIG_FSL_ESDHC
 586 #define CONFIG_SYS_FSL_ESDHC_ADDR       CONFIG_SYS_MPC85xx_ESDHC_ADDR
 587 #define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT
 588 #endif
 589
 590 /*
 591  * Miscellaneous configurable options
 592  */
 593 #define CONFIG_SYS_LONGHELP                     /* undef to save memory */
 594 #define CONFIG_CMDLINE_EDITING                  /* Command-line editing */
 595 #define CONFIG_AUTO_COMPLETE                    /* add autocompletion support */
 596 #define CONFIG_SYS_LOAD_ADDR    0x2000000       /* default load address */
 597 /* Print Buffer Size */
 598 #define CONFIG_SYS_PBSIZE       (CONFIG_SYS_CBSIZE + \
 599                                 sizeof(CONFIG_SYS_PROMPT)+16)
 600 #define CONFIG_SYS_MAXARGS      16              /* max number of command args */
 601 /* Boot Argument Buffer Size */
 602 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE
 603
 604 /*
 605  * For booting Linux, the board info and command line data
 606  * have to be in the first 64 MB of memory, since this is
 607  * the maximum mapped by the Linux kernel during initialization.
 608  */
 609 #define CONFIG_SYS_BOOTMAPSZ    (64 << 20)      /* Initial Memory for Linux */
 610 #define CONFIG_SYS_BOOTM_LEN    (64 << 20)      /* Increase max gunzip size */
 611
 612 #ifdef CONFIG_CMD_KGDB
 613 #define CONFIG_KGDB_BAUDRATE    230400  /* speed to run kgdb serial port */
 614 #endif
 615
 616 /*
 617  * Environment Configuration
 618  */
 619 #define CONFIG_ROOTPATH         "/opt/nfsroot"
 620 #define CONFIG_BOOTFILE         "uImage"
 621 #define CONFIG_UBOOTPATH        u-boot.bin
 622
 623 /* default location for tftp and bootm */
 624 #define CONFIG_LOADADDR         1000000
 625
 626 #define __USB_PHY_TYPE  utmi
 627
 628 #define CONFIG_EXTRA_ENV_SETTINGS                               \
 629         "hwconfig=fsl_ddr:ctlr_intlv=cacheline,"                \
 630         "bank_intlv=cs0_cs1\0"                                  \
 631         "netdev=eth0\0"                                         \
 632         "uboot=" __stringify(CONFIG_UBOOTPATH) "\0"                     \
 633         "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0"             \
 634         "tftpflash=tftpboot $loadaddr $uboot && "               \
 635         "protect off $ubootaddr +$filesize && "                 \
 636         "erase $ubootaddr +$filesize && "                       \
 637         "cp.b $loadaddr $ubootaddr $filesize && "               \
 638         "protect on $ubootaddr +$filesize && "                  \
 639         "cmp.b $loadaddr $ubootaddr $filesize\0"                \
 640         "consoledev=ttyS0\0"                                    \
 641         "usb_phy_type=" __stringify(__USB_PHY_TYPE) "\0"                \
 642         "usb_dr_mode=host\0"                                    \
 643         "ramdiskaddr=2000000\0"                                 \
 644         "ramdiskfile=p2041rdb/ramdisk.uboot\0"                  \
 645         "fdtaddr=1e00000\0"                                     \
 646         "fdtfile=p2041rdb/p2041rdb.dtb\0"                       \
 647         "bdev=sda3\0"
 648
 649 #define CONFIG_HDBOOT                                   \
 650         "setenv bootargs root=/dev/$bdev rw "           \
 651         "console=$consoledev,$baudrate $othbootargs;"   \
 652         "tftp $loadaddr $bootfile;"                     \
 653         "tftp $fdtaddr $fdtfile;"                       \
 654         "bootm $loadaddr - $fdtaddr"
 655
 656 #define CONFIG_NFSBOOTCOMMAND                   \
 657         "setenv bootargs root=/dev/nfs rw "     \
 658         "nfsroot=$serverip:$rootpath "          \
 659         "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
 660         "console=$consoledev,$baudrate $othbootargs;"   \
 661         "tftp $loadaddr $bootfile;"             \
 662         "tftp $fdtaddr $fdtfile;"               \
 663         "bootm $loadaddr - $fdtaddr"
 664
 665 #define CONFIG_RAMBOOTCOMMAND                           \
 666         "setenv bootargs root=/dev/ram rw "             \
 667         "console=$consoledev,$baudrate $othbootargs;"   \
 668         "tftp $ramdiskaddr $ramdiskfile;"               \
 669         "tftp $loadaddr $bootfile;"                     \
 670         "tftp $fdtaddr $fdtfile;"                       \
 671         "bootm $loadaddr $ramdiskaddr $fdtaddr"
 672
 673 #define CONFIG_BOOTCOMMAND              CONFIG_HDBOOT
 674
 675 #include <asm/fsl_secure_boot.h>
 676
 677 #endif  /* __CONFIG_H */