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1 /*
2  * Copyright 2011-2012 Freescale Semiconductor, Inc.
3  *
4  * SPDX-License-Identifier:     GPL-2.0+
5  */
6
7 /*
8  * P2041 RDB board configuration file
9  * Also supports P2040 RDB
10  */
11 #ifndef __CONFIG_H
12 #define __CONFIG_H
13
14 #ifdef CONFIG_RAMBOOT_PBL
15 #define CONFIG_RAMBOOT_TEXT_BASE        CONFIG_SYS_TEXT_BASE
16 #define CONFIG_RESET_VECTOR_ADDRESS     0xfffffffc
17 #define CONFIG_SYS_FSL_PBL_PBI board/freescale/corenet_ds/pbi.cfg
18 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/corenet_ds/rcw_p2041rdb.cfg
19 #endif
20
21 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
22 /* Set 1M boot space */
23 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000)
24 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \
25                 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR)
26 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
27 #endif
28
29 /* High Level Configuration Options */
30 #define CONFIG_SYS_BOOK3E_HV            /* Category E.HV supported */
31 #define CONFIG_MP                       /* support multiple processors */
32
33 #ifndef CONFIG_SYS_TEXT_BASE
34 #define CONFIG_SYS_TEXT_BASE    0xeff40000
35 #endif
36
37 #ifndef CONFIG_RESET_VECTOR_ADDRESS
38 #define CONFIG_RESET_VECTOR_ADDRESS     0xeffffffc
39 #endif
40
41 #define CONFIG_SYS_FSL_CPC              /* Corenet Platform Cache */
42 #define CONFIG_SYS_NUM_CPC              CONFIG_SYS_NUM_DDR_CTLRS
43 #define CONFIG_PCIE1                    /* PCIE controller 1 */
44 #define CONFIG_PCIE2                    /* PCIE controller 2 */
45 #define CONFIG_PCIE3                    /* PCIE controller 3 */
46 #define CONFIG_FSL_PCI_INIT             /* Use common FSL init code */
47 #define CONFIG_SYS_PCI_64BIT            /* enable 64-bit PCI resources */
48
49 #define CONFIG_SYS_SRIO
50 #define CONFIG_SRIO1                    /* SRIO port 1 */
51 #define CONFIG_SRIO2                    /* SRIO port 2 */
52 #define CONFIG_SRIO_PCIE_BOOT_MASTER
53 #define CONFIG_SYS_DPAA_RMAN            /* RMan */
54
55 #define CONFIG_ENV_OVERWRITE
56
57 #ifndef CONFIG_MTD_NOR_FLASH
58 #else
59 #define CONFIG_FLASH_CFI_DRIVER
60 #define CONFIG_SYS_FLASH_CFI
61 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
62 #endif
63
64 #if defined(CONFIG_SPIFLASH)
65         #define CONFIG_SYS_EXTRA_ENV_RELOC
66         #define CONFIG_ENV_SPI_BUS              0
67         #define CONFIG_ENV_SPI_CS               0
68         #define CONFIG_ENV_SPI_MAX_HZ           10000000
69         #define CONFIG_ENV_SPI_MODE             0
70         #define CONFIG_ENV_SIZE                 0x2000          /* 8KB */
71         #define CONFIG_ENV_OFFSET               0x100000        /* 1MB */
72         #define CONFIG_ENV_SECT_SIZE            0x10000
73 #elif defined(CONFIG_SDCARD)
74         #define CONFIG_SYS_EXTRA_ENV_RELOC
75         #define CONFIG_FSL_FIXED_MMC_LOCATION
76         #define CONFIG_SYS_MMC_ENV_DEV          0
77         #define CONFIG_ENV_SIZE                 0x2000
78         #define CONFIG_ENV_OFFSET               (512 * 1658)
79 #elif defined(CONFIG_NAND)
80 #define CONFIG_SYS_EXTRA_ENV_RELOC
81 #define CONFIG_ENV_SIZE                 CONFIG_SYS_NAND_BLOCK_SIZE
82 #define CONFIG_ENV_OFFSET               (7 * CONFIG_SYS_NAND_BLOCK_SIZE)
83 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
84 #define CONFIG_ENV_ADDR         0xffe20000
85 #define CONFIG_ENV_SIZE         0x2000
86 #elif defined(CONFIG_ENV_IS_NOWHERE)
87 #define CONFIG_ENV_SIZE         0x2000
88 #else
89         #define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE \
90                         - CONFIG_ENV_SECT_SIZE)
91         #define CONFIG_ENV_SIZE         0x2000
92         #define CONFIG_ENV_SECT_SIZE    0x20000 /* 128K (one sector) */
93 #endif
94
95 #ifndef __ASSEMBLY__
96 unsigned long get_board_sys_clk(unsigned long dummy);
97 #endif
98 #define CONFIG_SYS_CLK_FREQ     get_board_sys_clk(0)
99
100 /*
101  * These can be toggled for performance analysis, otherwise use default.
102  */
103 #define CONFIG_SYS_CACHE_STASHING
104 #define CONFIG_BACKSIDE_L2_CACHE
105 #define CONFIG_SYS_INIT_L2CSR0          L2CSR0_L2E
106 #define CONFIG_BTB                      /* toggle branch predition */
107
108 #define CONFIG_ENABLE_36BIT_PHYS
109
110 #ifdef CONFIG_PHYS_64BIT
111 #define CONFIG_ADDR_MAP
112 #define CONFIG_SYS_NUM_ADDR_MAP         64      /* number of TLB1 entries */
113 #endif
114
115 #define CONFIG_POST CONFIG_SYS_POST_MEMORY      /* test POST memory test */
116 #define CONFIG_SYS_MEMTEST_START        0x00200000      /* memtest works on */
117 #define CONFIG_SYS_MEMTEST_END          0x00400000
118 #define CONFIG_SYS_ALT_MEMTEST
119
120 /*
121  *  Config the L3 Cache as L3 SRAM
122  */
123 #define CONFIG_SYS_INIT_L3_ADDR         CONFIG_RAMBOOT_TEXT_BASE
124 #ifdef CONFIG_PHYS_64BIT
125 #define CONFIG_SYS_INIT_L3_ADDR_PHYS    (0xf00000000ull | \
126                 CONFIG_RAMBOOT_TEXT_BASE)
127 #else
128 #define CONFIG_SYS_INIT_L3_ADDR_PHYS    CONFIG_SYS_INIT_L3_ADDR
129 #endif
130 #define CONFIG_SYS_L3_SIZE              (1024 << 10)
131 #define CONFIG_SYS_INIT_L3_END (CONFIG_SYS_INIT_L3_ADDR + CONFIG_SYS_L3_SIZE)
132
133 #ifdef CONFIG_PHYS_64BIT
134 #define CONFIG_SYS_DCSRBAR              0xf0000000
135 #define CONFIG_SYS_DCSRBAR_PHYS         0xf00000000ull
136 #endif
137
138 /* EEPROM */
139 #define CONFIG_ID_EEPROM
140 #define CONFIG_SYS_I2C_EEPROM_NXID
141 #define CONFIG_SYS_EEPROM_BUS_NUM       0
142 #define CONFIG_SYS_I2C_EEPROM_ADDR      0x50
143 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN  1
144
145 /*
146  * DDR Setup
147  */
148 #define CONFIG_VERY_BIG_RAM
149 #define CONFIG_SYS_DDR_SDRAM_BASE       0x00000000
150 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_SDRAM_BASE
151
152 #define CONFIG_DIMM_SLOTS_PER_CTLR      1
153 #define CONFIG_CHIP_SELECTS_PER_CTRL    (4 * CONFIG_DIMM_SLOTS_PER_CTLR)
154
155 #define CONFIG_DDR_SPD
156
157 #define CONFIG_SYS_SPD_BUS_NUM  0
158 #define SPD_EEPROM_ADDRESS      0x52
159 #define CONFIG_SYS_SDRAM_SIZE   4096    /* for fixed parameter use */
160
161 /*
162  * Local Bus Definitions
163  */
164
165 /* Set the local bus clock 1/8 of platform clock */
166 #define CONFIG_SYS_LBC_LCRR             LCRR_CLKDIV_8
167
168 /*
169  * This board doesn't have a promjet connector.
170  * However, it uses commone corenet board LAW and TLB.
171  * It is necessary to use the same start address with proper offset.
172  */
173 #define CONFIG_SYS_FLASH_BASE           0xe0000000
174 #ifdef CONFIG_PHYS_64BIT
175 #define CONFIG_SYS_FLASH_BASE_PHYS      0xfe0000000ull
176 #else
177 #define CONFIG_SYS_FLASH_BASE_PHYS      CONFIG_SYS_FLASH_BASE
178 #endif
179
180 #define CONFIG_SYS_FLASH_BR_PRELIM \
181                 (BR_PHYS_ADDR((CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000)) | \
182                 BR_PS_16 | BR_V)
183 #define CONFIG_SYS_FLASH_OR_PRELIM \
184                 ((0xf8000ff7 & ~OR_GPCM_SCY & ~OR_GPCM_EHTR) \
185                  | OR_GPCM_SCY_8 | OR_GPCM_EHTR_CLEAR)
186
187 #define CONFIG_FSL_CPLD
188 #define CPLD_BASE               0xffdf0000      /* CPLD registers */
189 #ifdef CONFIG_PHYS_64BIT
190 #define CPLD_BASE_PHYS          0xfffdf0000ull
191 #else
192 #define CPLD_BASE_PHYS          CPLD_BASE
193 #endif
194
195 #define CONFIG_SYS_BR3_PRELIM   (BR_PHYS_ADDR(CPLD_BASE_PHYS) | BR_PS_8 | BR_V)
196 #define CONFIG_SYS_OR3_PRELIM   0xffffeff7      /* 32KB but only 4k mapped */
197
198 #define PIXIS_LBMAP_SWITCH      7
199 #define PIXIS_LBMAP_MASK        0xf0
200 #define PIXIS_LBMAP_SHIFT       4
201 #define PIXIS_LBMAP_ALTBANK     0x40
202
203 #define CONFIG_SYS_FLASH_QUIET_TEST
204 #define CONFIG_FLASH_SHOW_PROGRESS      45 /* count down from 45/5: 9..1 */
205
206 #define CONFIG_SYS_MAX_FLASH_BANKS      1               /* number of banks */
207 #define CONFIG_SYS_MAX_FLASH_SECT       1024            /* sectors per device */
208 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000           /* Erase Timeout (ms) */
209 #define CONFIG_SYS_FLASH_WRITE_TOUT     500             /* Write Timeout (ms) */
210
211 #define CONFIG_SYS_MONITOR_BASE         CONFIG_SYS_TEXT_BASE
212
213 #if defined(CONFIG_RAMBOOT_PBL)
214 #define CONFIG_SYS_RAMBOOT
215 #endif
216
217 #define CONFIG_NAND_FSL_ELBC
218 /* Nand Flash */
219 #ifdef CONFIG_NAND_FSL_ELBC
220 #define CONFIG_SYS_NAND_BASE            0xffa00000
221 #ifdef CONFIG_PHYS_64BIT
222 #define CONFIG_SYS_NAND_BASE_PHYS       0xfffa00000ull
223 #else
224 #define CONFIG_SYS_NAND_BASE_PHYS       CONFIG_SYS_NAND_BASE
225 #endif
226
227 #define CONFIG_SYS_NAND_BASE_LIST     {CONFIG_SYS_NAND_BASE}
228 #define CONFIG_SYS_MAX_NAND_DEVICE      1
229 #define CONFIG_SYS_NAND_BLOCK_SIZE    (128 * 1024)
230
231 /* NAND flash config */
232 #define CONFIG_SYS_NAND_BR_PRELIM  (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
233                                | (2<<BR_DECC_SHIFT)    /* Use HW ECC */ \
234                                | BR_PS_8               /* Port Size = 8 bit */ \
235                                | BR_MS_FCM             /* MSEL = FCM */ \
236                                | BR_V)                 /* valid */
237 #define CONFIG_SYS_NAND_OR_PRELIM  (0xFFFC0000        /* length 256K */ \
238                                | OR_FCM_PGS            /* Large Page*/ \
239                                | OR_FCM_CSCT \
240                                | OR_FCM_CST \
241                                | OR_FCM_CHT \
242                                | OR_FCM_SCY_1 \
243                                | OR_FCM_TRLX \
244                                | OR_FCM_EHTR)
245
246 #ifdef CONFIG_NAND
247 #define CONFIG_SYS_BR0_PRELIM  CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */
248 #define CONFIG_SYS_OR0_PRELIM  CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
249 #define CONFIG_SYS_BR1_PRELIM  CONFIG_SYS_FLASH_BR_PRELIM /* NOR Base Address */
250 #define CONFIG_SYS_OR1_PRELIM  CONFIG_SYS_FLASH_OR_PRELIM /* NOR Options */
251 #else
252 #define CONFIG_SYS_BR0_PRELIM  CONFIG_SYS_FLASH_BR_PRELIM /* NOR Base Address */
253 #define CONFIG_SYS_OR0_PRELIM  CONFIG_SYS_FLASH_OR_PRELIM /* NOR Options */
254 #define CONFIG_SYS_BR1_PRELIM  CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */
255 #define CONFIG_SYS_OR1_PRELIM  CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
256 #endif
257 #else
258 #define CONFIG_SYS_BR0_PRELIM  CONFIG_SYS_FLASH_BR_PRELIM /* NOR Base Address */
259 #define CONFIG_SYS_OR0_PRELIM  CONFIG_SYS_FLASH_OR_PRELIM /* NOR Options */
260 #endif /* CONFIG_NAND_FSL_ELBC */
261
262 #define CONFIG_SYS_FLASH_EMPTY_INFO
263 #define CONFIG_SYS_FLASH_AMD_CHECK_DQ7
264 #define CONFIG_SYS_FLASH_BANKS_LIST     {CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000}
265
266 #define CONFIG_BOARD_EARLY_INIT_R       /* call board_early_init_r function */
267 #define CONFIG_MISC_INIT_R
268
269 #define CONFIG_HWCONFIG
270
271 /* define to use L1 as initial stack */
272 #define CONFIG_L1_INIT_RAM
273 #define CONFIG_SYS_INIT_RAM_LOCK
274 #define CONFIG_SYS_INIT_RAM_ADDR        0xffd00000      /* Initial L1 address */
275 #ifdef CONFIG_PHYS_64BIT
276 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
277 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR
278 /* The assembler doesn't like typecast */
279 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
280         ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
281           CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
282 #else
283 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS   CONFIG_SYS_INIT_RAM_ADDR
284 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0
285 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS
286 #endif
287 #define CONFIG_SYS_INIT_RAM_SIZE        0x00004000
288
289 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - \
290                                         GENERATED_GBL_DATA_SIZE)
291 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
292
293 #define CONFIG_SYS_MONITOR_LEN          (768 * 1024)
294 #define CONFIG_SYS_MALLOC_LEN           (1024 * 1024)
295
296 /* Serial Port - controlled on board with jumper J8
297  * open - index 2
298  * shorted - index 1
299  */
300 #define CONFIG_CONS_INDEX       1
301 #define CONFIG_SYS_NS16550_SERIAL
302 #define CONFIG_SYS_NS16550_REG_SIZE     1
303 #define CONFIG_SYS_NS16550_CLK          (get_bus_freq(0)/2)
304
305 #define CONFIG_SYS_BAUDRATE_TABLE       \
306         {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
307
308 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
309 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
310 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
311 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
312
313 /* I2C */
314 #define CONFIG_SYS_I2C
315 #define CONFIG_SYS_I2C_FSL
316 #define CONFIG_SYS_FSL_I2C_SPEED        400000
317 #define CONFIG_SYS_FSL_I2C_SLAVE        0x7F
318 #define CONFIG_SYS_FSL_I2C_OFFSET       0x118000
319 #define CONFIG_SYS_FSL_I2C2_SPEED       400000
320 #define CONFIG_SYS_FSL_I2C2_SLAVE       0x7F
321 #define CONFIG_SYS_FSL_I2C2_OFFSET      0x118100
322
323 /*
324  * RapidIO
325  */
326 #define CONFIG_SYS_SRIO1_MEM_VIRT       0xa0000000
327 #ifdef CONFIG_PHYS_64BIT
328 #define CONFIG_SYS_SRIO1_MEM_PHYS       0xc20000000ull
329 #else
330 #define CONFIG_SYS_SRIO1_MEM_PHYS       0xa0000000
331 #endif
332 #define CONFIG_SYS_SRIO1_MEM_SIZE       0x10000000      /* 256M */
333
334 #define CONFIG_SYS_SRIO2_MEM_VIRT       0xb0000000
335 #ifdef CONFIG_PHYS_64BIT
336 #define CONFIG_SYS_SRIO2_MEM_PHYS       0xc30000000ull
337 #else
338 #define CONFIG_SYS_SRIO2_MEM_PHYS       0xb0000000
339 #endif
340 #define CONFIG_SYS_SRIO2_MEM_SIZE       0x10000000      /* 256M */
341
342 /*
343  * for slave u-boot IMAGE instored in master memory space,
344  * PHYS must be aligned based on the SIZE
345  */
346 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull
347 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull
348 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x100000       /* 1M */
349 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull
350 /*
351  * for slave UCODE and ENV instored in master memory space,
352  * PHYS must be aligned based on the SIZE
353  */
354 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull
355 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull
356 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000    /* 256K */
357
358 /* slave core release by master*/
359 #define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4
360 #define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */
361
362 /*
363  * SRIO_PCIE_BOOT - SLAVE
364  */
365 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
366 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000
367 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \
368                 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR)
369 #endif
370
371 /*
372  * eSPI - Enhanced SPI
373  */
374 #define CONFIG_SF_DEFAULT_SPEED         10000000
375 #define CONFIG_SF_DEFAULT_MODE          0
376
377 /*
378  * General PCI
379  * Memory space is mapped 1-1, but I/O space must start from 0.
380  */
381
382 /* controller 1, direct to uli, tgtid 3, Base address 20000 */
383 #define CONFIG_SYS_PCIE1_MEM_VIRT       0x80000000
384 #ifdef CONFIG_PHYS_64BIT
385 #define CONFIG_SYS_PCIE1_MEM_BUS        0xe0000000
386 #define CONFIG_SYS_PCIE1_MEM_PHYS       0xc00000000ull
387 #else
388 #define CONFIG_SYS_PCIE1_MEM_BUS        0x80000000
389 #define CONFIG_SYS_PCIE1_MEM_PHYS       0x80000000
390 #endif
391 #define CONFIG_SYS_PCIE1_MEM_SIZE       0x20000000      /* 512M */
392 #define CONFIG_SYS_PCIE1_IO_VIRT        0xf8000000
393 #define CONFIG_SYS_PCIE1_IO_BUS         0x00000000
394 #ifdef CONFIG_PHYS_64BIT
395 #define CONFIG_SYS_PCIE1_IO_PHYS        0xff8000000ull
396 #else
397 #define CONFIG_SYS_PCIE1_IO_PHYS        0xf8000000
398 #endif
399 #define CONFIG_SYS_PCIE1_IO_SIZE        0x00010000      /* 64k */
400
401 /* controller 2, Slot 2, tgtid 2, Base address 201000 */
402 #define CONFIG_SYS_PCIE2_MEM_VIRT       0xa0000000
403 #ifdef CONFIG_PHYS_64BIT
404 #define CONFIG_SYS_PCIE2_MEM_BUS        0xe0000000
405 #define CONFIG_SYS_PCIE2_MEM_PHYS       0xc20000000ull
406 #else
407 #define CONFIG_SYS_PCIE2_MEM_BUS        0xa0000000
408 #define CONFIG_SYS_PCIE2_MEM_PHYS       0xa0000000
409 #endif
410 #define CONFIG_SYS_PCIE2_MEM_SIZE       0x20000000      /* 512M */
411 #define CONFIG_SYS_PCIE2_IO_VIRT        0xf8010000
412 #define CONFIG_SYS_PCIE2_IO_BUS         0x00000000
413 #ifdef CONFIG_PHYS_64BIT
414 #define CONFIG_SYS_PCIE2_IO_PHYS        0xff8010000ull
415 #else
416 #define CONFIG_SYS_PCIE2_IO_PHYS        0xf8010000
417 #endif
418 #define CONFIG_SYS_PCIE2_IO_SIZE        0x00010000      /* 64k */
419
420 /* controller 3, Slot 1, tgtid 1, Base address 202000 */
421 #define CONFIG_SYS_PCIE3_MEM_VIRT       0xc0000000
422 #ifdef CONFIG_PHYS_64BIT
423 #define CONFIG_SYS_PCIE3_MEM_BUS        0xe0000000
424 #define CONFIG_SYS_PCIE3_MEM_PHYS       0xc40000000ull
425 #else
426 #define CONFIG_SYS_PCIE3_MEM_BUS        0xc0000000
427 #define CONFIG_SYS_PCIE3_MEM_PHYS       0xc0000000
428 #endif
429 #define CONFIG_SYS_PCIE3_MEM_SIZE       0x20000000      /* 512M */
430 #define CONFIG_SYS_PCIE3_IO_VIRT        0xf8020000
431 #define CONFIG_SYS_PCIE3_IO_BUS         0x00000000
432 #ifdef CONFIG_PHYS_64BIT
433 #define CONFIG_SYS_PCIE3_IO_PHYS        0xff8020000ull
434 #else
435 #define CONFIG_SYS_PCIE3_IO_PHYS        0xf8020000
436 #endif
437 #define CONFIG_SYS_PCIE3_IO_SIZE        0x00010000      /* 64k */
438
439 /* Qman/Bman */
440 #define CONFIG_SYS_DPAA_QBMAN           /* Support Q/Bman */
441 #define CONFIG_SYS_BMAN_NUM_PORTALS     10
442 #define CONFIG_SYS_BMAN_MEM_BASE        0xf4000000
443 #ifdef CONFIG_PHYS_64BIT
444 #define CONFIG_SYS_BMAN_MEM_PHYS        0xff4000000ull
445 #else
446 #define CONFIG_SYS_BMAN_MEM_PHYS        CONFIG_SYS_BMAN_MEM_BASE
447 #endif
448 #define CONFIG_SYS_BMAN_MEM_SIZE        0x00200000
449 #define CONFIG_SYS_BMAN_SP_CENA_SIZE    0x4000
450 #define CONFIG_SYS_BMAN_SP_CINH_SIZE    0x1000
451 #define CONFIG_SYS_BMAN_CENA_BASE       CONFIG_SYS_BMAN_MEM_BASE
452 #define CONFIG_SYS_BMAN_CENA_SIZE       (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
453 #define CONFIG_SYS_BMAN_CINH_BASE       (CONFIG_SYS_BMAN_MEM_BASE + \
454                                         CONFIG_SYS_BMAN_CENA_SIZE)
455 #define CONFIG_SYS_BMAN_CINH_SIZE       (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
456 #define CONFIG_SYS_BMAN_SWP_ISDR_REG    0xE08
457 #define CONFIG_SYS_QMAN_NUM_PORTALS     10
458 #define CONFIG_SYS_QMAN_MEM_BASE        0xf4200000
459 #ifdef CONFIG_PHYS_64BIT
460 #define CONFIG_SYS_QMAN_MEM_PHYS        0xff4200000ull
461 #else
462 #define CONFIG_SYS_QMAN_MEM_PHYS        CONFIG_SYS_QMAN_MEM_BASE
463 #endif
464 #define CONFIG_SYS_QMAN_MEM_SIZE        0x00200000
465 #define CONFIG_SYS_QMAN_SP_CENA_SIZE    0x4000
466 #define CONFIG_SYS_QMAN_SP_CINH_SIZE    0x1000
467 #define CONFIG_SYS_QMAN_CENA_BASE       CONFIG_SYS_QMAN_MEM_BASE
468 #define CONFIG_SYS_QMAN_CENA_SIZE       (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
469 #define CONFIG_SYS_QMAN_CINH_BASE       (CONFIG_SYS_QMAN_MEM_BASE + \
470                                         CONFIG_SYS_QMAN_CENA_SIZE)
471 #define CONFIG_SYS_QMAN_CINH_SIZE       (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
472 #define CONFIG_SYS_QMAN_SWP_ISDR_REG    0xE08
473
474 #define CONFIG_SYS_DPAA_FMAN
475 #define CONFIG_SYS_DPAA_PME
476 /* Default address of microcode for the Linux Fman driver */
477 #if defined(CONFIG_SPIFLASH)
478 /*
479  * env is stored at 0x100000, sector size is 0x10000, ucode is stored after
480  * env, so we got 0x110000.
481  */
482 #define CONFIG_SYS_QE_FW_IN_SPIFLASH
483 #define CONFIG_SYS_FMAN_FW_ADDR 0x110000
484 #elif defined(CONFIG_SDCARD)
485 /*
486  * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
487  * about 825KB (1650 blocks), Env is stored after the image, and the env size is
488  * 0x2000 (16 blocks), 8 + 1650 + 16 = 1674, enlarge it to 1680.
489  */
490 #define CONFIG_SYS_QE_FMAN_FW_IN_MMC
491 #define CONFIG_SYS_FMAN_FW_ADDR (512 * 1680)
492 #elif defined(CONFIG_NAND)
493 #define CONFIG_SYS_QE_FMAN_FW_IN_NAND
494 #define CONFIG_SYS_FMAN_FW_ADDR (8 * CONFIG_SYS_NAND_BLOCK_SIZE)
495 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
496 /*
497  * Slave has no ucode locally, it can fetch this from remote. When implementing
498  * in two corenet boards, slave's ucode could be stored in master's memory
499  * space, the address can be mapped from slave TLB->slave LAW->
500  * slave SRIO or PCIE outbound window->master inbound window->
501  * master LAW->the ucode address in master's memory space.
502  */
503 #define CONFIG_SYS_QE_FMAN_FW_IN_REMOTE
504 #define CONFIG_SYS_FMAN_FW_ADDR 0xFFE00000
505 #else
506 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR
507 #define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000
508 #endif
509 #define CONFIG_SYS_QE_FMAN_FW_LENGTH    0x10000
510 #define CONFIG_SYS_FDT_PAD              (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
511
512 #ifdef CONFIG_SYS_DPAA_FMAN
513 #define CONFIG_FMAN_ENET
514 #define CONFIG_PHYLIB_10G
515 #define CONFIG_PHY_VITESSE
516 #define CONFIG_PHY_TERANETICS
517 #endif
518
519 #ifdef CONFIG_PCI
520 #define CONFIG_PCI_INDIRECT_BRIDGE
521
522 #define CONFIG_PCI_SCAN_SHOW            /* show pci devices on startup */
523 #endif  /* CONFIG_PCI */
524
525 /* SATA */
526 #define CONFIG_FSL_SATA_V2
527
528 #ifdef CONFIG_FSL_SATA_V2
529 #define CONFIG_SYS_SATA_MAX_DEVICE      2
530 #define CONFIG_SATA1
531 #define CONFIG_SYS_SATA1                CONFIG_SYS_MPC85xx_SATA1_ADDR
532 #define CONFIG_SYS_SATA1_FLAGS          FLAGS_DMA
533 #define CONFIG_SATA2
534 #define CONFIG_SYS_SATA2                CONFIG_SYS_MPC85xx_SATA2_ADDR
535 #define CONFIG_SYS_SATA2_FLAGS          FLAGS_DMA
536
537 #define CONFIG_LBA48
538 #endif
539
540 #ifdef CONFIG_FMAN_ENET
541 #define CONFIG_SYS_FM1_DTSEC1_PHY_ADDR  0x2
542 #define CONFIG_SYS_FM1_DTSEC2_PHY_ADDR  0x3
543 #define CONFIG_SYS_FM1_DTSEC3_PHY_ADDR  0x4
544 #define CONFIG_SYS_FM1_DTSEC4_PHY_ADDR  0x1
545 #define CONFIG_SYS_FM1_DTSEC5_PHY_ADDR  0x0
546
547 #define CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR    0x1c
548 #define CONFIG_SYS_FM1_DTSEC2_RISER_PHY_ADDR    0x1d
549 #define CONFIG_SYS_FM1_DTSEC3_RISER_PHY_ADDR    0x1e
550 #define CONFIG_SYS_FM1_DTSEC4_RISER_PHY_ADDR    0x1f
551
552 #define CONFIG_SYS_FM1_10GEC1_PHY_ADDR  0
553
554 #define CONFIG_SYS_TBIPA_VALUE  8
555 #define CONFIG_MII              /* MII PHY management */
556 #define CONFIG_ETHPRIME         "FM1@DTSEC1"
557 #endif
558
559 /*
560  * Environment
561  */
562 #define CONFIG_LOADS_ECHO               /* echo on for serial download */
563 #define CONFIG_SYS_LOADS_BAUD_CHANGE    /* allow baudrate change */
564
565 /*
566  * Command line configuration.
567  */
568
569 /*
570 * USB
571 */
572 #define CONFIG_HAS_FSL_DR_USB
573 #define CONFIG_HAS_FSL_MPH_USB
574
575 #if defined(CONFIG_HAS_FSL_DR_USB) || defined(CONFIG_HAS_FSL_MPH_USB)
576 #define CONFIG_USB_EHCI_FSL
577 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
578 #endif
579
580 #ifdef CONFIG_MMC
581 #define CONFIG_FSL_ESDHC
582 #define CONFIG_SYS_FSL_ESDHC_ADDR       CONFIG_SYS_MPC85xx_ESDHC_ADDR
583 #define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT
584 #endif
585
586 /*
587  * Miscellaneous configurable options
588  */
589 #define CONFIG_SYS_LONGHELP                     /* undef to save memory */
590 #define CONFIG_CMDLINE_EDITING                  /* Command-line editing */
591 #define CONFIG_AUTO_COMPLETE                    /* add autocompletion support */
592 #define CONFIG_SYS_LOAD_ADDR    0x2000000       /* default load address */
593
594 /*
595  * For booting Linux, the board info and command line data
596  * have to be in the first 64 MB of memory, since this is
597  * the maximum mapped by the Linux kernel during initialization.
598  */
599 #define CONFIG_SYS_BOOTMAPSZ    (64 << 20)      /* Initial Memory for Linux */
600 #define CONFIG_SYS_BOOTM_LEN    (64 << 20)      /* Increase max gunzip size */
601
602 #ifdef CONFIG_CMD_KGDB
603 #define CONFIG_KGDB_BAUDRATE    230400  /* speed to run kgdb serial port */
604 #endif
605
606 /*
607  * Environment Configuration
608  */
609 #define CONFIG_ROOTPATH         "/opt/nfsroot"
610 #define CONFIG_BOOTFILE         "uImage"
611 #define CONFIG_UBOOTPATH        u-boot.bin
612
613 /* default location for tftp and bootm */
614 #define CONFIG_LOADADDR         1000000
615
616 #define __USB_PHY_TYPE  utmi
617
618 #define CONFIG_EXTRA_ENV_SETTINGS                               \
619         "hwconfig=fsl_ddr:ctlr_intlv=cacheline,"                \
620         "bank_intlv=cs0_cs1\0"                                  \
621         "netdev=eth0\0"                                         \
622         "uboot=" __stringify(CONFIG_UBOOTPATH) "\0"                     \
623         "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0"             \
624         "tftpflash=tftpboot $loadaddr $uboot && "               \
625         "protect off $ubootaddr +$filesize && "                 \
626         "erase $ubootaddr +$filesize && "                       \
627         "cp.b $loadaddr $ubootaddr $filesize && "               \
628         "protect on $ubootaddr +$filesize && "                  \
629         "cmp.b $loadaddr $ubootaddr $filesize\0"                \
630         "consoledev=ttyS0\0"                                    \
631         "usb_phy_type=" __stringify(__USB_PHY_TYPE) "\0"                \
632         "usb_dr_mode=host\0"                                    \
633         "ramdiskaddr=2000000\0"                                 \
634         "ramdiskfile=p2041rdb/ramdisk.uboot\0"                  \
635         "fdtaddr=1e00000\0"                                     \
636         "fdtfile=p2041rdb/p2041rdb.dtb\0"                       \
637         "bdev=sda3\0"
638
639 #define CONFIG_HDBOOT                                   \
640         "setenv bootargs root=/dev/$bdev rw "           \
641         "console=$consoledev,$baudrate $othbootargs;"   \
642         "tftp $loadaddr $bootfile;"                     \
643         "tftp $fdtaddr $fdtfile;"                       \
644         "bootm $loadaddr - $fdtaddr"
645
646 #define CONFIG_NFSBOOTCOMMAND                   \
647         "setenv bootargs root=/dev/nfs rw "     \
648         "nfsroot=$serverip:$rootpath "          \
649         "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
650         "console=$consoledev,$baudrate $othbootargs;"   \
651         "tftp $loadaddr $bootfile;"             \
652         "tftp $fdtaddr $fdtfile;"               \
653         "bootm $loadaddr - $fdtaddr"
654
655 #define CONFIG_RAMBOOTCOMMAND                           \
656         "setenv bootargs root=/dev/ram rw "             \
657         "console=$consoledev,$baudrate $othbootargs;"   \
658         "tftp $ramdiskaddr $ramdiskfile;"               \
659         "tftp $loadaddr $bootfile;"                     \
660         "tftp $fdtaddr $fdtfile;"                       \
661         "bootm $loadaddr $ramdiskaddr $fdtaddr"
662
663 #define CONFIG_BOOTCOMMAND              CONFIG_HDBOOT
664
665 #include <asm/fsl_secure_boot.h>
666
667 #endif  /* __CONFIG_H */