git.sur5r.net Git - u-boot/blob - include/configs/P2041RDB.h

   1 /*
   2  * Copyright 2011-2012 Freescale Semiconductor, Inc.
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+
   5  */
   6
   7 /*
   8  * P2041 RDB board configuration file
   9  * Also supports P2040 RDB
  10  */
  11 #ifndef __CONFIG_H
  12 #define __CONFIG_H
  13
  14 #ifdef CONFIG_RAMBOOT_PBL
  15 #define CONFIG_RAMBOOT_TEXT_BASE        CONFIG_SYS_TEXT_BASE
  16 #define CONFIG_RESET_VECTOR_ADDRESS     0xfffffffc
  17 #define CONFIG_SYS_FSL_PBL_PBI board/freescale/corenet_ds/pbi.cfg
  18 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/corenet_ds/rcw_p2041rdb.cfg
  19 #endif
  20
  21 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
  22 /* Set 1M boot space */
  23 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000)
  24 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \
  25                 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR)
  26 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
  27 #endif
  28
  29 /* High Level Configuration Options */
  30 #define CONFIG_SYS_BOOK3E_HV            /* Category E.HV supported */
  31 #define CONFIG_MP                       /* support multiple processors */
  32
  33 #ifndef CONFIG_SYS_TEXT_BASE
  34 #define CONFIG_SYS_TEXT_BASE    0xeff40000
  35 #endif
  36
  37 #ifndef CONFIG_RESET_VECTOR_ADDRESS
  38 #define CONFIG_RESET_VECTOR_ADDRESS     0xeffffffc
  39 #endif
  40
  41 #define CONFIG_SYS_FSL_CPC              /* Corenet Platform Cache */
  42 #define CONFIG_SYS_NUM_CPC              CONFIG_SYS_NUM_DDR_CTLRS
  43 #define CONFIG_PCIE1                    /* PCIE controller 1 */
  44 #define CONFIG_PCIE2                    /* PCIE controller 2 */
  45 #define CONFIG_PCIE3                    /* PCIE controller 3 */
  46 #define CONFIG_FSL_PCI_INIT             /* Use common FSL init code */
  47 #define CONFIG_SYS_PCI_64BIT            /* enable 64-bit PCI resources */
  48
  49 #define CONFIG_SYS_SRIO
  50 #define CONFIG_SRIO1                    /* SRIO port 1 */
  51 #define CONFIG_SRIO2                    /* SRIO port 2 */
  52 #define CONFIG_SRIO_PCIE_BOOT_MASTER
  53 #define CONFIG_SYS_DPAA_RMAN            /* RMan */
  54
  55 #define CONFIG_ENV_OVERWRITE
  56
  57 #ifndef CONFIG_MTD_NOR_FLASH
  58 #if !defined(CONFIG_RAMBOOT_PBL) && !defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
  59 #define CONFIG_ENV_IS_NOWHERE
  60 #endif
  61 #else
  62 #define CONFIG_FLASH_CFI_DRIVER
  63 #define CONFIG_SYS_FLASH_CFI
  64 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
  65 #endif
  66
  67 #if defined(CONFIG_SPIFLASH)
  68         #define CONFIG_SYS_EXTRA_ENV_RELOC
  69         #define CONFIG_ENV_IS_IN_SPI_FLASH
  70         #define CONFIG_ENV_SPI_BUS              0
  71         #define CONFIG_ENV_SPI_CS               0
  72         #define CONFIG_ENV_SPI_MAX_HZ           10000000
  73         #define CONFIG_ENV_SPI_MODE             0
  74         #define CONFIG_ENV_SIZE                 0x2000          /* 8KB */
  75         #define CONFIG_ENV_OFFSET               0x100000        /* 1MB */
  76         #define CONFIG_ENV_SECT_SIZE            0x10000
  77 #elif defined(CONFIG_SDCARD)
  78         #define CONFIG_SYS_EXTRA_ENV_RELOC
  79         #define CONFIG_ENV_IS_IN_MMC
  80         #define CONFIG_FSL_FIXED_MMC_LOCATION
  81         #define CONFIG_SYS_MMC_ENV_DEV          0
  82         #define CONFIG_ENV_SIZE                 0x2000
  83         #define CONFIG_ENV_OFFSET               (512 * 1658)
  84 #elif defined(CONFIG_NAND)
  85 #define CONFIG_SYS_EXTRA_ENV_RELOC
  86 #define CONFIG_ENV_IS_IN_NAND
  87 #define CONFIG_ENV_SIZE                 CONFIG_SYS_NAND_BLOCK_SIZE
  88 #define CONFIG_ENV_OFFSET               (7 * CONFIG_SYS_NAND_BLOCK_SIZE)
  89 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
  90 #define CONFIG_ENV_IS_IN_REMOTE
  91 #define CONFIG_ENV_ADDR         0xffe20000
  92 #define CONFIG_ENV_SIZE         0x2000
  93 #elif defined(CONFIG_ENV_IS_NOWHERE)
  94 #define CONFIG_ENV_SIZE         0x2000
  95 #else
  96         #define CONFIG_ENV_IS_IN_FLASH
  97         #define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE \
  98                         - CONFIG_ENV_SECT_SIZE)
  99         #define CONFIG_ENV_SIZE         0x2000
 100         #define CONFIG_ENV_SECT_SIZE    0x20000 /* 128K (one sector) */
 101 #endif
 102
 103 #ifndef __ASSEMBLY__
 104 unsigned long get_board_sys_clk(unsigned long dummy);
 105 #endif
 106 #define CONFIG_SYS_CLK_FREQ     get_board_sys_clk(0)
 107
 108 /*
 109  * These can be toggled for performance analysis, otherwise use default.
 110  */
 111 #define CONFIG_SYS_CACHE_STASHING
 112 #define CONFIG_BACKSIDE_L2_CACHE
 113 #define CONFIG_SYS_INIT_L2CSR0          L2CSR0_L2E
 114 #define CONFIG_BTB                      /* toggle branch predition */
 115
 116 #define CONFIG_ENABLE_36BIT_PHYS
 117
 118 #ifdef CONFIG_PHYS_64BIT
 119 #define CONFIG_ADDR_MAP
 120 #define CONFIG_SYS_NUM_ADDR_MAP         64      /* number of TLB1 entries */
 121 #endif
 122
 123 #define CONFIG_POST CONFIG_SYS_POST_MEMORY      /* test POST memory test */
 124 #define CONFIG_SYS_MEMTEST_START        0x00200000      /* memtest works on */
 125 #define CONFIG_SYS_MEMTEST_END          0x00400000
 126 #define CONFIG_SYS_ALT_MEMTEST
 127 #define CONFIG_PANIC_HANG       /* do not reset board on panic */
 128
 129 /*
 130  *  Config the L3 Cache as L3 SRAM
 131  */
 132 #define CONFIG_SYS_INIT_L3_ADDR         CONFIG_RAMBOOT_TEXT_BASE
 133 #ifdef CONFIG_PHYS_64BIT
 134 #define CONFIG_SYS_INIT_L3_ADDR_PHYS    (0xf00000000ull | \
 135                 CONFIG_RAMBOOT_TEXT_BASE)
 136 #else
 137 #define CONFIG_SYS_INIT_L3_ADDR_PHYS    CONFIG_SYS_INIT_L3_ADDR
 138 #endif
 139 #define CONFIG_SYS_L3_SIZE              (1024 << 10)
 140 #define CONFIG_SYS_INIT_L3_END (CONFIG_SYS_INIT_L3_ADDR + CONFIG_SYS_L3_SIZE)
 141
 142 #ifdef CONFIG_PHYS_64BIT
 143 #define CONFIG_SYS_DCSRBAR              0xf0000000
 144 #define CONFIG_SYS_DCSRBAR_PHYS         0xf00000000ull
 145 #endif
 146
 147 /* EEPROM */
 148 #define CONFIG_ID_EEPROM
 149 #define CONFIG_SYS_I2C_EEPROM_NXID
 150 #define CONFIG_SYS_EEPROM_BUS_NUM       0
 151 #define CONFIG_SYS_I2C_EEPROM_ADDR      0x50
 152 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN  1
 153
 154 /*
 155  * DDR Setup
 156  */
 157 #define CONFIG_VERY_BIG_RAM
 158 #define CONFIG_SYS_DDR_SDRAM_BASE       0x00000000
 159 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_SDRAM_BASE
 160
 161 #define CONFIG_DIMM_SLOTS_PER_CTLR      1
 162 #define CONFIG_CHIP_SELECTS_PER_CTRL    (4 * CONFIG_DIMM_SLOTS_PER_CTLR)
 163
 164 #define CONFIG_DDR_SPD
 165
 166 #define CONFIG_SYS_SPD_BUS_NUM  0
 167 #define SPD_EEPROM_ADDRESS      0x52
 168 #define CONFIG_SYS_SDRAM_SIZE   4096    /* for fixed parameter use */
 169
 170 /*
 171  * Local Bus Definitions
 172  */
 173
 174 /* Set the local bus clock 1/8 of platform clock */
 175 #define CONFIG_SYS_LBC_LCRR             LCRR_CLKDIV_8
 176
 177 /*
 178  * This board doesn't have a promjet connector.
 179  * However, it uses commone corenet board LAW and TLB.
 180  * It is necessary to use the same start address with proper offset.
 181  */
 182 #define CONFIG_SYS_FLASH_BASE           0xe0000000
 183 #ifdef CONFIG_PHYS_64BIT
 184 #define CONFIG_SYS_FLASH_BASE_PHYS      0xfe0000000ull
 185 #else
 186 #define CONFIG_SYS_FLASH_BASE_PHYS      CONFIG_SYS_FLASH_BASE
 187 #endif
 188
 189 #define CONFIG_SYS_FLASH_BR_PRELIM \
 190                 (BR_PHYS_ADDR((CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000)) | \
 191                 BR_PS_16 | BR_V)
 192 #define CONFIG_SYS_FLASH_OR_PRELIM \
 193                 ((0xf8000ff7 & ~OR_GPCM_SCY & ~OR_GPCM_EHTR) \
 194                  | OR_GPCM_SCY_8 | OR_GPCM_EHTR_CLEAR)
 195
 196 #define CONFIG_FSL_CPLD
 197 #define CPLD_BASE               0xffdf0000      /* CPLD registers */
 198 #ifdef CONFIG_PHYS_64BIT
 199 #define CPLD_BASE_PHYS          0xfffdf0000ull
 200 #else
 201 #define CPLD_BASE_PHYS          CPLD_BASE
 202 #endif
 203
 204 #define CONFIG_SYS_BR3_PRELIM   (BR_PHYS_ADDR(CPLD_BASE_PHYS) | BR_PS_8 | BR_V)
 205 #define CONFIG_SYS_OR3_PRELIM   0xffffeff7      /* 32KB but only 4k mapped */
 206
 207 #define PIXIS_LBMAP_SWITCH      7
 208 #define PIXIS_LBMAP_MASK        0xf0
 209 #define PIXIS_LBMAP_SHIFT       4
 210 #define PIXIS_LBMAP_ALTBANK     0x40
 211
 212 #define CONFIG_SYS_FLASH_QUIET_TEST
 213 #define CONFIG_FLASH_SHOW_PROGRESS      45 /* count down from 45/5: 9..1 */
 214
 215 #define CONFIG_SYS_MAX_FLASH_BANKS      1               /* number of banks */
 216 #define CONFIG_SYS_MAX_FLASH_SECT       1024            /* sectors per device */
 217 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000           /* Erase Timeout (ms) */
 218 #define CONFIG_SYS_FLASH_WRITE_TOUT     500             /* Write Timeout (ms) */
 219
 220 #define CONFIG_SYS_MONITOR_BASE         CONFIG_SYS_TEXT_BASE
 221
 222 #if defined(CONFIG_RAMBOOT_PBL)
 223 #define CONFIG_SYS_RAMBOOT
 224 #endif
 225
 226 #define CONFIG_NAND_FSL_ELBC
 227 /* Nand Flash */
 228 #ifdef CONFIG_NAND_FSL_ELBC
 229 #define CONFIG_SYS_NAND_BASE            0xffa00000
 230 #ifdef CONFIG_PHYS_64BIT
 231 #define CONFIG_SYS_NAND_BASE_PHYS       0xfffa00000ull
 232 #else
 233 #define CONFIG_SYS_NAND_BASE_PHYS       CONFIG_SYS_NAND_BASE
 234 #endif
 235
 236 #define CONFIG_SYS_NAND_BASE_LIST     {CONFIG_SYS_NAND_BASE}
 237 #define CONFIG_SYS_MAX_NAND_DEVICE      1
 238 #define CONFIG_CMD_NAND
 239 #define CONFIG_SYS_NAND_BLOCK_SIZE    (128 * 1024)
 240
 241 /* NAND flash config */
 242 #define CONFIG_SYS_NAND_BR_PRELIM  (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
 243                                | (2<<BR_DECC_SHIFT)    /* Use HW ECC */ \
 244                                | BR_PS_8               /* Port Size = 8 bit */ \
 245                                | BR_MS_FCM             /* MSEL = FCM */ \
 246                                | BR_V)                 /* valid */
 247 #define CONFIG_SYS_NAND_OR_PRELIM  (0xFFFC0000        /* length 256K */ \
 248                                | OR_FCM_PGS            /* Large Page*/ \
 249                                | OR_FCM_CSCT \
 250                                | OR_FCM_CST \
 251                                | OR_FCM_CHT \
 252                                | OR_FCM_SCY_1 \
 253                                | OR_FCM_TRLX \
 254                                | OR_FCM_EHTR)
 255
 256 #ifdef CONFIG_NAND
 257 #define CONFIG_SYS_BR0_PRELIM  CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */
 258 #define CONFIG_SYS_OR0_PRELIM  CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
 259 #define CONFIG_SYS_BR1_PRELIM  CONFIG_SYS_FLASH_BR_PRELIM /* NOR Base Address */
 260 #define CONFIG_SYS_OR1_PRELIM  CONFIG_SYS_FLASH_OR_PRELIM /* NOR Options */
 261 #else
 262 #define CONFIG_SYS_BR0_PRELIM  CONFIG_SYS_FLASH_BR_PRELIM /* NOR Base Address */
 263 #define CONFIG_SYS_OR0_PRELIM  CONFIG_SYS_FLASH_OR_PRELIM /* NOR Options */
 264 #define CONFIG_SYS_BR1_PRELIM  CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */
 265 #define CONFIG_SYS_OR1_PRELIM  CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
 266 #endif
 267 #else
 268 #define CONFIG_SYS_BR0_PRELIM  CONFIG_SYS_FLASH_BR_PRELIM /* NOR Base Address */
 269 #define CONFIG_SYS_OR0_PRELIM  CONFIG_SYS_FLASH_OR_PRELIM /* NOR Options */
 270 #endif /* CONFIG_NAND_FSL_ELBC */
 271
 272 #define CONFIG_SYS_FLASH_EMPTY_INFO
 273 #define CONFIG_SYS_FLASH_AMD_CHECK_DQ7
 274 #define CONFIG_SYS_FLASH_BANKS_LIST     {CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000}
 275
 276 #define CONFIG_BOARD_EARLY_INIT_R       /* call board_early_init_r function */
 277 #define CONFIG_MISC_INIT_R
 278
 279 #define CONFIG_HWCONFIG
 280
 281 /* define to use L1 as initial stack */
 282 #define CONFIG_L1_INIT_RAM
 283 #define CONFIG_SYS_INIT_RAM_LOCK
 284 #define CONFIG_SYS_INIT_RAM_ADDR        0xffd00000      /* Initial L1 address */
 285 #ifdef CONFIG_PHYS_64BIT
 286 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
 287 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR
 288 /* The assembler doesn't like typecast */
 289 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
 290         ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
 291           CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
 292 #else
 293 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS   CONFIG_SYS_INIT_RAM_ADDR
 294 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0
 295 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS
 296 #endif
 297 #define CONFIG_SYS_INIT_RAM_SIZE        0x00004000
 298
 299 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - \
 300                                         GENERATED_GBL_DATA_SIZE)
 301 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 302
 303 #define CONFIG_SYS_MONITOR_LEN          (768 * 1024)
 304 #define CONFIG_SYS_MALLOC_LEN           (1024 * 1024)
 305
 306 /* Serial Port - controlled on board with jumper J8
 307  * open - index 2
 308  * shorted - index 1
 309  */
 310 #define CONFIG_CONS_INDEX       1
 311 #define CONFIG_SYS_NS16550_SERIAL
 312 #define CONFIG_SYS_NS16550_REG_SIZE     1
 313 #define CONFIG_SYS_NS16550_CLK          (get_bus_freq(0)/2)
 314
 315 #define CONFIG_SYS_BAUDRATE_TABLE       \
 316         {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
 317
 318 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
 319 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
 320 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
 321 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
 322
 323 /* I2C */
 324 #define CONFIG_SYS_I2C
 325 #define CONFIG_SYS_I2C_FSL
 326 #define CONFIG_SYS_FSL_I2C_SPEED        400000
 327 #define CONFIG_SYS_FSL_I2C_SLAVE        0x7F
 328 #define CONFIG_SYS_FSL_I2C_OFFSET       0x118000
 329 #define CONFIG_SYS_FSL_I2C2_SPEED       400000
 330 #define CONFIG_SYS_FSL_I2C2_SLAVE       0x7F
 331 #define CONFIG_SYS_FSL_I2C2_OFFSET      0x118100
 332
 333 /*
 334  * RapidIO
 335  */
 336 #define CONFIG_SYS_SRIO1_MEM_VIRT       0xa0000000
 337 #ifdef CONFIG_PHYS_64BIT
 338 #define CONFIG_SYS_SRIO1_MEM_PHYS       0xc20000000ull
 339 #else
 340 #define CONFIG_SYS_SRIO1_MEM_PHYS       0xa0000000
 341 #endif
 342 #define CONFIG_SYS_SRIO1_MEM_SIZE       0x10000000      /* 256M */
 343
 344 #define CONFIG_SYS_SRIO2_MEM_VIRT       0xb0000000
 345 #ifdef CONFIG_PHYS_64BIT
 346 #define CONFIG_SYS_SRIO2_MEM_PHYS       0xc30000000ull
 347 #else
 348 #define CONFIG_SYS_SRIO2_MEM_PHYS       0xb0000000
 349 #endif
 350 #define CONFIG_SYS_SRIO2_MEM_SIZE       0x10000000      /* 256M */
 351
 352 /*
 353  * for slave u-boot IMAGE instored in master memory space,
 354  * PHYS must be aligned based on the SIZE
 355  */
 356 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull
 357 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull
 358 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x100000       /* 1M */
 359 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull
 360 /*
 361  * for slave UCODE and ENV instored in master memory space,
 362  * PHYS must be aligned based on the SIZE
 363  */
 364 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull
 365 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull
 366 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000    /* 256K */
 367
 368 /* slave core release by master*/
 369 #define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4
 370 #define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */
 371
 372 /*
 373  * SRIO_PCIE_BOOT - SLAVE
 374  */
 375 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
 376 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000
 377 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \
 378                 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR)
 379 #endif
 380
 381 /*
 382  * eSPI - Enhanced SPI
 383  */
 384 #define CONFIG_SF_DEFAULT_SPEED         10000000
 385 #define CONFIG_SF_DEFAULT_MODE          0
 386
 387 /*
 388  * General PCI
 389  * Memory space is mapped 1-1, but I/O space must start from 0.
 390  */
 391
 392 /* controller 1, direct to uli, tgtid 3, Base address 20000 */
 393 #define CONFIG_SYS_PCIE1_MEM_VIRT       0x80000000
 394 #ifdef CONFIG_PHYS_64BIT
 395 #define CONFIG_SYS_PCIE1_MEM_BUS        0xe0000000
 396 #define CONFIG_SYS_PCIE1_MEM_PHYS       0xc00000000ull
 397 #else
 398 #define CONFIG_SYS_PCIE1_MEM_BUS        0x80000000
 399 #define CONFIG_SYS_PCIE1_MEM_PHYS       0x80000000
 400 #endif
 401 #define CONFIG_SYS_PCIE1_MEM_SIZE       0x20000000      /* 512M */
 402 #define CONFIG_SYS_PCIE1_IO_VIRT        0xf8000000
 403 #define CONFIG_SYS_PCIE1_IO_BUS         0x00000000
 404 #ifdef CONFIG_PHYS_64BIT
 405 #define CONFIG_SYS_PCIE1_IO_PHYS        0xff8000000ull
 406 #else
 407 #define CONFIG_SYS_PCIE1_IO_PHYS        0xf8000000
 408 #endif
 409 #define CONFIG_SYS_PCIE1_IO_SIZE        0x00010000      /* 64k */
 410
 411 /* controller 2, Slot 2, tgtid 2, Base address 201000 */
 412 #define CONFIG_SYS_PCIE2_MEM_VIRT       0xa0000000
 413 #ifdef CONFIG_PHYS_64BIT
 414 #define CONFIG_SYS_PCIE2_MEM_BUS        0xe0000000
 415 #define CONFIG_SYS_PCIE2_MEM_PHYS       0xc20000000ull
 416 #else
 417 #define CONFIG_SYS_PCIE2_MEM_BUS        0xa0000000
 418 #define CONFIG_SYS_PCIE2_MEM_PHYS       0xa0000000
 419 #endif
 420 #define CONFIG_SYS_PCIE2_MEM_SIZE       0x20000000      /* 512M */
 421 #define CONFIG_SYS_PCIE2_IO_VIRT        0xf8010000
 422 #define CONFIG_SYS_PCIE2_IO_BUS         0x00000000
 423 #ifdef CONFIG_PHYS_64BIT
 424 #define CONFIG_SYS_PCIE2_IO_PHYS        0xff8010000ull
 425 #else
 426 #define CONFIG_SYS_PCIE2_IO_PHYS        0xf8010000
 427 #endif
 428 #define CONFIG_SYS_PCIE2_IO_SIZE        0x00010000      /* 64k */
 429
 430 /* controller 3, Slot 1, tgtid 1, Base address 202000 */
 431 #define CONFIG_SYS_PCIE3_MEM_VIRT       0xc0000000
 432 #ifdef CONFIG_PHYS_64BIT
 433 #define CONFIG_SYS_PCIE3_MEM_BUS        0xe0000000
 434 #define CONFIG_SYS_PCIE3_MEM_PHYS       0xc40000000ull
 435 #else
 436 #define CONFIG_SYS_PCIE3_MEM_BUS        0xc0000000
 437 #define CONFIG_SYS_PCIE3_MEM_PHYS       0xc0000000
 438 #endif
 439 #define CONFIG_SYS_PCIE3_MEM_SIZE       0x20000000      /* 512M */
 440 #define CONFIG_SYS_PCIE3_IO_VIRT        0xf8020000
 441 #define CONFIG_SYS_PCIE3_IO_BUS         0x00000000
 442 #ifdef CONFIG_PHYS_64BIT
 443 #define CONFIG_SYS_PCIE3_IO_PHYS        0xff8020000ull
 444 #else
 445 #define CONFIG_SYS_PCIE3_IO_PHYS        0xf8020000
 446 #endif
 447 #define CONFIG_SYS_PCIE3_IO_SIZE        0x00010000      /* 64k */
 448
 449 /* Qman/Bman */
 450 #define CONFIG_SYS_DPAA_QBMAN           /* Support Q/Bman */
 451 #define CONFIG_SYS_BMAN_NUM_PORTALS     10
 452 #define CONFIG_SYS_BMAN_MEM_BASE        0xf4000000
 453 #ifdef CONFIG_PHYS_64BIT
 454 #define CONFIG_SYS_BMAN_MEM_PHYS        0xff4000000ull
 455 #else
 456 #define CONFIG_SYS_BMAN_MEM_PHYS        CONFIG_SYS_BMAN_MEM_BASE
 457 #endif
 458 #define CONFIG_SYS_BMAN_MEM_SIZE        0x00200000
 459 #define CONFIG_SYS_BMAN_SP_CENA_SIZE    0x4000
 460 #define CONFIG_SYS_BMAN_SP_CINH_SIZE    0x1000
 461 #define CONFIG_SYS_BMAN_CENA_BASE       CONFIG_SYS_BMAN_MEM_BASE
 462 #define CONFIG_SYS_BMAN_CENA_SIZE       (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
 463 #define CONFIG_SYS_BMAN_CINH_BASE       (CONFIG_SYS_BMAN_MEM_BASE + \
 464                                         CONFIG_SYS_BMAN_CENA_SIZE)
 465 #define CONFIG_SYS_BMAN_CINH_SIZE       (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
 466 #define CONFIG_SYS_BMAN_SWP_ISDR_REG    0xE08
 467 #define CONFIG_SYS_QMAN_NUM_PORTALS     10
 468 #define CONFIG_SYS_QMAN_MEM_BASE        0xf4200000
 469 #ifdef CONFIG_PHYS_64BIT
 470 #define CONFIG_SYS_QMAN_MEM_PHYS        0xff4200000ull
 471 #else
 472 #define CONFIG_SYS_QMAN_MEM_PHYS        CONFIG_SYS_QMAN_MEM_BASE
 473 #endif
 474 #define CONFIG_SYS_QMAN_MEM_SIZE        0x00200000
 475 #define CONFIG_SYS_QMAN_SP_CENA_SIZE    0x4000
 476 #define CONFIG_SYS_QMAN_SP_CINH_SIZE    0x1000
 477 #define CONFIG_SYS_QMAN_CENA_BASE       CONFIG_SYS_QMAN_MEM_BASE
 478 #define CONFIG_SYS_QMAN_CENA_SIZE       (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
 479 #define CONFIG_SYS_QMAN_CINH_BASE       (CONFIG_SYS_QMAN_MEM_BASE + \
 480                                         CONFIG_SYS_QMAN_CENA_SIZE)
 481 #define CONFIG_SYS_QMAN_CINH_SIZE       (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
 482 #define CONFIG_SYS_QMAN_SWP_ISDR_REG    0xE08
 483
 484 #define CONFIG_SYS_DPAA_FMAN
 485 #define CONFIG_SYS_DPAA_PME
 486 /* Default address of microcode for the Linux Fman driver */
 487 #if defined(CONFIG_SPIFLASH)
 488 /*
 489  * env is stored at 0x100000, sector size is 0x10000, ucode is stored after
 490  * env, so we got 0x110000.
 491  */
 492 #define CONFIG_SYS_QE_FW_IN_SPIFLASH
 493 #define CONFIG_SYS_FMAN_FW_ADDR 0x110000
 494 #elif defined(CONFIG_SDCARD)
 495 /*
 496  * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
 497  * about 825KB (1650 blocks), Env is stored after the image, and the env size is
 498  * 0x2000 (16 blocks), 8 + 1650 + 16 = 1674, enlarge it to 1680.
 499  */
 500 #define CONFIG_SYS_QE_FMAN_FW_IN_MMC
 501 #define CONFIG_SYS_FMAN_FW_ADDR (512 * 1680)
 502 #elif defined(CONFIG_NAND)
 503 #define CONFIG_SYS_QE_FMAN_FW_IN_NAND
 504 #define CONFIG_SYS_FMAN_FW_ADDR (8 * CONFIG_SYS_NAND_BLOCK_SIZE)
 505 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
 506 /*
 507  * Slave has no ucode locally, it can fetch this from remote. When implementing
 508  * in two corenet boards, slave's ucode could be stored in master's memory
 509  * space, the address can be mapped from slave TLB->slave LAW->
 510  * slave SRIO or PCIE outbound window->master inbound window->
 511  * master LAW->the ucode address in master's memory space.
 512  */
 513 #define CONFIG_SYS_QE_FMAN_FW_IN_REMOTE
 514 #define CONFIG_SYS_FMAN_FW_ADDR 0xFFE00000
 515 #else
 516 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR
 517 #define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000
 518 #endif
 519 #define CONFIG_SYS_QE_FMAN_FW_LENGTH    0x10000
 520 #define CONFIG_SYS_FDT_PAD              (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
 521
 522 #ifdef CONFIG_SYS_DPAA_FMAN
 523 #define CONFIG_FMAN_ENET
 524 #define CONFIG_PHYLIB_10G
 525 #define CONFIG_PHY_VITESSE
 526 #define CONFIG_PHY_TERANETICS
 527 #endif
 528
 529 #ifdef CONFIG_PCI
 530 #define CONFIG_PCI_INDIRECT_BRIDGE
 531
 532 #define CONFIG_PCI_SCAN_SHOW            /* show pci devices on startup */
 533 #endif  /* CONFIG_PCI */
 534
 535 /* SATA */
 536 #define CONFIG_FSL_SATA_V2
 537
 538 #ifdef CONFIG_FSL_SATA_V2
 539 #define CONFIG_FSL_SATA
 540 #define CONFIG_LIBATA
 541
 542 #define CONFIG_SYS_SATA_MAX_DEVICE      2
 543 #define CONFIG_SATA1
 544 #define CONFIG_SYS_SATA1                CONFIG_SYS_MPC85xx_SATA1_ADDR
 545 #define CONFIG_SYS_SATA1_FLAGS          FLAGS_DMA
 546 #define CONFIG_SATA2
 547 #define CONFIG_SYS_SATA2                CONFIG_SYS_MPC85xx_SATA2_ADDR
 548 #define CONFIG_SYS_SATA2_FLAGS          FLAGS_DMA
 549
 550 #define CONFIG_LBA48
 551 #define CONFIG_CMD_SATA
 552 #endif
 553
 554 #ifdef CONFIG_FMAN_ENET
 555 #define CONFIG_SYS_FM1_DTSEC1_PHY_ADDR  0x2
 556 #define CONFIG_SYS_FM1_DTSEC2_PHY_ADDR  0x3
 557 #define CONFIG_SYS_FM1_DTSEC3_PHY_ADDR  0x4
 558 #define CONFIG_SYS_FM1_DTSEC4_PHY_ADDR  0x1
 559 #define CONFIG_SYS_FM1_DTSEC5_PHY_ADDR  0x0
 560
 561 #define CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR    0x1c
 562 #define CONFIG_SYS_FM1_DTSEC2_RISER_PHY_ADDR    0x1d
 563 #define CONFIG_SYS_FM1_DTSEC3_RISER_PHY_ADDR    0x1e
 564 #define CONFIG_SYS_FM1_DTSEC4_RISER_PHY_ADDR    0x1f
 565
 566 #define CONFIG_SYS_FM1_10GEC1_PHY_ADDR  0
 567
 568 #define CONFIG_SYS_TBIPA_VALUE  8
 569 #define CONFIG_MII              /* MII PHY management */
 570 #define CONFIG_ETHPRIME         "FM1@DTSEC1"
 571 #define CONFIG_PHY_GIGE         /* Include GbE speed/duplex detection */
 572 #endif
 573
 574 /*
 575  * Environment
 576  */
 577 #define CONFIG_LOADS_ECHO               /* echo on for serial download */
 578 #define CONFIG_SYS_LOADS_BAUD_CHANGE    /* allow baudrate change */
 579
 580 /*
 581  * Command line configuration.
 582  */
 583 #define CONFIG_CMD_ERRATA
 584 #define CONFIG_CMD_IRQ
 585
 586 #ifdef CONFIG_PCI
 587 #define CONFIG_CMD_PCI
 588 #endif
 589
 590 /*
 591 * USB
 592 */
 593 #define CONFIG_HAS_FSL_DR_USB
 594 #define CONFIG_HAS_FSL_MPH_USB
 595
 596 #if defined(CONFIG_HAS_FSL_DR_USB) || defined(CONFIG_HAS_FSL_MPH_USB)
 597 #define CONFIG_USB_EHCI_FSL
 598 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
 599 #endif
 600
 601 #ifdef CONFIG_MMC
 602 #define CONFIG_FSL_ESDHC
 603 #define CONFIG_SYS_FSL_ESDHC_ADDR       CONFIG_SYS_MPC85xx_ESDHC_ADDR
 604 #define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT
 605 #endif
 606
 607 /* Hash command with SHA acceleration supported in hardware */
 608 #ifdef CONFIG_FSL_CAAM
 609 #define CONFIG_CMD_HASH
 610 #define CONFIG_SHA_HW_ACCEL
 611 #endif
 612
 613 /*
 614  * Miscellaneous configurable options
 615  */
 616 #define CONFIG_SYS_LONGHELP                     /* undef to save memory */
 617 #define CONFIG_CMDLINE_EDITING                  /* Command-line editing */
 618 #define CONFIG_AUTO_COMPLETE                    /* add autocompletion support */
 619 #define CONFIG_SYS_LOAD_ADDR    0x2000000       /* default load address */
 620 #ifdef CONFIG_CMD_KGDB
 621 #define CONFIG_SYS_CBSIZE       1024            /* Console I/O Buffer Size */
 622 #else
 623 #define CONFIG_SYS_CBSIZE       256             /* Console I/O Buffer Size */
 624 #endif
 625 /* Print Buffer Size */
 626 #define CONFIG_SYS_PBSIZE       (CONFIG_SYS_CBSIZE + \
 627                                 sizeof(CONFIG_SYS_PROMPT)+16)
 628 #define CONFIG_SYS_MAXARGS      16              /* max number of command args */
 629 /* Boot Argument Buffer Size */
 630 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE
 631
 632 /*
 633  * For booting Linux, the board info and command line data
 634  * have to be in the first 64 MB of memory, since this is
 635  * the maximum mapped by the Linux kernel during initialization.
 636  */
 637 #define CONFIG_SYS_BOOTMAPSZ    (64 << 20)      /* Initial Memory for Linux */
 638 #define CONFIG_SYS_BOOTM_LEN    (64 << 20)      /* Increase max gunzip size */
 639
 640 #ifdef CONFIG_CMD_KGDB
 641 #define CONFIG_KGDB_BAUDRATE    230400  /* speed to run kgdb serial port */
 642 #endif
 643
 644 /*
 645  * Environment Configuration
 646  */
 647 #define CONFIG_ROOTPATH         "/opt/nfsroot"
 648 #define CONFIG_BOOTFILE         "uImage"
 649 #define CONFIG_UBOOTPATH        u-boot.bin
 650
 651 /* default location for tftp and bootm */
 652 #define CONFIG_LOADADDR         1000000
 653
 654 #define __USB_PHY_TYPE  utmi
 655
 656 #define CONFIG_EXTRA_ENV_SETTINGS                               \
 657         "hwconfig=fsl_ddr:ctlr_intlv=cacheline,"                \
 658         "bank_intlv=cs0_cs1\0"                                  \
 659         "netdev=eth0\0"                                         \
 660         "uboot=" __stringify(CONFIG_UBOOTPATH) "\0"                     \
 661         "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0"             \
 662         "tftpflash=tftpboot $loadaddr $uboot && "               \
 663         "protect off $ubootaddr +$filesize && "                 \
 664         "erase $ubootaddr +$filesize && "                       \
 665         "cp.b $loadaddr $ubootaddr $filesize && "               \
 666         "protect on $ubootaddr +$filesize && "                  \
 667         "cmp.b $loadaddr $ubootaddr $filesize\0"                \
 668         "consoledev=ttyS0\0"                                    \
 669         "usb_phy_type=" __stringify(__USB_PHY_TYPE) "\0"                \
 670         "usb_dr_mode=host\0"                                    \
 671         "ramdiskaddr=2000000\0"                                 \
 672         "ramdiskfile=p2041rdb/ramdisk.uboot\0"                  \
 673         "fdtaddr=1e00000\0"                                     \
 674         "fdtfile=p2041rdb/p2041rdb.dtb\0"                       \
 675         "bdev=sda3\0"
 676
 677 #define CONFIG_HDBOOT                                   \
 678         "setenv bootargs root=/dev/$bdev rw "           \
 679         "console=$consoledev,$baudrate $othbootargs;"   \
 680         "tftp $loadaddr $bootfile;"                     \
 681         "tftp $fdtaddr $fdtfile;"                       \
 682         "bootm $loadaddr - $fdtaddr"
 683
 684 #define CONFIG_NFSBOOTCOMMAND                   \
 685         "setenv bootargs root=/dev/nfs rw "     \
 686         "nfsroot=$serverip:$rootpath "          \
 687         "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
 688         "console=$consoledev,$baudrate $othbootargs;"   \
 689         "tftp $loadaddr $bootfile;"             \
 690         "tftp $fdtaddr $fdtfile;"               \
 691         "bootm $loadaddr - $fdtaddr"
 692
 693 #define CONFIG_RAMBOOTCOMMAND                           \
 694         "setenv bootargs root=/dev/ram rw "             \
 695         "console=$consoledev,$baudrate $othbootargs;"   \
 696         "tftp $ramdiskaddr $ramdiskfile;"               \
 697         "tftp $loadaddr $bootfile;"                     \
 698         "tftp $fdtaddr $fdtfile;"                       \
 699         "bootm $loadaddr $ramdiskaddr $fdtaddr"
 700
 701 #define CONFIG_BOOTCOMMAND              CONFIG_HDBOOT
 702
 703 #include <asm/fsl_secure_boot.h>
 704
 705 #endif  /* __CONFIG_H */