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[u-boot] / include / configs / P2041RDB.h
1 /*
2  * Copyright 2011-2012 Freescale Semiconductor, Inc.
3  *
4  * SPDX-License-Identifier:     GPL-2.0+
5  */
6
7 /*
8  * P2041 RDB board configuration file
9  * Also supports P2040 RDB
10  */
11 #ifndef __CONFIG_H
12 #define __CONFIG_H
13
14 #ifdef CONFIG_RAMBOOT_PBL
15 #define CONFIG_RAMBOOT_TEXT_BASE        CONFIG_SYS_TEXT_BASE
16 #define CONFIG_RESET_VECTOR_ADDRESS     0xfffffffc
17 #define CONFIG_SYS_FSL_PBL_PBI board/freescale/corenet_ds/pbi.cfg
18 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/corenet_ds/rcw_p2041rdb.cfg
19 #endif
20
21 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
22 /* Set 1M boot space */
23 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000)
24 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \
25                 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR)
26 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
27 #endif
28
29 /* High Level Configuration Options */
30 #define CONFIG_SYS_BOOK3E_HV            /* Category E.HV supported */
31 #define CONFIG_MP                       /* support multiple processors */
32
33 #ifndef CONFIG_SYS_TEXT_BASE
34 #define CONFIG_SYS_TEXT_BASE    0xeff40000
35 #endif
36
37 #ifndef CONFIG_RESET_VECTOR_ADDRESS
38 #define CONFIG_RESET_VECTOR_ADDRESS     0xeffffffc
39 #endif
40
41 #define CONFIG_SYS_FSL_CPC              /* Corenet Platform Cache */
42 #define CONFIG_SYS_NUM_CPC              CONFIG_SYS_NUM_DDR_CTLRS
43 #define CONFIG_PCIE1                    /* PCIE controller 1 */
44 #define CONFIG_PCIE2                    /* PCIE controller 2 */
45 #define CONFIG_PCIE3                    /* PCIE controller 3 */
46 #define CONFIG_FSL_PCI_INIT             /* Use common FSL init code */
47 #define CONFIG_SYS_PCI_64BIT            /* enable 64-bit PCI resources */
48
49 #define CONFIG_SYS_SRIO
50 #define CONFIG_SRIO1                    /* SRIO port 1 */
51 #define CONFIG_SRIO2                    /* SRIO port 2 */
52 #define CONFIG_SRIO_PCIE_BOOT_MASTER
53 #define CONFIG_SYS_DPAA_RMAN            /* RMan */
54
55 #define CONFIG_ENV_OVERWRITE
56
57 #ifndef CONFIG_MTD_NOR_FLASH
58 #else
59 #define CONFIG_FLASH_CFI_DRIVER
60 #define CONFIG_SYS_FLASH_CFI
61 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
62 #endif
63
64 #if defined(CONFIG_SPIFLASH)
65         #define CONFIG_SYS_EXTRA_ENV_RELOC
66         #define CONFIG_ENV_IS_IN_SPI_FLASH
67         #define CONFIG_ENV_SPI_BUS              0
68         #define CONFIG_ENV_SPI_CS               0
69         #define CONFIG_ENV_SPI_MAX_HZ           10000000
70         #define CONFIG_ENV_SPI_MODE             0
71         #define CONFIG_ENV_SIZE                 0x2000          /* 8KB */
72         #define CONFIG_ENV_OFFSET               0x100000        /* 1MB */
73         #define CONFIG_ENV_SECT_SIZE            0x10000
74 #elif defined(CONFIG_SDCARD)
75         #define CONFIG_SYS_EXTRA_ENV_RELOC
76         #define CONFIG_FSL_FIXED_MMC_LOCATION
77         #define CONFIG_SYS_MMC_ENV_DEV          0
78         #define CONFIG_ENV_SIZE                 0x2000
79         #define CONFIG_ENV_OFFSET               (512 * 1658)
80 #elif defined(CONFIG_NAND)
81 #define CONFIG_SYS_EXTRA_ENV_RELOC
82 #define CONFIG_ENV_SIZE                 CONFIG_SYS_NAND_BLOCK_SIZE
83 #define CONFIG_ENV_OFFSET               (7 * CONFIG_SYS_NAND_BLOCK_SIZE)
84 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
85 #define CONFIG_ENV_IS_IN_REMOTE
86 #define CONFIG_ENV_ADDR         0xffe20000
87 #define CONFIG_ENV_SIZE         0x2000
88 #elif defined(CONFIG_ENV_IS_NOWHERE)
89 #define CONFIG_ENV_SIZE         0x2000
90 #else
91         #define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE \
92                         - CONFIG_ENV_SECT_SIZE)
93         #define CONFIG_ENV_SIZE         0x2000
94         #define CONFIG_ENV_SECT_SIZE    0x20000 /* 128K (one sector) */
95 #endif
96
97 #ifndef __ASSEMBLY__
98 unsigned long get_board_sys_clk(unsigned long dummy);
99 #endif
100 #define CONFIG_SYS_CLK_FREQ     get_board_sys_clk(0)
101
102 /*
103  * These can be toggled for performance analysis, otherwise use default.
104  */
105 #define CONFIG_SYS_CACHE_STASHING
106 #define CONFIG_BACKSIDE_L2_CACHE
107 #define CONFIG_SYS_INIT_L2CSR0          L2CSR0_L2E
108 #define CONFIG_BTB                      /* toggle branch predition */
109
110 #define CONFIG_ENABLE_36BIT_PHYS
111
112 #ifdef CONFIG_PHYS_64BIT
113 #define CONFIG_ADDR_MAP
114 #define CONFIG_SYS_NUM_ADDR_MAP         64      /* number of TLB1 entries */
115 #endif
116
117 #define CONFIG_POST CONFIG_SYS_POST_MEMORY      /* test POST memory test */
118 #define CONFIG_SYS_MEMTEST_START        0x00200000      /* memtest works on */
119 #define CONFIG_SYS_MEMTEST_END          0x00400000
120 #define CONFIG_SYS_ALT_MEMTEST
121 #define CONFIG_PANIC_HANG       /* do not reset board on panic */
122
123 /*
124  *  Config the L3 Cache as L3 SRAM
125  */
126 #define CONFIG_SYS_INIT_L3_ADDR         CONFIG_RAMBOOT_TEXT_BASE
127 #ifdef CONFIG_PHYS_64BIT
128 #define CONFIG_SYS_INIT_L3_ADDR_PHYS    (0xf00000000ull | \
129                 CONFIG_RAMBOOT_TEXT_BASE)
130 #else
131 #define CONFIG_SYS_INIT_L3_ADDR_PHYS    CONFIG_SYS_INIT_L3_ADDR
132 #endif
133 #define CONFIG_SYS_L3_SIZE              (1024 << 10)
134 #define CONFIG_SYS_INIT_L3_END (CONFIG_SYS_INIT_L3_ADDR + CONFIG_SYS_L3_SIZE)
135
136 #ifdef CONFIG_PHYS_64BIT
137 #define CONFIG_SYS_DCSRBAR              0xf0000000
138 #define CONFIG_SYS_DCSRBAR_PHYS         0xf00000000ull
139 #endif
140
141 /* EEPROM */
142 #define CONFIG_ID_EEPROM
143 #define CONFIG_SYS_I2C_EEPROM_NXID
144 #define CONFIG_SYS_EEPROM_BUS_NUM       0
145 #define CONFIG_SYS_I2C_EEPROM_ADDR      0x50
146 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN  1
147
148 /*
149  * DDR Setup
150  */
151 #define CONFIG_VERY_BIG_RAM
152 #define CONFIG_SYS_DDR_SDRAM_BASE       0x00000000
153 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_SDRAM_BASE
154
155 #define CONFIG_DIMM_SLOTS_PER_CTLR      1
156 #define CONFIG_CHIP_SELECTS_PER_CTRL    (4 * CONFIG_DIMM_SLOTS_PER_CTLR)
157
158 #define CONFIG_DDR_SPD
159
160 #define CONFIG_SYS_SPD_BUS_NUM  0
161 #define SPD_EEPROM_ADDRESS      0x52
162 #define CONFIG_SYS_SDRAM_SIZE   4096    /* for fixed parameter use */
163
164 /*
165  * Local Bus Definitions
166  */
167
168 /* Set the local bus clock 1/8 of platform clock */
169 #define CONFIG_SYS_LBC_LCRR             LCRR_CLKDIV_8
170
171 /*
172  * This board doesn't have a promjet connector.
173  * However, it uses commone corenet board LAW and TLB.
174  * It is necessary to use the same start address with proper offset.
175  */
176 #define CONFIG_SYS_FLASH_BASE           0xe0000000
177 #ifdef CONFIG_PHYS_64BIT
178 #define CONFIG_SYS_FLASH_BASE_PHYS      0xfe0000000ull
179 #else
180 #define CONFIG_SYS_FLASH_BASE_PHYS      CONFIG_SYS_FLASH_BASE
181 #endif
182
183 #define CONFIG_SYS_FLASH_BR_PRELIM \
184                 (BR_PHYS_ADDR((CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000)) | \
185                 BR_PS_16 | BR_V)
186 #define CONFIG_SYS_FLASH_OR_PRELIM \
187                 ((0xf8000ff7 & ~OR_GPCM_SCY & ~OR_GPCM_EHTR) \
188                  | OR_GPCM_SCY_8 | OR_GPCM_EHTR_CLEAR)
189
190 #define CONFIG_FSL_CPLD
191 #define CPLD_BASE               0xffdf0000      /* CPLD registers */
192 #ifdef CONFIG_PHYS_64BIT
193 #define CPLD_BASE_PHYS          0xfffdf0000ull
194 #else
195 #define CPLD_BASE_PHYS          CPLD_BASE
196 #endif
197
198 #define CONFIG_SYS_BR3_PRELIM   (BR_PHYS_ADDR(CPLD_BASE_PHYS) | BR_PS_8 | BR_V)
199 #define CONFIG_SYS_OR3_PRELIM   0xffffeff7      /* 32KB but only 4k mapped */
200
201 #define PIXIS_LBMAP_SWITCH      7
202 #define PIXIS_LBMAP_MASK        0xf0
203 #define PIXIS_LBMAP_SHIFT       4
204 #define PIXIS_LBMAP_ALTBANK     0x40
205
206 #define CONFIG_SYS_FLASH_QUIET_TEST
207 #define CONFIG_FLASH_SHOW_PROGRESS      45 /* count down from 45/5: 9..1 */
208
209 #define CONFIG_SYS_MAX_FLASH_BANKS      1               /* number of banks */
210 #define CONFIG_SYS_MAX_FLASH_SECT       1024            /* sectors per device */
211 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000           /* Erase Timeout (ms) */
212 #define CONFIG_SYS_FLASH_WRITE_TOUT     500             /* Write Timeout (ms) */
213
214 #define CONFIG_SYS_MONITOR_BASE         CONFIG_SYS_TEXT_BASE
215
216 #if defined(CONFIG_RAMBOOT_PBL)
217 #define CONFIG_SYS_RAMBOOT
218 #endif
219
220 #define CONFIG_NAND_FSL_ELBC
221 /* Nand Flash */
222 #ifdef CONFIG_NAND_FSL_ELBC
223 #define CONFIG_SYS_NAND_BASE            0xffa00000
224 #ifdef CONFIG_PHYS_64BIT
225 #define CONFIG_SYS_NAND_BASE_PHYS       0xfffa00000ull
226 #else
227 #define CONFIG_SYS_NAND_BASE_PHYS       CONFIG_SYS_NAND_BASE
228 #endif
229
230 #define CONFIG_SYS_NAND_BASE_LIST     {CONFIG_SYS_NAND_BASE}
231 #define CONFIG_SYS_MAX_NAND_DEVICE      1
232 #define CONFIG_CMD_NAND
233 #define CONFIG_SYS_NAND_BLOCK_SIZE    (128 * 1024)
234
235 /* NAND flash config */
236 #define CONFIG_SYS_NAND_BR_PRELIM  (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
237                                | (2<<BR_DECC_SHIFT)    /* Use HW ECC */ \
238                                | BR_PS_8               /* Port Size = 8 bit */ \
239                                | BR_MS_FCM             /* MSEL = FCM */ \
240                                | BR_V)                 /* valid */
241 #define CONFIG_SYS_NAND_OR_PRELIM  (0xFFFC0000        /* length 256K */ \
242                                | OR_FCM_PGS            /* Large Page*/ \
243                                | OR_FCM_CSCT \
244                                | OR_FCM_CST \
245                                | OR_FCM_CHT \
246                                | OR_FCM_SCY_1 \
247                                | OR_FCM_TRLX \
248                                | OR_FCM_EHTR)
249
250 #ifdef CONFIG_NAND
251 #define CONFIG_SYS_BR0_PRELIM  CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */
252 #define CONFIG_SYS_OR0_PRELIM  CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
253 #define CONFIG_SYS_BR1_PRELIM  CONFIG_SYS_FLASH_BR_PRELIM /* NOR Base Address */
254 #define CONFIG_SYS_OR1_PRELIM  CONFIG_SYS_FLASH_OR_PRELIM /* NOR Options */
255 #else
256 #define CONFIG_SYS_BR0_PRELIM  CONFIG_SYS_FLASH_BR_PRELIM /* NOR Base Address */
257 #define CONFIG_SYS_OR0_PRELIM  CONFIG_SYS_FLASH_OR_PRELIM /* NOR Options */
258 #define CONFIG_SYS_BR1_PRELIM  CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */
259 #define CONFIG_SYS_OR1_PRELIM  CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
260 #endif
261 #else
262 #define CONFIG_SYS_BR0_PRELIM  CONFIG_SYS_FLASH_BR_PRELIM /* NOR Base Address */
263 #define CONFIG_SYS_OR0_PRELIM  CONFIG_SYS_FLASH_OR_PRELIM /* NOR Options */
264 #endif /* CONFIG_NAND_FSL_ELBC */
265
266 #define CONFIG_SYS_FLASH_EMPTY_INFO
267 #define CONFIG_SYS_FLASH_AMD_CHECK_DQ7
268 #define CONFIG_SYS_FLASH_BANKS_LIST     {CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000}
269
270 #define CONFIG_BOARD_EARLY_INIT_R       /* call board_early_init_r function */
271 #define CONFIG_MISC_INIT_R
272
273 #define CONFIG_HWCONFIG
274
275 /* define to use L1 as initial stack */
276 #define CONFIG_L1_INIT_RAM
277 #define CONFIG_SYS_INIT_RAM_LOCK
278 #define CONFIG_SYS_INIT_RAM_ADDR        0xffd00000      /* Initial L1 address */
279 #ifdef CONFIG_PHYS_64BIT
280 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
281 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR
282 /* The assembler doesn't like typecast */
283 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
284         ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
285           CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
286 #else
287 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS   CONFIG_SYS_INIT_RAM_ADDR
288 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0
289 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS
290 #endif
291 #define CONFIG_SYS_INIT_RAM_SIZE        0x00004000
292
293 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - \
294                                         GENERATED_GBL_DATA_SIZE)
295 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
296
297 #define CONFIG_SYS_MONITOR_LEN          (768 * 1024)
298 #define CONFIG_SYS_MALLOC_LEN           (1024 * 1024)
299
300 /* Serial Port - controlled on board with jumper J8
301  * open - index 2
302  * shorted - index 1
303  */
304 #define CONFIG_CONS_INDEX       1
305 #define CONFIG_SYS_NS16550_SERIAL
306 #define CONFIG_SYS_NS16550_REG_SIZE     1
307 #define CONFIG_SYS_NS16550_CLK          (get_bus_freq(0)/2)
308
309 #define CONFIG_SYS_BAUDRATE_TABLE       \
310         {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
311
312 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
313 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
314 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
315 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
316
317 /* I2C */
318 #define CONFIG_SYS_I2C
319 #define CONFIG_SYS_I2C_FSL
320 #define CONFIG_SYS_FSL_I2C_SPEED        400000
321 #define CONFIG_SYS_FSL_I2C_SLAVE        0x7F
322 #define CONFIG_SYS_FSL_I2C_OFFSET       0x118000
323 #define CONFIG_SYS_FSL_I2C2_SPEED       400000
324 #define CONFIG_SYS_FSL_I2C2_SLAVE       0x7F
325 #define CONFIG_SYS_FSL_I2C2_OFFSET      0x118100
326
327 /*
328  * RapidIO
329  */
330 #define CONFIG_SYS_SRIO1_MEM_VIRT       0xa0000000
331 #ifdef CONFIG_PHYS_64BIT
332 #define CONFIG_SYS_SRIO1_MEM_PHYS       0xc20000000ull
333 #else
334 #define CONFIG_SYS_SRIO1_MEM_PHYS       0xa0000000
335 #endif
336 #define CONFIG_SYS_SRIO1_MEM_SIZE       0x10000000      /* 256M */
337
338 #define CONFIG_SYS_SRIO2_MEM_VIRT       0xb0000000
339 #ifdef CONFIG_PHYS_64BIT
340 #define CONFIG_SYS_SRIO2_MEM_PHYS       0xc30000000ull
341 #else
342 #define CONFIG_SYS_SRIO2_MEM_PHYS       0xb0000000
343 #endif
344 #define CONFIG_SYS_SRIO2_MEM_SIZE       0x10000000      /* 256M */
345
346 /*
347  * for slave u-boot IMAGE instored in master memory space,
348  * PHYS must be aligned based on the SIZE
349  */
350 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull
351 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull
352 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x100000       /* 1M */
353 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull
354 /*
355  * for slave UCODE and ENV instored in master memory space,
356  * PHYS must be aligned based on the SIZE
357  */
358 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull
359 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull
360 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000    /* 256K */
361
362 /* slave core release by master*/
363 #define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4
364 #define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */
365
366 /*
367  * SRIO_PCIE_BOOT - SLAVE
368  */
369 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
370 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000
371 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \
372                 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR)
373 #endif
374
375 /*
376  * eSPI - Enhanced SPI
377  */
378 #define CONFIG_SF_DEFAULT_SPEED         10000000
379 #define CONFIG_SF_DEFAULT_MODE          0
380
381 /*
382  * General PCI
383  * Memory space is mapped 1-1, but I/O space must start from 0.
384  */
385
386 /* controller 1, direct to uli, tgtid 3, Base address 20000 */
387 #define CONFIG_SYS_PCIE1_MEM_VIRT       0x80000000
388 #ifdef CONFIG_PHYS_64BIT
389 #define CONFIG_SYS_PCIE1_MEM_BUS        0xe0000000
390 #define CONFIG_SYS_PCIE1_MEM_PHYS       0xc00000000ull
391 #else
392 #define CONFIG_SYS_PCIE1_MEM_BUS        0x80000000
393 #define CONFIG_SYS_PCIE1_MEM_PHYS       0x80000000
394 #endif
395 #define CONFIG_SYS_PCIE1_MEM_SIZE       0x20000000      /* 512M */
396 #define CONFIG_SYS_PCIE1_IO_VIRT        0xf8000000
397 #define CONFIG_SYS_PCIE1_IO_BUS         0x00000000
398 #ifdef CONFIG_PHYS_64BIT
399 #define CONFIG_SYS_PCIE1_IO_PHYS        0xff8000000ull
400 #else
401 #define CONFIG_SYS_PCIE1_IO_PHYS        0xf8000000
402 #endif
403 #define CONFIG_SYS_PCIE1_IO_SIZE        0x00010000      /* 64k */
404
405 /* controller 2, Slot 2, tgtid 2, Base address 201000 */
406 #define CONFIG_SYS_PCIE2_MEM_VIRT       0xa0000000
407 #ifdef CONFIG_PHYS_64BIT
408 #define CONFIG_SYS_PCIE2_MEM_BUS        0xe0000000
409 #define CONFIG_SYS_PCIE2_MEM_PHYS       0xc20000000ull
410 #else
411 #define CONFIG_SYS_PCIE2_MEM_BUS        0xa0000000
412 #define CONFIG_SYS_PCIE2_MEM_PHYS       0xa0000000
413 #endif
414 #define CONFIG_SYS_PCIE2_MEM_SIZE       0x20000000      /* 512M */
415 #define CONFIG_SYS_PCIE2_IO_VIRT        0xf8010000
416 #define CONFIG_SYS_PCIE2_IO_BUS         0x00000000
417 #ifdef CONFIG_PHYS_64BIT
418 #define CONFIG_SYS_PCIE2_IO_PHYS        0xff8010000ull
419 #else
420 #define CONFIG_SYS_PCIE2_IO_PHYS        0xf8010000
421 #endif
422 #define CONFIG_SYS_PCIE2_IO_SIZE        0x00010000      /* 64k */
423
424 /* controller 3, Slot 1, tgtid 1, Base address 202000 */
425 #define CONFIG_SYS_PCIE3_MEM_VIRT       0xc0000000
426 #ifdef CONFIG_PHYS_64BIT
427 #define CONFIG_SYS_PCIE3_MEM_BUS        0xe0000000
428 #define CONFIG_SYS_PCIE3_MEM_PHYS       0xc40000000ull
429 #else
430 #define CONFIG_SYS_PCIE3_MEM_BUS        0xc0000000
431 #define CONFIG_SYS_PCIE3_MEM_PHYS       0xc0000000
432 #endif
433 #define CONFIG_SYS_PCIE3_MEM_SIZE       0x20000000      /* 512M */
434 #define CONFIG_SYS_PCIE3_IO_VIRT        0xf8020000
435 #define CONFIG_SYS_PCIE3_IO_BUS         0x00000000
436 #ifdef CONFIG_PHYS_64BIT
437 #define CONFIG_SYS_PCIE3_IO_PHYS        0xff8020000ull
438 #else
439 #define CONFIG_SYS_PCIE3_IO_PHYS        0xf8020000
440 #endif
441 #define CONFIG_SYS_PCIE3_IO_SIZE        0x00010000      /* 64k */
442
443 /* Qman/Bman */
444 #define CONFIG_SYS_DPAA_QBMAN           /* Support Q/Bman */
445 #define CONFIG_SYS_BMAN_NUM_PORTALS     10
446 #define CONFIG_SYS_BMAN_MEM_BASE        0xf4000000
447 #ifdef CONFIG_PHYS_64BIT
448 #define CONFIG_SYS_BMAN_MEM_PHYS        0xff4000000ull
449 #else
450 #define CONFIG_SYS_BMAN_MEM_PHYS        CONFIG_SYS_BMAN_MEM_BASE
451 #endif
452 #define CONFIG_SYS_BMAN_MEM_SIZE        0x00200000
453 #define CONFIG_SYS_BMAN_SP_CENA_SIZE    0x4000
454 #define CONFIG_SYS_BMAN_SP_CINH_SIZE    0x1000
455 #define CONFIG_SYS_BMAN_CENA_BASE       CONFIG_SYS_BMAN_MEM_BASE
456 #define CONFIG_SYS_BMAN_CENA_SIZE       (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
457 #define CONFIG_SYS_BMAN_CINH_BASE       (CONFIG_SYS_BMAN_MEM_BASE + \
458                                         CONFIG_SYS_BMAN_CENA_SIZE)
459 #define CONFIG_SYS_BMAN_CINH_SIZE       (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
460 #define CONFIG_SYS_BMAN_SWP_ISDR_REG    0xE08
461 #define CONFIG_SYS_QMAN_NUM_PORTALS     10
462 #define CONFIG_SYS_QMAN_MEM_BASE        0xf4200000
463 #ifdef CONFIG_PHYS_64BIT
464 #define CONFIG_SYS_QMAN_MEM_PHYS        0xff4200000ull
465 #else
466 #define CONFIG_SYS_QMAN_MEM_PHYS        CONFIG_SYS_QMAN_MEM_BASE
467 #endif
468 #define CONFIG_SYS_QMAN_MEM_SIZE        0x00200000
469 #define CONFIG_SYS_QMAN_SP_CENA_SIZE    0x4000
470 #define CONFIG_SYS_QMAN_SP_CINH_SIZE    0x1000
471 #define CONFIG_SYS_QMAN_CENA_BASE       CONFIG_SYS_QMAN_MEM_BASE
472 #define CONFIG_SYS_QMAN_CENA_SIZE       (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
473 #define CONFIG_SYS_QMAN_CINH_BASE       (CONFIG_SYS_QMAN_MEM_BASE + \
474                                         CONFIG_SYS_QMAN_CENA_SIZE)
475 #define CONFIG_SYS_QMAN_CINH_SIZE       (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
476 #define CONFIG_SYS_QMAN_SWP_ISDR_REG    0xE08
477
478 #define CONFIG_SYS_DPAA_FMAN
479 #define CONFIG_SYS_DPAA_PME
480 /* Default address of microcode for the Linux Fman driver */
481 #if defined(CONFIG_SPIFLASH)
482 /*
483  * env is stored at 0x100000, sector size is 0x10000, ucode is stored after
484  * env, so we got 0x110000.
485  */
486 #define CONFIG_SYS_QE_FW_IN_SPIFLASH
487 #define CONFIG_SYS_FMAN_FW_ADDR 0x110000
488 #elif defined(CONFIG_SDCARD)
489 /*
490  * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
491  * about 825KB (1650 blocks), Env is stored after the image, and the env size is
492  * 0x2000 (16 blocks), 8 + 1650 + 16 = 1674, enlarge it to 1680.
493  */
494 #define CONFIG_SYS_QE_FMAN_FW_IN_MMC
495 #define CONFIG_SYS_FMAN_FW_ADDR (512 * 1680)
496 #elif defined(CONFIG_NAND)
497 #define CONFIG_SYS_QE_FMAN_FW_IN_NAND
498 #define CONFIG_SYS_FMAN_FW_ADDR (8 * CONFIG_SYS_NAND_BLOCK_SIZE)
499 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
500 /*
501  * Slave has no ucode locally, it can fetch this from remote. When implementing
502  * in two corenet boards, slave's ucode could be stored in master's memory
503  * space, the address can be mapped from slave TLB->slave LAW->
504  * slave SRIO or PCIE outbound window->master inbound window->
505  * master LAW->the ucode address in master's memory space.
506  */
507 #define CONFIG_SYS_QE_FMAN_FW_IN_REMOTE
508 #define CONFIG_SYS_FMAN_FW_ADDR 0xFFE00000
509 #else
510 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR
511 #define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000
512 #endif
513 #define CONFIG_SYS_QE_FMAN_FW_LENGTH    0x10000
514 #define CONFIG_SYS_FDT_PAD              (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
515
516 #ifdef CONFIG_SYS_DPAA_FMAN
517 #define CONFIG_FMAN_ENET
518 #define CONFIG_PHYLIB_10G
519 #define CONFIG_PHY_VITESSE
520 #define CONFIG_PHY_TERANETICS
521 #endif
522
523 #ifdef CONFIG_PCI
524 #define CONFIG_PCI_INDIRECT_BRIDGE
525
526 #define CONFIG_PCI_SCAN_SHOW            /* show pci devices on startup */
527 #endif  /* CONFIG_PCI */
528
529 /* SATA */
530 #define CONFIG_FSL_SATA_V2
531
532 #ifdef CONFIG_FSL_SATA_V2
533 #define CONFIG_FSL_SATA
534 #define CONFIG_LIBATA
535
536 #define CONFIG_SYS_SATA_MAX_DEVICE      2
537 #define CONFIG_SATA1
538 #define CONFIG_SYS_SATA1                CONFIG_SYS_MPC85xx_SATA1_ADDR
539 #define CONFIG_SYS_SATA1_FLAGS          FLAGS_DMA
540 #define CONFIG_SATA2
541 #define CONFIG_SYS_SATA2                CONFIG_SYS_MPC85xx_SATA2_ADDR
542 #define CONFIG_SYS_SATA2_FLAGS          FLAGS_DMA
543
544 #define CONFIG_LBA48
545 #endif
546
547 #ifdef CONFIG_FMAN_ENET
548 #define CONFIG_SYS_FM1_DTSEC1_PHY_ADDR  0x2
549 #define CONFIG_SYS_FM1_DTSEC2_PHY_ADDR  0x3
550 #define CONFIG_SYS_FM1_DTSEC3_PHY_ADDR  0x4
551 #define CONFIG_SYS_FM1_DTSEC4_PHY_ADDR  0x1
552 #define CONFIG_SYS_FM1_DTSEC5_PHY_ADDR  0x0
553
554 #define CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR    0x1c
555 #define CONFIG_SYS_FM1_DTSEC2_RISER_PHY_ADDR    0x1d
556 #define CONFIG_SYS_FM1_DTSEC3_RISER_PHY_ADDR    0x1e
557 #define CONFIG_SYS_FM1_DTSEC4_RISER_PHY_ADDR    0x1f
558
559 #define CONFIG_SYS_FM1_10GEC1_PHY_ADDR  0
560
561 #define CONFIG_SYS_TBIPA_VALUE  8
562 #define CONFIG_MII              /* MII PHY management */
563 #define CONFIG_ETHPRIME         "FM1@DTSEC1"
564 #define CONFIG_PHY_GIGE         /* Include GbE speed/duplex detection */
565 #endif
566
567 /*
568  * Environment
569  */
570 #define CONFIG_LOADS_ECHO               /* echo on for serial download */
571 #define CONFIG_SYS_LOADS_BAUD_CHANGE    /* allow baudrate change */
572
573 /*
574  * Command line configuration.
575  */
576
577 #ifdef CONFIG_PCI
578 #define CONFIG_CMD_PCI
579 #endif
580
581 /*
582 * USB
583 */
584 #define CONFIG_HAS_FSL_DR_USB
585 #define CONFIG_HAS_FSL_MPH_USB
586
587 #if defined(CONFIG_HAS_FSL_DR_USB) || defined(CONFIG_HAS_FSL_MPH_USB)
588 #define CONFIG_USB_EHCI_FSL
589 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
590 #endif
591
592 #ifdef CONFIG_MMC
593 #define CONFIG_FSL_ESDHC
594 #define CONFIG_SYS_FSL_ESDHC_ADDR       CONFIG_SYS_MPC85xx_ESDHC_ADDR
595 #define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT
596 #endif
597
598 /*
599  * Miscellaneous configurable options
600  */
601 #define CONFIG_SYS_LONGHELP                     /* undef to save memory */
602 #define CONFIG_CMDLINE_EDITING                  /* Command-line editing */
603 #define CONFIG_AUTO_COMPLETE                    /* add autocompletion support */
604 #define CONFIG_SYS_LOAD_ADDR    0x2000000       /* default load address */
605 #ifdef CONFIG_CMD_KGDB
606 #define CONFIG_SYS_CBSIZE       1024            /* Console I/O Buffer Size */
607 #else
608 #define CONFIG_SYS_CBSIZE       256             /* Console I/O Buffer Size */
609 #endif
610 /* Print Buffer Size */
611 #define CONFIG_SYS_PBSIZE       (CONFIG_SYS_CBSIZE + \
612                                 sizeof(CONFIG_SYS_PROMPT)+16)
613 #define CONFIG_SYS_MAXARGS      16              /* max number of command args */
614 /* Boot Argument Buffer Size */
615 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE
616
617 /*
618  * For booting Linux, the board info and command line data
619  * have to be in the first 64 MB of memory, since this is
620  * the maximum mapped by the Linux kernel during initialization.
621  */
622 #define CONFIG_SYS_BOOTMAPSZ    (64 << 20)      /* Initial Memory for Linux */
623 #define CONFIG_SYS_BOOTM_LEN    (64 << 20)      /* Increase max gunzip size */
624
625 #ifdef CONFIG_CMD_KGDB
626 #define CONFIG_KGDB_BAUDRATE    230400  /* speed to run kgdb serial port */
627 #endif
628
629 /*
630  * Environment Configuration
631  */
632 #define CONFIG_ROOTPATH         "/opt/nfsroot"
633 #define CONFIG_BOOTFILE         "uImage"
634 #define CONFIG_UBOOTPATH        u-boot.bin
635
636 /* default location for tftp and bootm */
637 #define CONFIG_LOADADDR         1000000
638
639 #define __USB_PHY_TYPE  utmi
640
641 #define CONFIG_EXTRA_ENV_SETTINGS                               \
642         "hwconfig=fsl_ddr:ctlr_intlv=cacheline,"                \
643         "bank_intlv=cs0_cs1\0"                                  \
644         "netdev=eth0\0"                                         \
645         "uboot=" __stringify(CONFIG_UBOOTPATH) "\0"                     \
646         "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0"             \
647         "tftpflash=tftpboot $loadaddr $uboot && "               \
648         "protect off $ubootaddr +$filesize && "                 \
649         "erase $ubootaddr +$filesize && "                       \
650         "cp.b $loadaddr $ubootaddr $filesize && "               \
651         "protect on $ubootaddr +$filesize && "                  \
652         "cmp.b $loadaddr $ubootaddr $filesize\0"                \
653         "consoledev=ttyS0\0"                                    \
654         "usb_phy_type=" __stringify(__USB_PHY_TYPE) "\0"                \
655         "usb_dr_mode=host\0"                                    \
656         "ramdiskaddr=2000000\0"                                 \
657         "ramdiskfile=p2041rdb/ramdisk.uboot\0"                  \
658         "fdtaddr=1e00000\0"                                     \
659         "fdtfile=p2041rdb/p2041rdb.dtb\0"                       \
660         "bdev=sda3\0"
661
662 #define CONFIG_HDBOOT                                   \
663         "setenv bootargs root=/dev/$bdev rw "           \
664         "console=$consoledev,$baudrate $othbootargs;"   \
665         "tftp $loadaddr $bootfile;"                     \
666         "tftp $fdtaddr $fdtfile;"                       \
667         "bootm $loadaddr - $fdtaddr"
668
669 #define CONFIG_NFSBOOTCOMMAND                   \
670         "setenv bootargs root=/dev/nfs rw "     \
671         "nfsroot=$serverip:$rootpath "          \
672         "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
673         "console=$consoledev,$baudrate $othbootargs;"   \
674         "tftp $loadaddr $bootfile;"             \
675         "tftp $fdtaddr $fdtfile;"               \
676         "bootm $loadaddr - $fdtaddr"
677
678 #define CONFIG_RAMBOOTCOMMAND                           \
679         "setenv bootargs root=/dev/ram rw "             \
680         "console=$consoledev,$baudrate $othbootargs;"   \
681         "tftp $ramdiskaddr $ramdiskfile;"               \
682         "tftp $loadaddr $bootfile;"                     \
683         "tftp $fdtaddr $fdtfile;"                       \
684         "bootm $loadaddr $ramdiskaddr $fdtaddr"
685
686 #define CONFIG_BOOTCOMMAND              CONFIG_HDBOOT
687
688 #include <asm/fsl_secure_boot.h>
689
690 #endif  /* __CONFIG_H */