3 * Denis Peter d.peter@mpl.ch
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
31 * High Level Configuration Options
34 #define CONFIG_MPC555 1 /* This is an MPC555 CPU */
35 #define CONFIG_PATI 1 /* ...On a PATI board */
36 /* Serial Console Configuration */
37 #define CONFIG_5xx_CONS_SCI1
38 #undef CONFIG_5xx_CONS_SCI2
40 #define CONFIG_BAUDRATE 9600
44 * Command line configuration.
46 #define CONFIG_CMD_MEMORY
47 #define CONFIG_CMD_LOADB
48 #define CONFIG_CMD_REGINFO
49 #define CONFIG_CMD_FLASH
50 #define CONFIG_CMD_LOADS
51 #define CONFIG_CMD_ENV
52 #define CONFIG_CMD_REGINFO
53 #define CONFIG_CMD_BDI
54 #define CONFIG_CMD_CONSOLE
55 #define CONFIG_CMD_RUN
56 #define CONFIG_CMD_BSP
57 #define CONFIG_CMD_IMI
58 #define CONFIG_CMD_EEPROM
59 #define CONFIG_CMD_IRQ
60 #define CONFIG_CMD_MISC
64 #define CONFIG_BOOTDELAY -1 /* autoboot disabled */
66 #define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
68 #define CONFIG_BOOTCOMMAND "" /* autoboot command */
70 #define CONFIG_BOOTARGS "" /* */
72 #define CONFIG_WATCHDOG /* turn on platform specific watchdog */
74 /*#define CONFIG_STATUS_LED 1 */ /* Enable status led */
76 #define CONFIG_LOADS_ECHO 1 /* Echo on for serial download */
79 * Miscellaneous configurable options
81 #define CFG_CONSOLE_IS_IN_ENV /* stdin, stdout and stderr are in evironment */
82 #define CONFIG_PREBOOT
84 #define CFG_LONGHELP /* undef to save memory */
85 #define CFG_PROMPT "pati=> " /* Monitor Command Prompt */
86 #if defined(CONFIG_CMD_KGDB)
87 #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
89 #define CFG_CBSIZE 256 /* Console I/O Buffer Size */
91 #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
92 #define CFG_MAXARGS 16 /* max number of command args */
93 #define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
95 #define CFG_MEMTEST_START 0x00010000 /* memtest works on */
96 #define CFG_MEMTEST_END 0x00A00000 /* 10 MB in SRAM */
98 #define CFG_LOAD_ADDR 0x100000 /* default load address */
100 #define CFG_HZ 1000 /* Decrementer freq: 1 ms ticks */
102 #define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 1250000 }
105 /***********************************************************************
107 ***********************************************************************/
108 #define CONFIG_LAST_STAGE_INIT
111 * Low Level Configuration Settings
115 * Internal Memory Mapped (This is not the IMMR content)
117 #define CFG_IMMR 0x01C00000 /* Physical start adress of internal memory map */
120 * Definitions for initial stack pointer and data area
122 #define CFG_INIT_RAM_ADDR (CFG_IMMR + 0x003f9800) /* Physical start adress of internal MPC555 writable RAM */
123 #define CFG_INIT_RAM_END (CFG_IMMR + 0x003fffff) /* Physical end adress of internal MPC555 used RAM area */
124 #define CFG_GBL_DATA_SIZE 128 /* Size in bytes reserved for initial global data */
125 #define CFG_GBL_DATA_OFFSET ((CFG_INIT_RAM_END - CFG_INIT_RAM_ADDR) - CFG_GBL_DATA_SIZE) /* Offset from the beginning of ram */
126 #define CFG_INIT_SP_ADDR (CFG_IMMR + 0x03fa000) /* Physical start adress of inital stack */
128 * Start addresses for the final memory configuration
129 * Please note that CFG_SDRAM_BASE _must_ start at 0
131 #define CFG_SDRAM_BASE 0x00000000 /* Monitor won't change memory map */
132 #define CFG_FLASH_BASE 0xffC00000 /* External flash */
133 #define PCI_BASE 0x03000000 /* PCI Base (CS2) */
134 #define PCI_CONFIG_BASE 0x04000000 /* PCI & PLD (CS3) */
135 #define PLD_CONFIG_BASE 0x04001000 /* PLD (CS3) */
137 #define CFG_MONITOR_BASE 0xFFF00000
138 /* CFG_FLASH_BASE */ /* TEXT_BASE is defined in the board config.mk file. */
139 /* This adress is given to the linker with -Ttext to */
140 /* locate the text section at this adress. */
141 #define CFG_MONITOR_LEN (256 << 10) /* Reserve 192 kB for Monitor */
142 #define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
144 #define CFG_RESET_ADDRESS (PLD_CONFIG_BASE + 0x10) /* Adress which causes reset */
147 * For booting Linux, the board info and command line data
148 * have to be in the first 8 MB of memory, since this is
149 * the maximum mapped by the Linux kernel during initialization.
151 #define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
154 /*-----------------------------------------------------------------------
156 *-----------------------------------------------------------------------
160 #define CFG_MAX_FLASH_BANKS 1 /* Max number of memory banks */
161 #define CFG_MAX_FLASH_SECT 128 /* Max number of sectors on one chip */
162 #define CFG_FLASH_ERASE_TOUT 180000 /* Timeout for Flash Erase (in ms) */
163 #define CFG_FLASH_WRITE_TOUT 600 /* Timeout for Flash Write (in ms) */
166 #define CFG_ENV_IS_IN_EEPROM
167 #ifdef CFG_ENV_IS_IN_EEPROM
168 #define CFG_ENV_OFFSET 0
169 #define CFG_ENV_SIZE 2048
172 #undef CFG_ENV_IS_IN_FLASH
173 #ifdef CFG_ENV_IS_IN_FLASH
174 #define CFG_ENV_SIZE 0x00002000 /* Set whole sector as env */
175 #define CFG_ENV_OFFSET ((0 - CFG_FLASH_BASE) - CFG_ENV_SIZE) /* Environment starts at this adress */
180 #define CFG_SPI_CS_USED 0x09 /* CS0 and CS3 are used */
181 #define CFG_SPI_CS_BASE 0x08 /* CS3 is active low */
182 #define CFG_SPI_CS_ACT 0x00 /* CS3 is active low */
183 /*-----------------------------------------------------------------------
184 * SYPCR - System Protection Control
185 * SYPCR can only be written once after reset!
186 *-----------------------------------------------------------------------
189 #undef CONFIG_WATCHDOG
190 #if defined(CONFIG_WATCHDOG)
191 #define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
192 SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP)
194 #define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
196 #endif /* CONFIG_WATCHDOG */
198 /*-----------------------------------------------------------------------
199 * TBSCR - Time Base Status and Control
200 *-----------------------------------------------------------------------
201 * Clear Reference Interrupt Status, Timebase freezing enabled
203 #define CFG_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
205 /*-----------------------------------------------------------------------
206 * PISCR - Periodic Interrupt Status and Control
207 *-----------------------------------------------------------------------
208 * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
210 #define CFG_PISCR (PISCR_PS | PISCR_PITF)
212 /*-----------------------------------------------------------------------
213 * SCCR - System Clock and reset Control Register
214 *-----------------------------------------------------------------------
215 * Set clock output, timebase and RTC source and divider,
216 * power management and some other internal clocks
218 #define SCCR_MASK SCCR_EBDF00
219 #define CFG_SCCR (SCCR_TBS | SCCR_RTDIV | SCCR_RTSEL | \
220 SCCR_COM01 | SCCR_DFNL000 | SCCR_DFNH000)
222 /*-----------------------------------------------------------------------
223 * SIUMCR - SIU Module Configuration
224 *-----------------------------------------------------------------------
227 #define CFG_SIUMCR (SIUMCR_DBGC00 | SIUMCR_EARB | SIUMCR_GPC01 | SIUMCR_MLRC11) /* Disable data show cycle */
229 /*-----------------------------------------------------------------------
230 * PLPRCR - PLL, Low-Power, and Reset Control Register
231 *-----------------------------------------------------------------------
232 * Set all bits to 40 Mhz
235 #define CFG_OSC_CLK ((uint)4000000) /* Oscillator clock is 4MHz */
238 #define CFG_PLPRCR (PLPRCR_MF_9 | PLPRCR_DIVF_0)
240 /*-----------------------------------------------------------------------
241 * UMCR - UIMB Module Configuration Register
242 *-----------------------------------------------------------------------
245 #define CFG_UMCR (UMCR_FSPEED) /* IMB clock same as U-bus */
247 /*-----------------------------------------------------------------------
248 * ICTRL - I-Bus Support Control Register
250 #define CFG_ICTRL (ICTRL_ISCT_SER_7) /* Take out of serialized mode */
252 /*-----------------------------------------------------------------------
253 * USIU - Memory Controller Register
254 *-----------------------------------------------------------------------
256 #define CFG_BR0_PRELIM (CFG_FLASH_BASE | BR_V | BR_BI | BR_PS_16 | BR_SETA)
257 #define CFG_OR0_PRELIM (0xffc00000) /* SCY is not used if external TA is set */
259 #define CFG_BR1_PRELIM (CFG_SDRAM_BASE | BR_V | BR_BI | BR_PS_32 | BR_SETA)
260 #define CFG_OR1_PRELIM (OR_ADDR_MK_FF) /* SCY is not used if external TA is set */
262 #define CFG_BR2_PRELIM (PCI_BASE | BR_V | BR_PS_32 | BR_SETA)
263 #define CFG_OR2_PRELIM (OR_ADDR_MK_FF)
264 /* config registers: */
265 #define CFG_BR3_PRELIM (PCI_CONFIG_BASE | BR_V | BR_BI | BR_PS_32 | BR_SETA)
266 #define CFG_OR3_PRELIM (0xffff0000)
268 #define FLASH_BASE0_PRELIM CFG_FLASH_BASE /* We don't realign the flash */
270 /*-----------------------------------------------------------------------
271 * DER - Timer Decrementer
272 *-----------------------------------------------------------------------
275 #define CFG_DER 0x00000000
279 * Internal Definitions
283 #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
284 #define BOOTFLAG_WARM 0x02 /* Software reboot */
287 #define VERSION_TAG "released"
288 #define CONFIG_ISO_STRING "MEV-10084-001"
290 #define CONFIG_IDENT_STRING "\n(c) 2003 by MPL AG Switzerland, " CONFIG_ISO_STRING " " VERSION_TAG
292 #endif /* __CONFIG_H */