3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
25 * board/config.h - configuration options, board specific
31 /***********************************************************
32 * High Level Configuration Options
34 ***********************************************************/
35 #define CONFIG_405GP 1 /* This is a PPC405 CPU */
36 #define CONFIG_4xx 1 /* ...member of PPC4xx family */
37 #define CONFIG_PIP405 1 /* ...on a PIP405 board */
38 /***********************************************************
40 ***********************************************************/
41 #define CONFIG_SYS_CLK_FREQ 33000000 /* external frequency to pll */
43 /***********************************************************
45 ***********************************************************/
46 #define CONFIG_COMMANDS \
67 /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
68 #include <cmd_confdefs.h>
70 #define CFG_HUSH_PARSER
71 #define CFG_PROMPT_HUSH_PS2 "> "
72 /**************************************************************
74 * the PIP405 is equiped with an Atmel 24C128/256 EEPROM at address
76 * Caution: on the same bus is the SPD (Serial Presens Detect
78 * The Atmel EEPROM uses 16Bit addressing.
79 ***************************************************************/
80 #define CONFIG_HARD_I2C /* I2c with hardware support */
81 #define CFG_I2C_SPEED 50000 /* I2C speed and slave address */
82 #define CFG_I2C_SLAVE 0x7F
84 #define CFG_I2C_EEPROM_ADDR 0x53
85 #define CFG_I2C_EEPROM_ADDR_LEN 2
86 #define CFG_ENV_IS_IN_EEPROM 1 /* use EEPROM for environment vars */
87 #define CFG_ENV_OFFSET 0x000 /* environment starts at the beginning of the EEPROM */
88 #define CFG_ENV_SIZE 0x800 /* 2 kBytes may be used for env vars */
90 #undef CFG_I2C_EEPROM_ADDR_OVERFLOW
91 #define CFG_EEPROM_PAGE_WRITE_BITS 6 /* The Atmel 24C128/256 has */
92 /* 64 byte page write mode using*/
93 /* last 6 bits of the address */
94 #define CFG_EEPROM_PAGE_WRITE_ENABLE /* enable Page write */
95 #define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */
98 /***************************************************************
99 * Definitions for Serial Presence Detect EEPROM address
100 * (to get SDRAM settings)
101 ***************************************************************/
102 #define SPD_EEPROM_ADDRESS 0x50
104 #define CONFIG_BOARD_PRE_INIT
105 /**************************************************************
106 * Environment definitions
107 **************************************************************/
108 #define CONFIG_BAUDRATE 9600 /* STD Baudrate */
111 #define CONFIG_BOOTDELAY 5
112 /* autoboot (do NOT change this set environment variable "bootdelay" to -1 instead) */
113 #define CONFIG_BOOT_RETRY_TIME -10 /* feature is avaiable but not enabled */
114 #define CONFIG_ZERO_BOOTDELAY_CHECK /* check console even if bootdelay = 0 */
117 #define CONFIG_BOOTCOMMAND "diskboot 400000 0:1; bootm" /* autoboot command */
118 #define CONFIG_BOOTARGS "console=ttyS0,9600 root=/dev/hda5" /* boot arguments */
120 #define CONFIG_IPADDR 10.0.0.100
121 #define CONFIG_SERVERIP 10.0.0.1
122 #define CONFIG_PREBOOT
123 /***************************************************************
124 * defines if the console is stored in the environment
125 ***************************************************************/
126 #define CFG_CONSOLE_IS_IN_ENV /* stdin, stdout and stderr are in evironment */
127 /***************************************************************
128 * defines if an overwrite_console function exists
129 *************************************************************/
130 #define CFG_CONSOLE_OVERWRITE_ROUTINE
131 #define CFG_CONSOLE_INFO_QUIET
132 /***************************************************************
133 * defines if the overwrite_console should be stored in the
135 **************************************************************/
136 #undef CFG_CONSOLE_ENV_OVERWRITE
138 /**************************************************************
140 *************************************************************/
141 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
142 #define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
145 /***********************************************************
146 * Miscellaneous configurable options
147 **********************************************************/
148 #define CFG_LONGHELP /* undef to save memory */
149 #define CFG_PROMPT "=> " /* Monitor Command Prompt */
150 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
151 #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
153 #define CFG_CBSIZE 256 /* Console I/O Buffer Size */
155 #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
156 #define CFG_MAXARGS 16 /* max number of command args */
157 #define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
159 #define CFG_MEMTEST_START 0x0100000 /* memtest works on */
160 #define CFG_MEMTEST_END 0x0C00000 /* 1 ... 12 MB in DRAM */
162 #undef CFG_EXT_SERIAL_CLOCK /* no external serial clock used */
163 #define CFG_BASE_BAUD 691200
165 /* The following table includes the supported baudrates */
166 #define CFG_BAUDRATE_TABLE \
167 { 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, \
168 57600, 115200, 230400, 460800, 921600 }
170 #define CFG_LOAD_ADDR 0x400000 /* default load address */
171 #define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */
173 #define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
175 /*-----------------------------------------------------------------------
177 *-----------------------------------------------------------------------
179 #define PCI_HOST_ADAPTER 0 /* configure ar pci adapter */
180 #define PCI_HOST_FORCE 1 /* configure as pci host */
181 #define PCI_HOST_AUTO 2 /* detected via arbiter enable */
183 #define CONFIG_PCI /* include pci support */
184 #define CONFIG_PCI_HOST PCI_HOST_FORCE /* configure as pci-host */
185 #define CONFIG_PCI_PNP /* pci plug-and-play */
186 /* resource configuration */
187 #define CFG_PCI_SUBSYS_VENDORID 0x0000 /* PCI Vendor ID: to-do!!! */
188 #define CFG_PCI_SUBSYS_DEVICEID 0x0000 /* PCI Device ID: to-do!!! */
189 #define CFG_PCI_PTM1LA 0x00000000 /* point to sdram */
190 #define CFG_PCI_PTM1MS 0x80000001 /* 2GB, enable hard-wired to 1 */
191 #define CFG_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */
192 #define CFG_PCI_PTM2LA 0x00000000 /* disabled */
193 #define CFG_PCI_PTM2MS 0x00000000 /* disabled */
194 #define CFG_PCI_PTM2PCI 0x00000000 /* Host: use this pci address */
196 /*-----------------------------------------------------------------------
197 * Start addresses for the final memory configuration
198 * (Set up by the startup code)
199 * Please note that CFG_SDRAM_BASE _must_ start at 0
201 #define CFG_SDRAM_BASE 0x00000000
202 #define CFG_FLASH_BASE 0xFFF80000
203 #define CFG_MONITOR_BASE CFG_FLASH_BASE
204 #define CFG_MONITOR_LEN (512 * 1024) /* Reserve 512 kB for Monitor */
205 #define CFG_MALLOC_LEN (128 * 1024) /* Reserve 128 kB for malloc() */
208 * For booting Linux, the board info and command line data
209 * have to be in the first 8 MB of memory, since this is
210 * the maximum mapped by the Linux kernel during initialization.
212 #define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
213 /*-----------------------------------------------------------------------
216 #define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
217 #define CFG_MAX_FLASH_SECT 256 /* max number of sectors on one chip */
219 #define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
220 #define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
222 /*-----------------------------------------------------------------------
223 * Cache Configuration
225 #define CFG_DCACHE_SIZE 8192 /* For IBM 405 CPUs */
226 #define CFG_CACHELINE_SIZE 32 /* ... */
227 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
228 #define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
232 * Init Memory Controller:
235 #define FLASH_BASE0_PRELIM 0xFFC00000 /* FLASH bank #0 */
236 #define FLASH_BASE1_PRELIM 0 /* FLASH bank #1 */
238 /* Configuration Port location */
239 #define CONFIG_PORT_ADDR 0xF4000000
240 #define MULTI_PURPOSE_SOCKET_ADDR 0xF8000000
243 /*-----------------------------------------------------------------------
244 * Definitions for initial stack pointer and data area (in On Chip SRAM)
246 #define CFG_TEMP_STACK_OCM 1
247 #define CFG_OCM_DATA_ADDR 0xF0000000
248 #define CFG_OCM_DATA_SIZE 0x1000
249 #define CFG_INIT_RAM_ADDR CFG_OCM_DATA_ADDR /* inside of On Chip SRAM */
250 #define CFG_INIT_RAM_END CFG_OCM_DATA_SIZE /* End of On Chip SRAM */
251 #define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */
252 #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
253 #define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
256 * Internal Definitions
260 #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
261 #define BOOTFLAG_WARM 0x02 /* Software reboot */
264 /***********************************************************************
265 * External peripheral base address
266 ***********************************************************************/
267 #define CFG_ISA_IO_BASE_ADDRESS 0xE8000000
269 /***********************************************************************
271 ***********************************************************************/
272 #define CONFIG_LAST_STAGE_INIT
273 /************************************************************
275 ***********************************************************/
276 #define CONFIG_MII 1 /* MII PHY management */
277 #define CONFIG_PHY_ADDR 1 /* PHY address */
278 #define CONFIG_CS8952_PHY 1 /* its a CS8952 PHY */
279 /************************************************************
281 ***********************************************************/
282 #define CONFIG_RTC_MC146818
283 #undef CONFIG_WATCHDOG /* watchdog disabled */
285 /************************************************************
287 ************************************************************/
288 #define CFG_IDE_MAXBUS 2 /* max. 2 IDE busses */
289 #define CFG_IDE_MAXDEVICE (CFG_IDE_MAXBUS*2) /* max. 2 drives per IDE bus */
291 #define CFG_ATA_BASE_ADDR CFG_ISA_IO_BASE_ADDRESS /* base address */
292 #define CFG_ATA_IDE0_OFFSET 0x01F0 /* ide0 offste */
293 #define CFG_ATA_IDE1_OFFSET 0x0170 /* ide1 offset */
294 #define CFG_ATA_DATA_OFFSET 0 /* data reg offset */
295 #define CFG_ATA_REG_OFFSET 0 /* reg offset */
296 #define CFG_ATA_ALT_OFFSET 0x200 /* alternate register offset */
298 #undef CONFIG_IDE_8xx_DIRECT /* no pcmcia interface required */
299 #undef CONFIG_IDE_LED /* no led for ide supported */
300 #define CONFIG_IDE_RESET /* reset for ide supported... */
301 #define CONFIG_IDE_RESET_ROUTINE /* with a special reset function */
303 /************************************************************
304 * ATAPI support (experimental)
305 ************************************************************/
306 #define CONFIG_ATAPI /* enable ATAPI Support */
308 /************************************************************
309 * SCSI support (experimental) only SYM53C8xx supported
310 ************************************************************/
311 #define CONFIG_SCSI_SYM53C8XX
312 #define CFG_SCSI_MAX_LUN 8 /* number of supported LUNs */
313 #define CFG_SCSI_MAX_SCSI_ID 7 /* maximum SCSI ID (0..6) */
314 #define CFG_SCSI_MAX_DEVICE CFG_SCSI_MAX_SCSI_ID * CFG_SCSI_MAX_LUN /* maximum Target devices */
315 #define CFG_SCSI_SPIN_UP_TIME 2
317 /************************************************************
318 * Disk-On-Chip configuration
319 ************************************************************/
320 #define CFG_MAX_DOC_DEVICE 1 /* Max number of DOC devices */
321 #define CFG_DOC_SHORT_TIMEOUT
322 #define CFG_DOC_SUPPORT_2000
323 #define CFG_DOC_SUPPORT_MILLENNIUM
325 /************************************************************
326 * DISK Partition support
327 ************************************************************/
328 #define CONFIG_DOS_PARTITION
329 #define CONFIG_MAC_PARTITION
330 #define CONFIG_ISO_PARTITION /* Experimental */
332 /************************************************************
334 ************************************************************/
335 #define CONFIG_ISA_KEYBOARD
337 /************************************************************
339 ************************************************************/
340 #define CONFIG_VIDEO /*To enable video controller support */
341 #define CONFIG_VIDEO_CT69000
342 #define CONFIG_CFB_CONSOLE
343 #define CONFIG_VIDEO_LOGO
344 #define CONFIG_CONSOLE_EXTRA_INFO
345 #define CONFIG_VGA_AS_SINGLE_DEVICE
346 #define CONFIG_VIDEO_SW_CURSOR
347 #define CONFIG_VIDEO_ONBOARD /* Video controller is on-board */
349 /************************************************************
351 ************************************************************/
352 #define CONFIG_USB_UHCI
353 #define CONFIG_USB_KEYBOARD
354 #define CONFIG_USB_STORAGE
356 /* Enable needed helper functions */
357 #define CFG_DEVICE_DEREGISTER /* needs device_deregister */
359 /************************************************************
361 ************************************************************/
362 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
363 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
364 #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
367 /************************************************************
369 ************************************************************/
370 #define VERSION_TAG "released"
371 #define CONFIG_ISO_STRING "MEV-10066-001"
372 #define CONFIG_IDENT_STRING "\n(c) 2002 by MPL AG Switzerland, " CONFIG_ISO_STRING " " VERSION_TAG
375 #endif /* __CONFIG_H */