3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
5 * SPDX-License-Identifier: GPL-2.0+
9 * board/config.h - configuration options, board specific
15 /***********************************************************
16 * High Level Configuration Options
18 ***********************************************************/
19 #define CONFIG_405GP 1 /* This is a PPC405 CPU */
20 #define CONFIG_PIP405 1 /* ...on a PIP405 board */
22 #define CONFIG_SYS_TEXT_BASE 0xFFF80000
24 /***********************************************************
26 ***********************************************************/
27 #define CONFIG_SYS_CLK_FREQ 33000000 /* external frequency to pll */
32 #define CONFIG_BOOTP_BOOTFILESIZE
33 #define CONFIG_BOOTP_BOOTPATH
34 #define CONFIG_BOOTP_GATEWAY
35 #define CONFIG_BOOTP_HOSTNAME
38 * Command line configuration.
40 #define CONFIG_CMD_IDE
41 #define CONFIG_CMD_PCI
42 #define CONFIG_CMD_IRQ
43 #define CONFIG_CMD_EEPROM
44 #define CONFIG_CMD_REGINFO
45 #define CONFIG_CMD_FDC
47 #define CONFIG_CMD_DATE
48 #define CONFIG_CMD_SDRAM
49 #define CONFIG_CMD_SAVES
50 #define CONFIG_CMD_BSP
52 /**************************************************************
54 * the PIP405 is equiped with an Atmel 24C128/256 EEPROM at address
56 * Caution: on the same bus is the SPD (Serial Presens Detect
58 * The Atmel EEPROM uses 16Bit addressing.
59 ***************************************************************/
60 #define CONFIG_SYS_I2C
61 #define CONFIG_SYS_I2C_PPC4XX
62 #define CONFIG_SYS_I2C_PPC4XX_CH0
63 #define CONFIG_SYS_I2C_PPC4XX_SPEED_0 50000
64 #define CONFIG_SYS_I2C_PPC4XX_SLAVE_0 0x7F
66 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x53
67 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
68 #define CONFIG_ENV_IS_IN_EEPROM 1 /* use EEPROM for environment vars */
69 #define CONFIG_ENV_OFFSET 0x000 /* environment starts at the beginning of the EEPROM */
70 #define CONFIG_ENV_SIZE 0x800 /* 2 kBytes may be used for env vars */
72 #undef CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW
73 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 6 /* The Atmel 24C128/256 has */
74 /* 64 byte page write mode using*/
75 /* last 6 bits of the address */
76 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */
78 /***************************************************************
79 * Definitions for Serial Presence Detect EEPROM address
80 * (to get SDRAM settings)
81 ***************************************************************/
82 #define SPD_EEPROM_ADDRESS 0x50
84 #define CONFIG_BOARD_EARLY_INIT_F
85 #define CONFIG_BOARD_EARLY_INIT_R
87 /**************************************************************
88 * Environment definitions
89 **************************************************************/
90 #define CONFIG_BAUDRATE 9600 /* STD Baudrate */
92 /* autoboot (do NOT change this set environment variable "bootdelay" to -1 instead) */
93 /* #define CONFIG_BOOT_RETRY_TIME -10 /XXX* feature is available but not enabled */
95 #define CONFIG_BOOTCOMMAND "diskboot 400000 0:1; bootm" /* autoboot command */
96 #define CONFIG_BOOTARGS "console=ttyS0,9600 root=/dev/hda5" /* boot arguments */
98 #define CONFIG_IPADDR 10.0.0.100
99 #define CONFIG_SERVERIP 10.0.0.1
100 #define CONFIG_PREBOOT
101 /***************************************************************
102 * defines if an overwrite_console function exists
103 *************************************************************/
104 #define CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE
105 #define CONFIG_SYS_CONSOLE_INFO_QUIET
106 /***************************************************************
107 * defines if the overwrite_console should be stored in the
109 **************************************************************/
110 #undef CONFIG_SYS_CONSOLE_ENV_OVERWRITE
112 /**************************************************************
114 *************************************************************/
115 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
116 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
118 #define CONFIG_MISC_INIT_R
119 /***********************************************************
120 * Miscellaneous configurable options
121 **********************************************************/
122 #define CONFIG_SYS_LONGHELP /* undef to save memory */
123 #if defined(CONFIG_CMD_KGDB)
124 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
126 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
128 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
129 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */
130 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
132 #define CONFIG_SYS_MEMTEST_START 0x0100000 /* memtest works on */
133 #define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 1 ... 12 MB in DRAM */
135 #define CONFIG_CONS_INDEX 1 /* Use UART0 */
136 #define CONFIG_SYS_NS16550_SERIAL
137 #define CONFIG_SYS_NS16550_REG_SIZE 1
138 #define CONFIG_SYS_NS16550_CLK get_serial_clock()
140 #undef CONFIG_SYS_EXT_SERIAL_CLOCK /* no external serial clock used */
141 #define CONFIG_SYS_BASE_BAUD 691200
143 /* The following table includes the supported baudrates */
144 #define CONFIG_SYS_BAUDRATE_TABLE \
145 { 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, \
146 57600, 115200, 230400, 460800, 921600 }
148 #define CONFIG_SYS_LOAD_ADDR 0x400000 /* default load address */
149 #define CONFIG_SYS_EXTBDINFO 1 /* To use extended board_into (bd_t) */
151 /*-----------------------------------------------------------------------
153 *-----------------------------------------------------------------------
155 #define PCI_HOST_ADAPTER 0 /* configure ar pci adapter */
156 #define PCI_HOST_FORCE 1 /* configure as pci host */
157 #define PCI_HOST_AUTO 2 /* detected via arbiter enable */
159 #define CONFIG_PCI /* include pci support */
160 #define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */
161 #define CONFIG_PCI_HOST PCI_HOST_FORCE /* configure as pci-host */
162 #define CONFIG_PCI_PNP /* pci plug-and-play */
163 /* resource configuration */
164 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x0000 /* PCI Vendor ID: to-do!!! */
165 #define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0x0000 /* PCI Device ID: to-do!!! */
166 #define CONFIG_SYS_PCI_PTM1LA 0x00000000 /* point to sdram */
167 #define CONFIG_SYS_PCI_PTM1MS 0x80000001 /* 2GB, enable hard-wired to 1 */
168 #define CONFIG_SYS_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */
169 #define CONFIG_SYS_PCI_PTM2LA 0x00000000 /* disabled */
170 #define CONFIG_SYS_PCI_PTM2MS 0x00000000 /* disabled */
171 #define CONFIG_SYS_PCI_PTM2PCI 0x00000000 /* Host: use this pci address */
173 /*-----------------------------------------------------------------------
174 * Start addresses for the final memory configuration
175 * (Set up by the startup code)
176 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
178 #define CONFIG_SYS_SDRAM_BASE 0x00000000
179 #define CONFIG_SYS_FLASH_BASE 0xFFF80000
180 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
181 #define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 kB for Monitor */
182 #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserve 1024 kB for malloc() */
185 * For booting Linux, the board info and command line data
186 * have to be in the first 8 MB of memory, since this is
187 * the maximum mapped by the Linux kernel during initialization.
189 #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
190 /*-----------------------------------------------------------------------
193 #define CONFIG_SYS_UPDATE_FLASH_SIZE
194 #define CONFIG_SYS_FLASH_PROTECTION
195 #define CONFIG_SYS_FLASH_EMPTY_INFO
197 #define CONFIG_SYS_FLASH_CFI
198 #define CONFIG_FLASH_CFI_DRIVER
200 #define CONFIG_FLASH_SHOW_PROGRESS 45
202 #define CONFIG_SYS_MAX_FLASH_BANKS 1
203 #define CONFIG_SYS_MAX_FLASH_SECT 256
206 * Init Memory Controller:
208 #define FLASH_MAX_SIZE 0x00800000 /* 8MByte max */
209 #define FLASH_BASE_PRELIM 0xFF800000 /* open the flash CS */
210 /* Size: 0=1MB, 1=2MB, 2=4MB, 3=8MB, 4=16MB, 5=32MB, 6=64MB, 7=128MB */
211 #define FLASH_SIZE_PRELIM 3 /* maximal flash FLASH size bank #0 */
213 #define CONFIG_BOARD_EARLY_INIT_F
215 /* Configuration Port location */
216 #define CONFIG_PORT_ADDR 0xF4000000
217 #define MULTI_PURPOSE_SOCKET_ADDR 0xF8000000
219 /*-----------------------------------------------------------------------
220 * Definitions for initial stack pointer and data area (in On Chip SRAM)
222 #define CONFIG_SYS_TEMP_STACK_OCM 1
223 #define CONFIG_SYS_OCM_DATA_ADDR 0xF0000000
224 #define CONFIG_SYS_OCM_DATA_SIZE 0x1000
225 #define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_OCM_DATA_ADDR /* inside of On Chip SRAM */
226 #define CONFIG_SYS_INIT_RAM_SIZE CONFIG_SYS_OCM_DATA_SIZE /* Size of On Chip SRAM */
227 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
228 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
230 /***********************************************************************
231 * External peripheral base address
232 ***********************************************************************/
233 #define CONFIG_SYS_ISA_IO_BASE_ADDRESS 0xE8000000
235 /***********************************************************************
237 ***********************************************************************/
238 #define CONFIG_LAST_STAGE_INIT
239 /************************************************************
241 ***********************************************************/
242 #define CONFIG_PPC4xx_EMAC
243 #define CONFIG_MII 1 /* MII PHY management */
244 #define CONFIG_PHY_ADDR 1 /* PHY address */
245 /************************************************************
247 ***********************************************************/
248 #define CONFIG_RTC_MC146818
249 #undef CONFIG_WATCHDOG /* watchdog disabled */
251 /************************************************************
253 ************************************************************/
254 #define CONFIG_SYS_IDE_MAXBUS 2 /* max. 2 IDE busses */
255 #define CONFIG_SYS_IDE_MAXDEVICE (CONFIG_SYS_IDE_MAXBUS*2) /* max. 2 drives per IDE bus */
257 #define CONFIG_SYS_ATA_BASE_ADDR CONFIG_SYS_ISA_IO_BASE_ADDRESS /* base address */
258 #define CONFIG_SYS_ATA_IDE0_OFFSET 0x01F0 /* ide0 offste */
259 #define CONFIG_SYS_ATA_IDE1_OFFSET 0x0170 /* ide1 offset */
260 #define CONFIG_SYS_ATA_DATA_OFFSET 0 /* data reg offset */
261 #define CONFIG_SYS_ATA_REG_OFFSET 0 /* reg offset */
262 #define CONFIG_SYS_ATA_ALT_OFFSET 0x200 /* alternate register offset */
264 #undef CONFIG_IDE_8xx_DIRECT /* no pcmcia interface required */
265 #undef CONFIG_IDE_LED /* no led for ide supported */
266 #define CONFIG_IDE_RESET /* reset for ide supported... */
267 #define CONFIG_IDE_RESET_ROUTINE /* with a special reset function */
268 #define CONFIG_SUPPORT_VFAT
270 /************************************************************
271 * ATAPI support (experimental)
272 ************************************************************/
273 #define CONFIG_ATAPI /* enable ATAPI Support */
275 /************************************************************
276 * SCSI support (experimental) only SYM53C8xx supported
277 ************************************************************/
278 #define CONFIG_SCSI_SYM53C8XX
279 #define CONFIG_SYS_SCSI_MAX_LUN 8 /* number of supported LUNs */
280 #define CONFIG_SYS_SCSI_MAX_SCSI_ID 7 /* maximum SCSI ID (0..6) */
281 #define CONFIG_SYS_SCSI_MAX_DEVICE CONFIG_SYS_SCSI_MAX_SCSI_ID * CONFIG_SYS_SCSI_MAX_LUN /* maximum Target devices */
282 #define CONFIG_SYS_SCSI_SPIN_UP_TIME 2
284 /************************************************************
285 * Disk-On-Chip configuration
286 ************************************************************/
287 #define CONFIG_SYS_MAX_DOC_DEVICE 1 /* Max number of DOC devices */
288 #define CONFIG_SYS_DOC_SHORT_TIMEOUT
289 #define CONFIG_SYS_DOC_SUPPORT_2000
290 #define CONFIG_SYS_DOC_SUPPORT_MILLENNIUM
292 /************************************************************
293 * DISK Partition support
294 ************************************************************/
295 #define CONFIG_DOS_PARTITION
296 #define CONFIG_MAC_PARTITION
297 #define CONFIG_ISO_PARTITION /* Experimental */
299 /************************************************************
301 ************************************************************/
302 #define CONFIG_VIDEO_CT69000
303 #define CONFIG_VIDEO_LOGO
304 #define CONFIG_CONSOLE_EXTRA_INFO
305 #define CONFIG_VGA_AS_SINGLE_DEVICE
306 #define CONFIG_VIDEO_SW_CURSOR
307 #define CONFIG_VIDEO_ONBOARD /* Video controller is on-board */
309 /************************************************************
311 ************************************************************/
312 #define CONFIG_USB_UHCI
313 #define CONFIG_USB_KEYBOARD
315 /* Enable needed helper functions */
316 #define CONFIG_SYS_STDIO_DEREGISTER /* needs stdio_deregister */
318 /************************************************************
320 ************************************************************/
321 #if defined(CONFIG_CMD_KGDB)
322 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
325 /************************************************************
326 * support BZIP2 compression
327 ************************************************************/
328 #define CONFIG_BZIP2 1
330 #endif /* __CONFIG_H */