2 * (C) Copyright 2001-2005
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
25 * board/config.h - configuration options, board specific
31 #undef CONFIG_SYS_RAMBOOT
34 * High Level Configuration Options
38 #define CONFIG_MPC8260 1 /* This is a MPC8260 CPU */
39 #define CONFIG_PM826 1 /* ...on a PM8260 module */
40 #define CONFIG_CPM2 1 /* Has a CPM2 */
42 #ifndef CONFIG_SYS_TEXT_BASE
43 #define CONFIG_SYS_TEXT_BASE 0xFF000000 /* Standard: boot 64-bit flash */
46 #undef CONFIG_DB_CR826_J30x_ON /* J30x jumpers on D.B. carrier */
48 #define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
50 #define CONFIG_PREBOOT "echo;echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;echo"
52 #undef CONFIG_BOOTARGS
53 #define CONFIG_BOOTCOMMAND \
55 "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \
56 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " \
59 /* enable I2C and select the hardware/software driver */
60 #undef CONFIG_HARD_I2C
61 #define CONFIG_SOFT_I2C 1 /* I2C bit-banged */
62 # define CONFIG_SYS_I2C_SPEED 50000
63 # define CONFIG_SYS_I2C_SLAVE 0xFE
65 * Software (bit-bang) I2C driver configuration
67 #define I2C_PORT 3 /* Port A=0, B=1, C=2, D=3 */
68 #define I2C_ACTIVE (iop->pdir |= 0x00010000)
69 #define I2C_TRISTATE (iop->pdir &= ~0x00010000)
70 #define I2C_READ ((iop->pdat & 0x00010000) != 0)
71 #define I2C_SDA(bit) if(bit) iop->pdat |= 0x00010000; \
72 else iop->pdat &= ~0x00010000
73 #define I2C_SCL(bit) if(bit) iop->pdat |= 0x00020000; \
74 else iop->pdat &= ~0x00020000
75 #define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */
78 #define CONFIG_RTC_PCF8563
79 #define CONFIG_SYS_I2C_RTC_ADDR 0x51
82 * select serial console configuration
84 * if either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then
85 * CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4
88 * if CONFIG_CONS_NONE is defined, then the serial console routines must
89 * defined elsewhere (for example, on the cogent platform, there are serial
90 * ports on the motherboard which are used for the serial console - see
91 * cogent/cma101/serial.[ch]).
93 #define CONFIG_CONS_ON_SMC /* define if console on SMC */
94 #undef CONFIG_CONS_ON_SCC /* define if console on SCC */
95 #undef CONFIG_CONS_NONE /* define if console on something else*/
96 #define CONFIG_CONS_INDEX 2 /* which serial channel for console */
99 * select ethernet configuration
101 * if CONFIG_ETHER_ON_SCC is selected, then
102 * - CONFIG_ETHER_INDEX must be set to the channel number (1-4)
103 * - CONFIG_NET_MULTI must not be defined
105 * if CONFIG_ETHER_ON_FCC is selected, then
106 * - one or more CONFIG_ETHER_ON_FCCx (x=1,2,3) must also be selected
107 * - CONFIG_NET_MULTI must be defined
109 * if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be
110 * defined elsewhere (as for the console), or CONFIG_CMD_NET must be unset.
112 #undef CONFIG_ETHER_NONE /* define if ether on something else */
114 #undef CONFIG_ETHER_ON_SCC /* define if ether on SCC */
115 #define CONFIG_ETHER_INDEX 1 /* which SCC channel for ethernet */
117 #define CONFIG_ETHER_ON_FCC /* define if ether on FCC */
122 #define CONFIG_ETHER_ON_FCC1
123 # define CONFIG_SYS_CMXFCR_MASK1 (CMXFCR_FC1|CMXFCR_RF1CS_MSK|CMXFCR_TF1CS_MSK)
124 #ifndef CONFIG_DB_CR826_J30x_ON
125 # define CONFIG_SYS_CMXFCR_VALUE1 (CMXFCR_RF1CS_CLK11|CMXFCR_TF1CS_CLK10)
127 # define CONFIG_SYS_CMXFCR_VALUE1 (CMXFCR_RF1CS_CLK11|CMXFCR_TF1CS_CLK12)
133 #define CONFIG_ETHER_ON_FCC2
134 # define CONFIG_SYS_CMXFCR_MASK2 (CMXFCR_FC2|CMXFCR_RF2CS_MSK|CMXFCR_TF2CS_MSK)
135 # define CONFIG_SYS_CMXFCR_VALUE2 (CMXFCR_RF2CS_CLK13|CMXFCR_TF2CS_CLK14)
137 * - RAM for BD/Buffers is on the 60x Bus (see 28-13)
138 * - Enable Full Duplex in FSMR
140 # define CONFIG_SYS_CPMFCR_RAMTYPE 0
141 # define CONFIG_SYS_FCC_PSMR (FCC_PSMR_FDE|FCC_PSMR_LPB)
143 /* system clock rate (CLKIN) - equal to the 60x and local bus speed */
144 #define CONFIG_8260_CLKIN 64000000 /* in Hz */
146 #if defined(CONFIG_CONS_NONE) || defined(CONFIG_CONS_USE_EXTC)
147 #define CONFIG_BAUDRATE 230400
149 #define CONFIG_BAUDRATE 9600
152 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
153 #undef CONFIG_SYS_LOADS_BAUD_CHANGE /* don't allow baudrate change */
155 #undef CONFIG_WATCHDOG /* watchdog disabled */
160 #define CONFIG_BOOTP_SUBNETMASK
161 #define CONFIG_BOOTP_GATEWAY
162 #define CONFIG_BOOTP_HOSTNAME
163 #define CONFIG_BOOTP_BOOTPATH
164 #define CONFIG_BOOTP_BOOTFILESIZE
168 * Command line configuration.
170 #include <config_cmd_default.h>
172 #define CONFIG_CMD_BEDBUG
173 #define CONFIG_CMD_DATE
174 #define CONFIG_CMD_DHCP
175 #define CONFIG_CMD_EEPROM
176 #define CONFIG_CMD_I2C
177 #define CONFIG_CMD_NFS
178 #define CONFIG_CMD_SNTP
181 #define CONFIG_CMD_PCI
185 * Miscellaneous configurable options
187 #define CONFIG_SYS_LONGHELP /* undef to save memory */
188 #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
189 #if defined(CONFIG_CMD_KGDB)
190 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
192 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
194 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
195 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */
196 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
198 #define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */
199 #define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
201 #define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
203 #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
205 #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
207 #define CONFIG_SYS_RESET_ADDRESS 0xFDFFFFFC /* "bad" address */
210 * For booting Linux, the board info and command line data
211 * have to be in the first 8 MB of memory, since this is
212 * the maximum mapped by the Linux kernel during initialization.
214 #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
216 /*-----------------------------------------------------------------------
217 * Flash and Boot ROM mapping
219 #ifdef CONFIG_FLASH_32MB
220 #define CONFIG_SYS_FLASH0_BASE 0x40000000
221 #define CONFIG_SYS_FLASH0_SIZE 0x02000000
223 #define CONFIG_SYS_FLASH0_BASE 0xFF000000
224 #define CONFIG_SYS_FLASH0_SIZE 0x00800000
226 #define CONFIG_SYS_BOOTROM_BASE 0xFF800000
227 #define CONFIG_SYS_BOOTROM_SIZE 0x00080000
228 #define CONFIG_SYS_DOC_BASE 0xFF800000
229 #define CONFIG_SYS_DOC_SIZE 0x00100000
231 /* Flash bank size (for preliminary settings)
233 #define CONFIG_SYS_FLASH_SIZE CONFIG_SYS_FLASH0_SIZE
235 /*-----------------------------------------------------------------------
238 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of memory banks */
239 #ifdef CONFIG_FLASH_32MB
240 #define CONFIG_SYS_MAX_FLASH_SECT 135 /* max num of sects on one chip */
242 #define CONFIG_SYS_MAX_FLASH_SECT 128 /* max num of sects on one chip */
244 #define CONFIG_SYS_FLASH_ERASE_TOUT 240000 /* Flash Erase Timeout (in ms) */
245 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */
248 /* Start port with environment in flash; switch to EEPROM later */
249 #define CONFIG_ENV_IS_IN_FLASH 1
250 #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE+0x40000)
251 #define CONFIG_ENV_SIZE 0x40000
252 #define CONFIG_ENV_SECT_SIZE 0x40000
254 /* Final version: environment in EEPROM */
255 #define CONFIG_ENV_IS_IN_EEPROM 1
256 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x58
257 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
258 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4
259 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */
260 #define CONFIG_ENV_OFFSET 512
261 #define CONFIG_ENV_SIZE (2048 - 512)
264 /*-----------------------------------------------------------------------
265 * Hard Reset Configuration Words
267 * if you change bits in the HRCW, you must also change the CONFIG_SYS_*
268 * defines for the various registers affected by the HRCW e.g. changing
269 * HRCW_DPPCxx requires you to also change CONFIG_SYS_SIUMCR.
271 #if defined(CONFIG_BOOT_ROM)
272 #define CONFIG_SYS_HRCW_MASTER (HRCW_BPS01 | HRCW_CIP | HRCW_ISB100 | HRCW_BMS)
274 #define CONFIG_SYS_HRCW_MASTER (HRCW_CIP | HRCW_ISB100 | HRCW_BMS)
277 /* no slaves so just fill with zeros */
278 #define CONFIG_SYS_HRCW_SLAVE1 0
279 #define CONFIG_SYS_HRCW_SLAVE2 0
280 #define CONFIG_SYS_HRCW_SLAVE3 0
281 #define CONFIG_SYS_HRCW_SLAVE4 0
282 #define CONFIG_SYS_HRCW_SLAVE5 0
283 #define CONFIG_SYS_HRCW_SLAVE6 0
284 #define CONFIG_SYS_HRCW_SLAVE7 0
286 /*-----------------------------------------------------------------------
287 * Internal Memory Mapped Register
289 #define CONFIG_SYS_IMMR 0xF0000000
291 /*-----------------------------------------------------------------------
292 * Definitions for initial stack pointer and data area (in DPRAM)
294 #define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR
295 #define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in DPRAM */
296 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
297 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
299 /*-----------------------------------------------------------------------
300 * Start addresses for the final memory configuration
301 * (Set up by the startup code)
302 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
304 * 60x SDRAM is mapped at CONFIG_SYS_SDRAM_BASE, local SDRAM
305 * is mapped at SDRAM_BASE2_PRELIM.
307 #define CONFIG_SYS_SDRAM_BASE 0x00000000
308 #define CONFIG_SYS_FLASH_BASE CONFIG_SYS_FLASH0_BASE
309 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
310 #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
311 #define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc()*/
313 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
314 # define CONFIG_SYS_RAMBOOT
318 #define CONFIG_PCI_PNP
319 #define CONFIG_EEPRO100
320 #define CONFIG_SYS_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */
323 /*-----------------------------------------------------------------------
324 * Cache Configuration
326 #define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC8260 CPU */
327 #if defined(CONFIG_CMD_KGDB)
328 # define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */
331 /*-----------------------------------------------------------------------
332 * HIDx - Hardware Implementation-dependent Registers 2-11
333 *-----------------------------------------------------------------------
334 * HID0 also contains cache control - initially enable both caches and
335 * invalidate contents, then the final state leaves only the instruction
336 * cache enabled. Note that Power-On and Hard reset invalidate the caches,
337 * but Soft reset does not.
339 * HID1 has only read-only information - nothing to set.
341 #define CONFIG_SYS_HID0_INIT (HID0_ICE|HID0_DCE|HID0_ICFI|HID0_DCI|\
343 #define CONFIG_SYS_HID0_FINAL (HID0_ICE|HID0_IFEM|HID0_ABE)
344 #define CONFIG_SYS_HID2 0
346 /*-----------------------------------------------------------------------
347 * RMR - Reset Mode Register 5-5
348 *-----------------------------------------------------------------------
349 * turn on Checkstop Reset Enable
351 #define CONFIG_SYS_RMR RMR_CSRE
353 /*-----------------------------------------------------------------------
354 * BCR - Bus Configuration 4-25
355 *-----------------------------------------------------------------------
358 #define BCR_APD01 0x10000000
359 #define CONFIG_SYS_BCR (BCR_APD01|BCR_ETM|BCR_LETM) /* 8260 mode */
361 /*-----------------------------------------------------------------------
362 * SIUMCR - SIU Module Configuration 4-31
363 *-----------------------------------------------------------------------
366 #define CONFIG_SYS_SIUMCR (SIUMCR_DPPC00|SIUMCR_APPC10|SIUMCR_CS10PC01)
368 #define CONFIG_SYS_SIUMCR (SIUMCR_DPPC10|SIUMCR_APPC10)
372 /*-----------------------------------------------------------------------
373 * SYPCR - System Protection Control 4-35
374 * SYPCR can only be written once after reset!
375 *-----------------------------------------------------------------------
376 * Watchdog & Bus Monitor Timer max, 60x Bus Monitor enable
378 #if defined(CONFIG_WATCHDOG)
379 #define CONFIG_SYS_SYPCR (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\
380 SYPCR_SWRI|SYPCR_SWP|SYPCR_SWE)
382 #define CONFIG_SYS_SYPCR (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\
383 SYPCR_SWRI|SYPCR_SWP)
384 #endif /* CONFIG_WATCHDOG */
386 /*-----------------------------------------------------------------------
387 * TMCNTSC - Time Counter Status and Control 4-40
388 *-----------------------------------------------------------------------
389 * Clear once per Second and Alarm Interrupt Status, Set 32KHz timersclk,
390 * and enable Time Counter
392 #define CONFIG_SYS_TMCNTSC (TMCNTSC_SEC|TMCNTSC_ALR|TMCNTSC_TCF|TMCNTSC_TCE)
394 /*-----------------------------------------------------------------------
395 * PISCR - Periodic Interrupt Status and Control 4-42
396 *-----------------------------------------------------------------------
397 * Clear Periodic Interrupt Status, Set 32KHz timersclk, and enable
400 #define CONFIG_SYS_PISCR (PISCR_PS|PISCR_PTF|PISCR_PTE)
402 /*-----------------------------------------------------------------------
403 * SCCR - System Clock Control 9-8
404 *-----------------------------------------------------------------------
406 #define CONFIG_SYS_SCCR (SCCR_DFBRG00)
408 /*-----------------------------------------------------------------------
409 * RCCR - RISC Controller Configuration 13-7
410 *-----------------------------------------------------------------------
412 #define CONFIG_SYS_RCCR 0
415 * Init Memory Controller:
417 * Bank Bus Machine PortSz Device
418 * ---- --- ------- ------ ------
419 * 0 60x GPCM 64 bit FLASH
420 * 1 60x SDRAM 64 bit SDRAM
424 /* Initialize SDRAM on local bus
426 #define CONFIG_SYS_INIT_LOCAL_SDRAM
429 /* Minimum mask to separate preliminary
430 * address ranges for CS[0:2]
432 #define CONFIG_SYS_MIN_AM_MASK 0xC0000000
435 * we use the same values for 32 MB and 128 MB SDRAM
436 * refresh rate = 7.73 uS (64 MHz Bus Clock)
438 #define CONFIG_SYS_MPTPR 0x2000
439 #define CONFIG_SYS_PSRT 0x0E
441 #define CONFIG_SYS_MRS_OFFS 0x00000000
444 #if defined(CONFIG_BOOT_ROM)
446 * Bank 0 - Boot ROM (8 bit wide)
448 #define CONFIG_SYS_BR0_PRELIM ((CONFIG_SYS_BOOTROM_BASE & BRx_BA_MSK)|\
453 #define CONFIG_SYS_OR0_PRELIM (P2SZ_TO_AM(CONFIG_SYS_BOOTROM_SIZE) |\
461 * Bank 1 - Flash (64 bit wide)
463 #define CONFIG_SYS_BR1_PRELIM ((CONFIG_SYS_FLASH_BASE & BRx_BA_MSK) |\
468 #define CONFIG_SYS_OR1_PRELIM (P2SZ_TO_AM(CONFIG_SYS_FLASH_SIZE) |\
475 #else /* ! CONFIG_BOOT_ROM */
478 * Bank 0 - Flash (64 bit wide)
480 #define CONFIG_SYS_BR0_PRELIM ((CONFIG_SYS_FLASH_BASE & BRx_BA_MSK) |\
485 #define CONFIG_SYS_OR0_PRELIM (P2SZ_TO_AM(CONFIG_SYS_FLASH_SIZE) |\
493 * Bank 1 - Disk-On-Chip
495 #define CONFIG_SYS_BR1_PRELIM ((CONFIG_SYS_DOC_BASE & BRx_BA_MSK) |\
500 #define CONFIG_SYS_OR1_PRELIM (P2SZ_TO_AM(CONFIG_SYS_DOC_SIZE) |\
507 #endif /* CONFIG_BOOT_ROM */
512 #ifndef CONFIG_SYS_RAMBOOT
513 #define CONFIG_SYS_BR2_PRELIM ((CONFIG_SYS_SDRAM_BASE & BRx_BA_MSK) |\
518 /* SDRAM initialization values for 8-column chips
520 #define CONFIG_SYS_OR2_8COL (CONFIG_SYS_MIN_AM_MASK |\
522 ORxS_ROWST_PBI0_A9 |\
525 #define CONFIG_SYS_PSDMR_8COL (PSDMR_SDAM_A13_IS_A5 |\
526 PSDMR_BSMA_A14_A16 |\
527 PSDMR_SDA10_PBI0_A10 |\
535 /* SDRAM initialization values for 9-column chips
537 #define CONFIG_SYS_OR2_9COL (CONFIG_SYS_MIN_AM_MASK |\
539 ORxS_ROWST_PBI0_A7 |\
542 #define CONFIG_SYS_PSDMR_9COL (PSDMR_SDAM_A14_IS_A5 |\
543 PSDMR_BSMA_A13_A15 |\
544 PSDMR_SDA10_PBI0_A9 |\
552 #define CONFIG_SYS_OR2_PRELIM CONFIG_SYS_OR2_9COL
553 #define CONFIG_SYS_PSDMR CONFIG_SYS_PSDMR_9COL
555 #endif /* CONFIG_SYS_RAMBOOT */
557 #endif /* __CONFIG_H */